File "rules" has instructional text as comments near top.
2) Convert all text files in repo to LF line ending form.
Any checkout done with "rules" in play will convert the working
tree to native line ending, while keeping repo as LF line ending.
* Eeschema can generate this netlist format.
* Pcbnew can use (automatic identification) the current format or the new format.
* Cvpcb does not use yet the new format.
* A track is seen connected to a pad if the track end is inside the pad shape.
* Pads inside pads are now seen connected, if the center of the pad is *inside* the other pad.
* this is made to be sure a large copper area is shared by the 2 pads, and to keep algorithm fast.
(WxWidgets 2.9.1 seems call setlocale( LC_NUMERIC, "" ) when wxConfig read doubles stored in config, but forget to back to current locale.)
Note: perhaps there are some dialogs that need this call to SetLocaleTo_Default() ).
* Minor code cleanup in pcbnew/netlist.cpp
Eeschema: cleaning code. Start work to enhance annotation algorithm.
Already added an option to annotate using sheet number (sheet 1 uses numbers 100 to 199, sheet 2 uses 200 to 299..).
Works fine if deleting existing annotation, but needs work to be used when the existing annotation is kept .
Added: in file dialog, multiple file selection.
Added: Draw mode selector (in left toolbar):
Raw mode:
a Gerber image is drawn on screen without buffering.
Artifacts happen if there are negative items drawn, if more than one Gerber file is shown.
Stacked mode:
each Geber image is drawn in a buffer and after drawn on screen
No artifact with negative items.
Each Gerber image covers previous images.
OR mode (transparency mode):
each Geber image is drawn in a buffer and after drawn on screen
No artifact with negative items.
Each Gerber image is "ORed" with previous images, like in Pcbnew.
Try to optimize Draw function in buffered modes.
(Useful for PC that have problems with "blit" graphic function)
Fix minor issues.
In netlist generation, changed the rule to calculate netnames of nets with labels:
Previously, named nets (i.e. nets with local, hierarchical or global labels) have their name
defined by the first label found in list.
So net names could be changed without really changing the schematic.
Now the names are calculated from the rules (by priority order) :
1 - use the most top level labels in hierarchies.
2 - use global labels first, local labels next (hidden power pins names are global labels).
3 - use alphabetic sort (so, if GND and AGND are connected, the net will be always named AGND,
and adding a VSS connection cannot change the net name)
So power nets and nets that have more than one label cannot have their netname changed
if there is no actual change relative to these nets names in schematic
jean-pierre charras
Dick Hollenbeck
Marco Serantoni
jp
charras