ab350cbfaa
qa: some trivial test cases for the P&S regressions
2022-10-31 11:49:31 +01:00
5eca8dd8de
Undo hardcoding swapping of diode pins
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Revert commits d1e2acd370b4d1aacff508fb
2022-10-30 11:01:59 +01:00
cff508fb3b
Sim: Reverse diode model pin order to match diode symbols
2022-10-28 14:01:09 +02:00
f31feaac42
Sim: Commit forgotten files
2022-10-27 08:08:14 +02:00
00c04e74ed
Sim QA: Test LTspice parameters and ako models of BJTs
2022-10-20 04:00:33 +02:00
c4fc9c1b16
Sim QA: Add tests for AKO and LTspice diodes
2022-10-19 06:56:21 +02:00
42acabb5a9
Fix a mistake in uopamp.lib.spice
2022-10-18 22:38:49 +02:00
ae671c07e1
Commit missing uopamp.lib.spice
2022-10-18 17:38:23 +02:00
e5704d7058
Update uopamp.lib.spice to be the same in all QA tests
2022-10-18 06:15:54 +02:00
c8e13813d9
Sim: Rename Sim_Disabled field to Sim_Enable
2022-10-16 00:49:44 +02:00
c3d5b3b3e5
Sim: Only store device type in reference, not full model type
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Instead of Reference="VSIN1", Value="dc=1 ampl=2 f=3", it's now
Reference="V1", Value="SIN dc=1 ampl=2 f=3".
2022-10-15 19:36:26 +02:00
9424b166d0
Add regression test case for 12609.
2022-10-09 23:31:26 +01:00
0150655ed3
Fix missing DRC check with via
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When the via is first and not second in our ordering, the hole-copper
clearance was not checked as the track did not have a hole.
We also calculated the NPTH-via clearance incorrectly in the inspector
2022-09-20 13:43:01 -07:00
60374daa49
Fix ERC global label unit tests
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Need to test all units in the subgraph as there are chances that the
subgraph might have more than one label, which needs to be consistently
handled
2022-09-12 13:16:45 -07:00
0e0d1a34f5
Sim: Spice grammar fixes
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- Fix parsing .model lines with model names containingnon-alphanumeric
characters like - and _,
- Fix parsing libraries in which EOF is not preceded by a newline.
Fixes https://gitlab.com/kicad/code/kicad/issues/12394
2022-09-12 04:05:17 +02:00
e56635a02b
Sim: Add mutual inductor model
2022-09-11 19:23:01 +02:00
f2e3329617
Add ERC QA tests
2022-09-09 17:21:57 -07:00
a5246a6df7
DbLib: Support showing field names
2022-09-04 13:01:32 -04:00
b225e53135
Sim QA: Test raw model with fewer pins than its symbol
2022-09-02 16:42:15 +02:00
121fad63ab
Sim QA: Add Directives test
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This test checks whether Spice directives placed in schematics as text
objects are properly included in the generated Spice netlist.
2022-08-31 09:41:35 +02:00
bd6c153ad9
Sim: Implement "enum" model parameters for switches
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Displayed in Sim Model Dialog parameter grid as a dropdown
(wxEnumProperty).
2022-08-30 09:45:49 +02:00
385e5deaaa
Add Switches sim QA test
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Tests voltage switches. Current switches will be tested as well once
they're fixed to work with .probe alli command in Ngspice.
2022-08-29 04:30:21 +02:00
ae6a2a6443
ADDED: Database libraries MVP
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Allows placing parts from an external database that reference symbols from another loaded library.
Includes:
- nanodbc wrapper
- database schematic library plugin
- basic tests
Fixes https://gitlab.com/kicad/code/kicad/-/issues/7436
2022-08-26 10:51:13 -04:00
103b8a0d2c
Update the Opamp test to use a symbol with unordered pins
2022-08-26 04:36:48 +02:00
c6defadb78
Add Fliege filter Spice netlist exporter test
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Which we use to test multi-part symbols, as Fliege filter has two op
amps.
2022-08-25 08:47:31 +02:00
8a6a0ff7dc
Allow inferred voltage/current sources to have a single float in Value
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Update Opamp test to use this feature.
2022-08-24 06:19:38 +02:00
b9461f2ba7
Re-enable tests for zones
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Avoid invalid substantial checks triggered by signed floating point
zeros. Adds a QA check to ensure zone-self checks are maintained
2022-08-18 17:06:29 -07:00
b6f6d1ef81
Sim QA: Add legacy_opamp test to check legacy subckt fields
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In particular, Spice_Node_Sequence needed some additional coverage.
2022-08-11 21:23:05 +02:00
c669d55eb8
Sim QA: Use uopamp_lvl2 instead of uopamp_lvl1 in Opamp test
2022-08-11 18:32:20 +02:00
cc1e99ff5d
QA test: annotate rlc.kicad_sch. only annotated schematic give reliable result.
2022-08-10 11:16:07 +02:00
128fedec1a
Sim QA: Commit the missing rlc unit test project
2022-08-08 22:05:15 +02:00
f6771ed789
Sim QA: Add rlc project to test RLC ideal model inference
2022-08-08 17:06:50 +02:00
9e7bc585ef
Sim QA: Test only specific hardcoded points of the results
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We don't want to assume Ngspice results to be very deterministic.
2022-08-04 21:07:43 +02:00
800b512fe8
Further cut off digits down to one after period in sim QA
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We just want to make sure our netlist exporter works. Being
deterministic is the simulator's job, not ours, though perhaps we should
investigate that too eventually.
2022-08-03 16:25:00 +02:00
37209bb496
Try to fix Ngspice QA by resampling and cutting off value digits
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`linearize` command resamples the data. Fourth and further digits from
decimal point are cut off by using `wrdata` command instead of `write`.
Oddly, "sources" unit test is not working (so it's still uncommented) --
some substantially different values are generated when generating the
reference with standalone Ngspice.
2022-08-03 14:28:01 +02:00
cc78997386
Add annular ring test and fix footprint/pad mismatch in other test.
2022-08-01 21:50:35 +01:00
203d778c92
Fix test failure.
2022-08-01 21:42:02 +01:00
0304ad4494
Move connection width testing to rule system.
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Also copies connection width progress reporting architecture over to
the sliver checker.
2022-08-01 13:09:51 +01:00
d7e5254c17
Comment out failing sim QA tests
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The tests will probably have to test against manually specified bounds
and inexact points.
Added a previously mistakenly uncommitted cmos_not.csv.
2022-07-30 09:19:20 +02:00
7cf5138c63
Sim: Bugfixes, mostly for MS Windows compilation errors
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Unfortunately, Windows headers define a lot of macros for common words,
so we had to rename some enums to not collide.
We also fix some of the many bugs related to the new simulation
architecture and the Spice Model Editor dialog.
2022-07-30 02:25:34 +00:00
739b9255d9
Sim Model Editor improvements
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- Tab-switching,
- Automatic expansion of categories on tab-switch,
- Various minor simulation improvements,
- Various new simulation-related bugfixes.
2022-07-30 02:25:34 +00:00
6984f63af8
Sim: Transmission line models
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Implement transmission line models and perform some adjustments to
the current models. Add some QA tests.
2022-07-30 02:25:34 +00:00
fe38c622a9
Sim: Improvements to model serialization
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Don't serialize parameters in certain models for default values. Infer
models from Value field for some kinds of models. Resolve synonyms when
loading models from Spice libraries.
2022-07-30 02:25:34 +00:00
6450ec6b85
Sim: Spice netlist exporter rewrite
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Rewrite the spice exporter to work with the new simulation model
architecture and data model, with many bugfixes related to the latter
two along the way.
2022-07-30 02:25:34 +00:00
79fa911e0e
Fix various typos
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Found via `codespell -q 3 -S *.po,./thirdparty,./Documentation/changelogs -L aactual,acount,aline,alocation,alog,anormal,anumber,aother,apoints,aparent,aray,ba,busses,dout,einstance,leaded,modul,ontext,ot,overide,serie,te,,tesselate,tesselator,tht`
2022-07-21 16:31:41 +00:00
3081023b5e
ADDED: Minimum copper connection width DRC check
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Checks all copper connections in each net/layer for minimum width
setting.
Fixes https://gitlab.com/kicad/code/kicad/issues/9870
2022-07-11 19:26:56 +00:00
ce4cedb5b4
Regression test case for 11814.
2022-06-15 11:45:29 +01:00
09c9bc3037
Fix net ordering in gold file.
2022-05-27 21:28:17 +01:00
e9e1878d96
Attempt to fix eeschema tests.
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(Slashes in netnames must be escaped or else we think they're path
separators.)
2022-05-27 17:53:11 +01:00
55f22c526a
Fix annotation of incomplete multi-unit symbols and re-annotation of duplicates
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/11496
2022-05-26 09:23:36 +00:00
Tomasz Wlostowski
Mikolaj Wielgus
Jeff Young
Seth Hillbrand
Jon Evans
jean-pierre charras
luz paz
Roberto Fernandez Bautista