141b332d4f
Add regression test for 13988.
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(cherry picked from commit 35ca3e7264
2023-03-25 15:37:57 +00:00
b82020722b
Eeschema netlist output: Propagate NC across hierarchical schematics
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Fixes #12580
Additionally does not export no_connect netlist annotation on pins
which are both connected to another pin and a NC item, unless all
connected pins are stacked at the symbol level.
Adds testing of pin types to netlist QA unit tests.
(cherry picked from commit 9dca70a773
2023-03-06 16:22:25 -08:00
05d425ea88
Add 12505 to the regression test suite.
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Fixes https://gitlab.com/kicad/code/kicad/issues/12505
(cherry picked from commit d96598c87c
2023-03-06 10:27:46 +00:00
9ca539b416
Remove TL072.031 from regression test.
2023-01-31 14:57:52 +00:00
fef3274e8e
Eeschema: ERC checks handle connections between a common sub-circuit
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Fixes #10926
Contains the following changes:
- Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
comparison between items causing ERC violations (e.g. pins) when associated
with a SCH_SHEET_PATH context.
- Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
which caused an ERC violation. This allows correct display of markers on the
sheets of interest only, and allows correct naming resolution and cross-probing
from the ERC dialog.
- Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
resolves component references across heirarchical sheets using the associated
SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
correctly in the ERC results tree.
- Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
an ERC violation.
- Increments the schematic file version.
- When loading a schematic with legacy ERC exclusions, discards those of type
ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
information which is now stored with these exclusions (sheet paths for error
location and related items). Requiring users to (once) re-add exclusions is
preferable to silently incorrectly matching new ERC issues to legacy exclusions.
2023-01-24 14:11:01 +00:00
f6d9a2574b
Fix a QA simulation test on W1/msys2:
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- Gives a bigger relative tolerance when comparing 2 values to pass some tests
- Fix error in test_sim_regressions.cpp for 3 TestNetlist() calls
2023-01-22 16:52:11 +01:00
241dc0d96b
Add SPICE regression test.
2023-01-21 19:32:25 +00:00
259e382041
Add simulation regression test for legacy fixups.
2023-01-21 19:32:25 +00:00
e218c7109b
Test case for immediate SBCKT models.
2023-01-21 19:32:25 +00:00
6053b86a24
Add new spice regression test for windows path separators.
2023-01-21 19:32:25 +00:00
fc86998bf6
Ensure duplicate pin names get unique nets
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Same pin name != same net name unless the pins are explicitly connected
Also add pin number to all unconnected pads ensuring they have unique
nets
Fixes https://gitlab.com/kicad/code/kicad/issues/13236
2023-01-04 11:32:15 -08:00
a3a2e2e5b1
Update demos and legacy qa files SpiceMapping -> Spice_Node_Sequence.
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Also removes migration in the code as it will no longer be needed.
2022-12-19 12:04:53 +00:00
ba11de6e66
Update QA test schematics with valid and invalid variants
2022-12-09 02:14:05 +00:00
63da407345
Add tests for no connect flag
2022-12-09 02:14:05 +00:00
b025b103de
Sim Model Editor: Make the VBIC model the first BJT model to select
2022-11-29 10:13:20 +01:00
484620eeb5
Sim QA: Add test for VDMOS
2022-11-29 09:48:01 +01:00
5fb191e4d6
Sim QA: Test all BJT parameters in each model
2022-11-28 09:49:48 +01:00
26644952a4
Sim QA: Test all diode parameters
2022-11-28 08:01:50 +01:00
f2fb734e06
Sim QA: Add test for Numparam expressions inside .subckt
2022-11-27 06:32:17 +01:00
08d37d2795
Sim QA: Add Spice .subckt parsing tests
2022-11-26 10:24:11 +01:00
9766351ee6
Sim: Update QA to tests to match the new model upgrade scheme
2022-11-25 05:38:21 +01:00
833146cf50
Sim QA: Fix QA errors
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Let's not allow units in fields for now. (is 1m one meter or one milli?)
2022-11-22 21:18:01 +01:00
e9fe59a28c
Sim: Rename the missed Sim_* fields to Sim.*
2022-11-21 03:33:11 +01:00
059ca8fc48
Sim: Rename Sim_* fields to Sim.*
2022-11-20 03:37:54 +01:00
e7c43ca20a
Sim: Remove inference from Reference and Value
2022-11-18 08:39:15 +01:00
5eca8dd8de
Undo hardcoding swapping of diode pins
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Revert commits d1e2acd370b4d1aacff508fb
2022-10-30 11:01:59 +01:00
cff508fb3b
Sim: Reverse diode model pin order to match diode symbols
2022-10-28 14:01:09 +02:00
f31feaac42
Sim: Commit forgotten files
2022-10-27 08:08:14 +02:00
00c04e74ed
Sim QA: Test LTspice parameters and ako models of BJTs
2022-10-20 04:00:33 +02:00
c4fc9c1b16
Sim QA: Add tests for AKO and LTspice diodes
2022-10-19 06:56:21 +02:00
42acabb5a9
Fix a mistake in uopamp.lib.spice
2022-10-18 22:38:49 +02:00
ae671c07e1
Commit missing uopamp.lib.spice
2022-10-18 17:38:23 +02:00
e5704d7058
Update uopamp.lib.spice to be the same in all QA tests
2022-10-18 06:15:54 +02:00
c8e13813d9
Sim: Rename Sim_Disabled field to Sim_Enable
2022-10-16 00:49:44 +02:00
c3d5b3b3e5
Sim: Only store device type in reference, not full model type
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Instead of Reference="VSIN1", Value="dc=1 ampl=2 f=3", it's now
Reference="V1", Value="SIN dc=1 ampl=2 f=3".
2022-10-15 19:36:26 +02:00
60374daa49
Fix ERC global label unit tests
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Need to test all units in the subgraph as there are chances that the
subgraph might have more than one label, which needs to be consistently
handled
2022-09-12 13:16:45 -07:00
0e0d1a34f5
Sim: Spice grammar fixes
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- Fix parsing .model lines with model names containingnon-alphanumeric
characters like - and _,
- Fix parsing libraries in which EOF is not preceded by a newline.
Fixes https://gitlab.com/kicad/code/kicad/issues/12394
2022-09-12 04:05:17 +02:00
e56635a02b
Sim: Add mutual inductor model
2022-09-11 19:23:01 +02:00
f2e3329617
Add ERC QA tests
2022-09-09 17:21:57 -07:00
b225e53135
Sim QA: Test raw model with fewer pins than its symbol
2022-09-02 16:42:15 +02:00
121fad63ab
Sim QA: Add Directives test
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This test checks whether Spice directives placed in schematics as text
objects are properly included in the generated Spice netlist.
2022-08-31 09:41:35 +02:00
bd6c153ad9
Sim: Implement "enum" model parameters for switches
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Displayed in Sim Model Dialog parameter grid as a dropdown
(wxEnumProperty).
2022-08-30 09:45:49 +02:00
385e5deaaa
Add Switches sim QA test
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Tests voltage switches. Current switches will be tested as well once
they're fixed to work with .probe alli command in Ngspice.
2022-08-29 04:30:21 +02:00
103b8a0d2c
Update the Opamp test to use a symbol with unordered pins
2022-08-26 04:36:48 +02:00
c6defadb78
Add Fliege filter Spice netlist exporter test
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Which we use to test multi-part symbols, as Fliege filter has two op
amps.
2022-08-25 08:47:31 +02:00
8a6a0ff7dc
Allow inferred voltage/current sources to have a single float in Value
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Update Opamp test to use this feature.
2022-08-24 06:19:38 +02:00
b6f6d1ef81
Sim QA: Add legacy_opamp test to check legacy subckt fields
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In particular, Spice_Node_Sequence needed some additional coverage.
2022-08-11 21:23:05 +02:00
c669d55eb8
Sim QA: Use uopamp_lvl2 instead of uopamp_lvl1 in Opamp test
2022-08-11 18:32:20 +02:00
cc1e99ff5d
QA test: annotate rlc.kicad_sch. only annotated schematic give reliable result.
2022-08-10 11:16:07 +02:00
128fedec1a
Sim QA: Commit the missing rlc unit test project
2022-08-08 22:05:15 +02:00
Jeff Young
JamesJCode
jean-pierre charras
Seth Hillbrand
Barabas Raffai
Mikolaj Wielgus