Commit Graph

83 Commits

Author SHA1 Message Date
Jeff Young 2d15067453 ADDED allow update of teardrops before running DRC.
Fixes https://gitlab.com/kicad/code/kicad/issues/14264
2023-04-15 12:18:41 +01:00
Jeff Young 461def2719 Move automatic dimension processing inside PCB_DIMENSION_BASE.
Also move dimension precision to an enum so it can get a proper dropdown
in the properties inspector.
2023-03-05 15:19:06 +00:00
Jon Evans 1215a967e2 Set copper edge clearance to a more reasonable default 2023-02-24 20:43:28 -05:00
Marek Roszko aacc9746e3 Yeet the last of wxSize/wxPoint to stop leaking gdicmn everywhere 2023-02-18 22:57:18 -05:00
kliment ef8062bfad pcbnew: Change some of the default settings in board setup and netclasses 2023-01-29 23:20:40 +00:00
Jeff Young 86938aa425 Read, write and process the board-wide Allow soldermask bridges in FPs. 2022-08-14 22:56:29 +01:00
Jeff Young a9536b5de9 CHANGED netclass assignments now done via canvas or via patterns. 2022-08-14 22:56:29 +01:00
Seth Hillbrand a9a5136c1c Always allow blind/buried/micro vias
Removes a nanny setting that prevented the use of
blind/buried/micro-vias without a checkbox.  If the designer does not
want microvias in their board, they simply do not place microvias.
2022-07-12 19:47:31 -07:00
Seth Hillbrand 3081023b5e ADDED: Minimum copper connection width DRC check
Checks all copper connections in each net/layer for minimum width
setting.

Fixes https://gitlab.com/kicad/code/kicad/issues/9870
2022-07-11 19:26:56 +00:00
Jeff Young 3deaf902bb Retire the V5 zone fill algorithm.
Fixes https://gitlab.com/kicad/code/kicad/issues/10578
2022-02-11 13:10:52 +00:00
jean-pierre charras 1b42152ba0 Teardrops: store parameters in BOARD_DESIGN_SETTINGS. 2022-01-23 10:57:08 +01:00
Marek Roszko 347e03363a Convert wxPoint/wxSize starting from EDA_RECT usages 2022-01-01 11:30:33 -05:00
Jeff Young dabc75bee8 Source 3D dimensions from board stackup.
Also includes a performance improvemnt by caching the 3D model matrices.
2021-12-24 21:10:28 +00:00
Jeff Young ef10b36948 Add mask-to-copper clearance parameter and rename mask margin. 2021-12-24 12:36:41 +00:00
Jeff Young a1e3f2b188 Starved thermals DRC checking.
ADDED min_resolved_spokes constraint.
ADDED "Thermal relief connection to zone incomplete" violation.

Fixes https://gitlab.com/kicad/code/kicad/issues/2183
2021-12-23 22:30:42 +00:00
Jeff Young 2001d08186 Add DRC tests for text height and text thickness.
Fixes https://gitlab.com/kicad/code/kicad/issues/8683
2021-12-23 19:18:45 +00:00
Mike Williams 956ac871c3 PCB Editor: changes to track width overrides starting track width
Fixes: https://gitlab.com/kicad/code/kicad/-/issues/8797
Fixes: https://gitlab.com/kicad/code/kicad/-/issues/8797
2021-12-15 23:32:48 +00:00
Jeff Young 1f9e75f676 Pad with hole same size or larger than pad isn't flashed.
... even if it's marked as being on copper layers.

Also changes the default hole clearance to 0.25mm.

Fixes https://gitlab.com/kicad/code/kicad/issues/9901
2021-12-08 23:16:33 +00:00
Jon Evans 75d75799f7 Move to getters/setters for aux and grid origin
Fixes https://gitlab.com/kicad/code/kicad/-/issues/8836
2021-11-08 22:36:40 -05:00
Jeff Young 81fc710a5d Use consistent terminology.
Fixes https://gitlab.com/kicad/code/kicad/issues/8681
2021-06-26 10:11:41 +01:00
Marek Roszko 10e60acf34 Clean up including of board_design_settings.h 2021-06-06 15:03:42 -04:00
Jon Evans bc6b9b527a Allow stackup height to be excluded from length calculations
Fixes https://gitlab.com/kicad/code/kicad/-/issues/8384
2021-05-10 22:11:58 -04:00
Wayne Stambaugh 2ae264751f Rename class_board_stackup.{h|cpp} to board_stackup.{h|cpp}. 2021-04-16 17:07:06 -04:00
Jeff Young 3e9eb3c8ac More complete fix for crasher JP found.
Fixes https://gitlab.com/kicad/code/kicad/issues/7806
2021-03-05 15:30:52 +00:00
Jon Evans 68f958145d Gracefully handle lack of diff pair settings
Fixes https://gitlab.com/kicad/code/kicad/-/issues/7806
2021-03-05 09:09:56 -05:00
Dominik Wernberger ac94d72d2d Add more const specifiers 2021-01-12 20:51:31 +00:00
Wayne Stambaugh bf00ebee3b Header clean up round 1. 2020-12-18 09:04:26 -05:00
Jeff Young 3b35bfc0a5 Don't write out synthetic severities (they're headings).
Fixes https://gitlab.com/kicad/code/kicad/issues/6726
2020-12-14 13:34:53 +00:00
Jeff Young e09271ca0e Fixes for hole clearance and hole-to-hole tests.
1) Separate out CONSTRAINT types
2) Filter both source and dest pads/vias for drilled holes when doing
   hole-to-hole checks.  We were checking the items being put into the
   DRC RTree, but not the items we were scanning.
3) Add hole clearance to Board Setup Constraints panel.

Fixes https://gitlab.com/kicad/code/kicad/issues/6546

Fixes https://gitlab.com/kicad/code/kicad/issues/4683
2020-11-29 23:35:23 +00:00
jean-pierre charras a431fd99ca Fix crash when converting a Eagle board to a Kicad board.
During conversion a illegal layer number was used without filtering
2020-11-17 10:23:44 +01:00
Jeff Young 61bca4aaa4 A bit of "module" erradication, nameing conventions, and formatting. 2020-11-14 21:21:54 +00:00
Jeff Young f5443de7f9 D_PAD -> PAD. 2020-11-13 15:16:24 +00:00
Jeff Young 84dd5108ba Remove some "class_" prefixes from files. 2020-11-13 15:16:23 +00:00
Jeff Young f7333ad64a Update some classnames including archaic zone names. 2020-11-12 10:31:25 +00:00
Jeff Young 32dffd27ab Add silk clearance to board setup constraints. 2020-10-12 18:31:00 +01:00
Jeff Young 614d452f12 Resolve trackwidth[0]/viasize[0] to be the netclass values.
If we don't have a netclass use the default netclass.

Fixes https://gitlab.com/kicad/code/kicad/issues/5957
2020-10-11 00:54:49 +01:00
Jeff Young 04c4012ee6 Make track/via sizes UI more predictable and compatible with DRC.
Two main changes: netclass values need to go through the DRC engine
so they can interact with other rules.  They're also now dependent
on the layer being routed as well as the start object.

Also make the controls adjust to each other better.  For instance,
copy-track-width needs to turn off when you select a particular
track width, and a particular track width needs to zero out when
you choose copy-track-width.

Fixes https://gitlab.com/kicad/code/kicad/issues/5951
2020-10-10 19:32:30 +01:00
Jon Evans 728c207105 Deduplicate settings migration handling 2020-10-05 23:21:57 -04:00
Jeff Young f340636f70 When knocking out higher-priority zone use fill, not outline.
Also fixes a bunch of naming issues, primarily with lowercase for
protected variables, but also some for consistency with other parts
of the code.

Also changes the zone fill radio buttons in Board Setup to be more
generic referring to legacy vs. current, and to have tooltips.

Fixes https://gitlab.com/kicad/code/kicad/issues/5583
2020-09-18 16:45:41 +01:00
Jeff Young e2e229da96 Finish exorcising the old DRC system.
This moves the various BOARD_ITEM calls to the new system, and make
the DRC_ENGINE long-lived so that it can field those queries.
2020-09-15 20:15:46 +01:00
Jon Evans 3940e20fcb Expose extension offset and zero suppression settings 2020-09-12 11:52:59 -04:00
Jon Evans 0e9997d9ca Add new dimension features to board design defaults 2020-09-11 21:12:36 -04:00
Jon Evans ae7877c6cb Migrate dimension precision 2020-09-11 21:12:36 -04:00
Jon Evans b11e315d10 Refactor DIMENSION to hide internal details; add some new properties
This is a board file format change to account for the new properties.
Also, we now only store the critical information about the dimension's
geometry in the board, rather than storing every drawn line.

The DIMENSION object is now an abstract base, and ALIGNED_DIMENSION
is the implementation that exists today (we will add more dimension
types in the future)
2020-09-11 21:12:36 -04:00
Jeff Young d1006138fd ADDED holeWallPlatingThickness to AdvancedCfg.
Used for zone filling and DRC hole collision testing.  Allows us to
calculate the actual hole size from the finish hole size.

Fixes https://gitlab.com/kicad/code/kicad/issues/5468
2020-09-03 16:00:07 +01:00
Jeff Young 38e9217d54 Consolidate all DRC epsilon/threshold values to a single advancedCfg setting.
Fixes https://gitlab.com/kicad/code/kicad/issues/5464
2020-09-03 15:03:09 +01:00
Jeff Young 305abb210f Add a mode to allow zone smoothing to produce external fillets.
Fixes https://gitlab.com/kicad/code/kicad/issues/5306
2020-08-30 15:20:59 +01:00
jean-pierre charras df4226f896 Settings management: try to fix full filename issues when using non ASCII7 chars.
The fix convert all std::string storing a path to wxString (unicode support)
wxString were already used at many place to store paths, but not all.
For internal calculations mixing char strings and wide char strings is a recipe
for bug: any missing conversion between UTF8 and wxString breaks paths.
2020-08-02 21:31:03 +02:00
Jeff Young 095937563b Hook libeval compiler up to rule parser
- convert expression string tokens to single-quote-delimited
- fix bug where netclass assignments weren't getting updated after
  board setup dialog
- move property manager rebuild to lazy evaluation
- improve performance with wider use of const&
- retire DRC_SELECTOR stuff
- use wxString for GUI stuff (particularly translated stuff)
- fix EqualTo() to return false instead of asserting when op types
  don't match
- fix buffer overruns with fixed-size string buffers
- make expression function calls case-insensitive
- integrate expression errors into rule parser
- produce more and better error messages
- keep BOARD_ITEM ptrs const as long as possible
- fix a couple of uninitialized variables
2020-07-20 22:11:53 +01:00
Jeff Young 741481591e NetClass settings for Eeschema.
ADDED Eeschema-specific netclass settings including wire and bus
thickness, color, and line style.

Netclasses override individual wire & bus colors and line styles.
If that proves an issue we might look at something more sophisticated
with inheritance.

Fixes https://gitlab.com/kicad/code/kicad/issues/4581
2020-07-08 21:23:25 +01:00