Commit Graph

69 Commits

Author SHA1 Message Date
Seth Hillbrand 7d9222926a Connectivity: Correct alias-based bus resolution
Aliases in bus resolution were being resolved without a path, making
them effectively global nets.  This applies the corrected path to the
bus members and adds a QA to catch this error
2023-06-02 14:25:26 -07:00
Seth Hillbrand 57f0150a23 Ensure _changed_ netlist is propagated
The propagation is currently (maybe not needed) limited to the global
name that is the source of the change.  We also need to propagate the
global name that is changed in case the global is set in a tree leaf and
not the root

Fixes https://gitlab.com/kicad/code/kicad/issues/14657

(cherry picked from commit 6e4de18e15)
2023-05-09 12:13:30 -07:00
jean-pierre charras 2bbff64a12 Fix compatibility of QA golden files with 7.0x version 2023-04-13 08:01:32 +02:00
Seth Hillbrand 68dfcddbe9 Allow bus elements to connect
Previously, bus elements that were not instantiated as individual nets
could not connect to each other.  This caused issues for complex
schematics where busses needed to connect to other busses with elements
that resolved to the same net names.  Functionally, this means mixing
bus elements, which we will replace with first-class elements in version
8 but currently can only be accomplished either by using bus aliases and
  this patch or by individually instantiating each bus element as a
local label

Fixes https://gitlab.com/kicad/code/kicad/issues/14300

(cherry picked from commit 16b4ec3c7e)
2023-04-12 16:10:50 +02:00
Seth Hillbrand 39dcd0a352 Handle nested netclass assignments
Netclass directives should not be overriden, instead hold our error
checking for actually missing nets

Fixes https://gitlab.com/kicad/code/kicad/issues/14494

(cherry picked from commit 012737593b)
2023-04-06 17:38:42 -07:00
Jeff Young 141b332d4f Add regression test for 13988.
(cherry picked from commit 35ca3e7264)
2023-03-25 15:37:57 +00:00
JamesJCode b82020722b Eeschema netlist output: Propagate NC across hierarchical schematics
Fixes #12580

Additionally does not export no_connect netlist annotation on pins
which are both connected to another pin and a NC item, unless all
connected pins are stacked at the symbol level.

Adds testing of pin types to netlist QA unit tests.

(cherry picked from commit 9dca70a773)
2023-03-06 16:22:25 -08:00
Jeff Young 05d425ea88 Add 12505 to the regression test suite.
Fixes https://gitlab.com/kicad/code/kicad/issues/12505

(cherry picked from commit d96598c87c)
2023-03-06 10:27:46 +00:00
Jeff Young 9ca539b416 Remove TL072.031 from regression test. 2023-01-31 14:57:52 +00:00
JamesJCode fef3274e8e Eeschema: ERC checks handle connections between a common sub-circuit
Fixes #10926

Contains the following changes:

    - Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
      comparison between items causing ERC violations (e.g. pins) when associated
      with a SCH_SHEET_PATH context.

    - Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
      which caused an ERC violation. This allows correct display of markers on the
      sheets of interest only, and allows correct naming resolution and cross-probing
      from the ERC dialog.

    - Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
      resolves component references across heirarchical sheets using the associated
      SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
      correctly in the ERC results tree.

    - Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
      an ERC violation.

    - Increments the schematic file version.

    - When loading a schematic with legacy ERC exclusions, discards those of type
      ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
      ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
      information which is now stored with these exclusions (sheet paths for error
      location and related items). Requiring users to (once) re-add exclusions is
      preferable to silently incorrectly matching new ERC issues to legacy exclusions.
2023-01-24 14:11:01 +00:00
jean-pierre charras f6d9a2574b Fix a QA simulation test on W1/msys2:
- Gives a bigger relative tolerance when comparing 2 values to pass some tests
- Fix error in test_sim_regressions.cpp for 3 TestNetlist() calls
2023-01-22 16:52:11 +01:00
Jeff Young 241dc0d96b Add SPICE regression test. 2023-01-21 19:32:25 +00:00
Jeff Young 259e382041 Add simulation regression test for legacy fixups. 2023-01-21 19:32:25 +00:00
Jeff Young e218c7109b Test case for immediate SBCKT models. 2023-01-21 19:32:25 +00:00
Jeff Young 6053b86a24 Add new spice regression test for windows path separators. 2023-01-21 19:32:25 +00:00
Seth Hillbrand fc86998bf6 Ensure duplicate pin names get unique nets
Same pin name != same net name unless the pins are explicitly connected

Also add pin number to all unconnected pads ensuring they have unique
nets

Fixes https://gitlab.com/kicad/code/kicad/issues/13236
2023-01-04 11:32:15 -08:00
Jeff Young a3a2e2e5b1 Update demos and legacy qa files SpiceMapping -> Spice_Node_Sequence.
Also removes migration in the code as it will no longer be needed.
2022-12-19 12:04:53 +00:00
Seth Hillbrand ba11de6e66 Update QA test schematics with valid and invalid variants 2022-12-09 02:14:05 +00:00
Barabas Raffai 63da407345 Add tests for no connect flag 2022-12-09 02:14:05 +00:00
Mikolaj Wielgus b025b103de Sim Model Editor: Make the VBIC model the first BJT model to select 2022-11-29 10:13:20 +01:00
Mikolaj Wielgus 484620eeb5 Sim QA: Add test for VDMOS 2022-11-29 09:48:01 +01:00
Mikolaj Wielgus 5fb191e4d6 Sim QA: Test all BJT parameters in each model 2022-11-28 09:49:48 +01:00
Mikolaj Wielgus 26644952a4 Sim QA: Test all diode parameters 2022-11-28 08:01:50 +01:00
Mikolaj Wielgus f2fb734e06 Sim QA: Add test for Numparam expressions inside .subckt 2022-11-27 06:32:17 +01:00
Mikolaj Wielgus 08d37d2795 Sim QA: Add Spice .subckt parsing tests 2022-11-26 10:24:11 +01:00
Mikolaj Wielgus 9766351ee6 Sim: Update QA to tests to match the new model upgrade scheme 2022-11-25 05:38:21 +01:00
Mikolaj Wielgus 833146cf50 Sim QA: Fix QA errors
Let's not allow units in fields for now. (is 1m one meter or one milli?)
2022-11-22 21:18:01 +01:00
Mikolaj Wielgus e9fe59a28c Sim: Rename the missed Sim_* fields to Sim.* 2022-11-21 03:33:11 +01:00
Mikolaj Wielgus 059ca8fc48 Sim: Rename Sim_* fields to Sim.* 2022-11-20 03:37:54 +01:00
Mikolaj Wielgus e7c43ca20a Sim: Remove inference from Reference and Value 2022-11-18 08:39:15 +01:00
Mikolaj Wielgus 5eca8dd8de Undo hardcoding swapping of diode pins
Revert commits d1e2acd3 70b4d1aa cff508fb
2022-10-30 11:01:59 +01:00
Mikolaj Wielgus cff508fb3b Sim: Reverse diode model pin order to match diode symbols 2022-10-28 14:01:09 +02:00
Mikolaj Wielgus f31feaac42 Sim: Commit forgotten files 2022-10-27 08:08:14 +02:00
Mikolaj Wielgus 00c04e74ed Sim QA: Test LTspice parameters and ako models of BJTs 2022-10-20 04:00:33 +02:00
Mikolaj Wielgus c4fc9c1b16 Sim QA: Add tests for AKO and LTspice diodes 2022-10-19 06:56:21 +02:00
Mikolaj Wielgus 42acabb5a9 Fix a mistake in uopamp.lib.spice 2022-10-18 22:38:49 +02:00
Mikolaj Wielgus ae671c07e1 Commit missing uopamp.lib.spice 2022-10-18 17:38:23 +02:00
Mikolaj Wielgus e5704d7058 Update uopamp.lib.spice to be the same in all QA tests 2022-10-18 06:15:54 +02:00
Mikolaj Wielgus c8e13813d9 Sim: Rename Sim_Disabled field to Sim_Enable 2022-10-16 00:49:44 +02:00
Mikolaj Wielgus c3d5b3b3e5 Sim: Only store device type in reference, not full model type
Instead of Reference="VSIN1", Value="dc=1 ampl=2 f=3", it's now
Reference="V1", Value="SIN dc=1 ampl=2 f=3".
2022-10-15 19:36:26 +02:00
Seth Hillbrand 60374daa49 Fix ERC global label unit tests
Need to test all units in the subgraph as there are chances that the
subgraph might have more than one label, which needs to be consistently
handled
2022-09-12 13:16:45 -07:00
Mikolaj Wielgus 0e0d1a34f5 Sim: Spice grammar fixes
- Fix parsing .model lines with model names containingnon-alphanumeric
  characters like - and _,
- Fix parsing libraries in which EOF is not preceded by a newline.

Fixes https://gitlab.com/kicad/code/kicad/issues/12394
2022-09-12 04:05:17 +02:00
Mikolaj Wielgus e56635a02b Sim: Add mutual inductor model 2022-09-11 19:23:01 +02:00
Seth Hillbrand f2e3329617 Add ERC QA tests 2022-09-09 17:21:57 -07:00
Mikolaj Wielgus b225e53135 Sim QA: Test raw model with fewer pins than its symbol 2022-09-02 16:42:15 +02:00
Mikolaj Wielgus 121fad63ab Sim QA: Add Directives test
This test checks whether Spice directives placed in schematics as text
objects are properly included in the generated Spice netlist.
2022-08-31 09:41:35 +02:00
Mikolaj Wielgus bd6c153ad9 Sim: Implement "enum" model parameters for switches
Displayed in Sim Model Dialog parameter grid as a dropdown
(wxEnumProperty).
2022-08-30 09:45:49 +02:00
Mikolaj Wielgus 385e5deaaa Add Switches sim QA test
Tests voltage switches. Current switches will be tested as well once
they're fixed to work with .probe alli command in Ngspice.
2022-08-29 04:30:21 +02:00
Mikolaj Wielgus 103b8a0d2c Update the Opamp test to use a symbol with unordered pins 2022-08-26 04:36:48 +02:00
Mikolaj Wielgus c6defadb78 Add Fliege filter Spice netlist exporter test
Which we use to test multi-part symbols, as Fliege filter has two op
amps.
2022-08-25 08:47:31 +02:00