kicad/qa/unittests/pcbnew/drc
Seth Hillbrand 2451cbddec Consolidate Maximum clearance calculation
We were calculating the same thing in three locations and we missed
adding the clearance from the footprints in, resulting in bad fills and
missed drc errors (see QA addition)

(cherry picked from commit 96a34e5b57)
2023-07-26 13:16:32 -07:00
..
drc_test_utils.cpp
drc_test_utils.h
test_custom_rule_severities.cpp Don't use FindNamedPad for net-tie logic. It only reutrns the *first* 2022-09-25 17:38:31 +01:00
test_drc_copper_conn.cpp Smarten connection width checker looking for splits 2023-03-06 16:14:56 -08:00
test_drc_copper_graphics.cpp Add DRC testing for copper graphic to zone fill collisions. 2023-06-30 11:56:40 +01:00
test_drc_copper_sliver.cpp Rework Copper Sliver check 2023-05-03 10:22:49 -07:00
test_drc_courtyard_invalid.cpp Remove Millimeter2iu 2022-09-16 21:09:27 -04:00
test_drc_courtyard_overlap.cpp Remove Millimeter2iu 2022-09-16 21:09:27 -04:00
test_drc_regressions.cpp Consolidate Maximum clearance calculation 2023-07-26 13:16:32 -07:00
test_solder_mask_bridging.cpp Add DRC testing for copper graphic to zone fill collisions. 2023-06-30 11:56:40 +01:00