54 lines
1.4 KiB
YAML
54 lines
1.4 KiB
YAML
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# Tiny Tapeout project information
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project:
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title: "" # Project title
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author: "" # Your name
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discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
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description: "" # One line description of what your project does
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language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
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clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)
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# How many tiles your design occupies? A single tile is about 167x108 uM.
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tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
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# Your top module name must start with "tt_um_". Make it unique by including your github username:
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top_module: "tt_um_example"
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# List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
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source_files:
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- "project.v"
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# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
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pinout:
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# Inputs
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ui[0]: ""
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ui[1]: ""
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ui[2]: ""
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ui[3]: ""
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ui[4]: ""
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ui[5]: ""
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ui[6]: ""
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ui[7]: ""
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# Outputs
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uo[0]: ""
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uo[1]: ""
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uo[2]: ""
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uo[3]: ""
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uo[4]: ""
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uo[5]: ""
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uo[6]: ""
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uo[7]: ""
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# Bidirectional pins
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uio[0]: ""
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uio[1]: ""
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uio[2]: ""
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uio[3]: ""
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uio[4]: ""
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uio[5]: ""
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uio[6]: ""
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uio[7]: ""
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# Do not change!
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yaml_version: 6
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