01244fc84d
LPC43XX: Force target to use internal clock.
...
Without this, flash write timing might be incorrect.
2014-01-10 13:24:25 -08:00
2b798fa8fc
LPC43XX: Make the chunk_offset logic more explicit.
2014-01-10 13:24:25 -08:00
487252150f
LPC: Cleanup regs_size (in bytes).
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Also use sizeof() to make it clear why we multiple and divide by 4.
2014-01-10 13:24:25 -08:00
df9c19f071
LPC43XX: Remove type cast for erase function
2014-01-10 13:24:25 -08:00
911af3b836
LPC43XX: Add reset command to do a system reset (but not the debug).
2014-01-10 13:24:25 -08:00
813622b1b6
LPC43XX: Add mkboot target command; dont make banks bootable by default.
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This used to be done transparently in the write step, however that
breaks the 'verify' command. This is also more flexible for cases
where you want to write a flash bank without ever intending it to
be bootable.
2014-01-10 13:24:25 -08:00
29c7846612
LPC43XX: Make sure to align target struct to word alignment
2014-01-10 13:24:25 -08:00
8835df1822
Merge remote-tracking branch 'origin/usbuart_highrate'
2013-12-04 16:16:08 +13:00
42570efaf8
Revert "STM32F4: Add handling of second bank and dual boot devices."
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This reverts commit 536482f804
2013-10-22 07:48:06 +08:00
09fbe783c5
f4discovery: Limit clock to 48 MHz and stack 24 kiByte so that code can be compiled unchanged for F401Discovery too.
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TODO: Bump clk up to 84 MHz as soon as libopencm3 supports that speed.
2013-10-22 07:26:35 +08:00
536482f804
STM32F4: Add handling of second bank and dual boot devices.
2013-10-22 07:21:35 +08:00
cbd73cfb8f
STM32F4: Recognize F401.
2013-10-22 07:21:35 +08:00
5aa802969b
stlink: Give the NRST check more time as otherwise some L1 discovery board stayed in the bootloader.
2013-10-22 07:18:09 +08:00
086f3565f0
stm32f1: Fix handling of option byte write. Write needs to happend on erased option bytes.
2013-10-20 16:14:25 +02:00
15e529a43a
stm32f1.c: On a read protected device, deny any other option action than erase.
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Otherwise the first option action triggers an error, inhibiting further option
actions.
2013-10-20 16:14:19 +02:00
c395c6f73a
Configure SRST output as open-drain for BMP Mini hardware
2013-10-05 13:14:03 +08:00
3cce6f472c
Add support for the SYS_WRITEC semihosting operation.
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This is implemented in the same manner as QEMU semihosting
support, specifically, a SYS_WRITEC results in a single
character write to STDERR.
2013-10-05 13:14:03 +08:00
b8f9a2ed4b
Bugfix: Always apply the vector table magic number correctly.
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Previously when the flash write length was less than the Chunk size the 2nd chunk write would re-calculate and apply an incorrect magic number
2013-10-05 13:14:03 +08:00
40820a2354
Added internal pull-up to PWR_BR.
...
o Prevent probe from inadvertently powering target. If PWR_BR is
allowed to float, the gate on Q1 (blackmagic_mini) will tend to be
close enough to zero to turn the transistor on. We activate the
internal pull-up on this IO pin to force the transistor off.
2013-10-05 13:14:03 +08:00
e5d253bf81
Merge pull request #24 from richardeoin/master
...
New contrib board
2013-10-04 21:33:39 -07:00
e67192348f
FIX: usbd_init compatibility fix
...
Updated compatibility with libopencm3 commit 113e5c22e6390ba072148315e83a5faa5ff7ce86
2013-10-05 12:23:23 +08:00
c857165c12
FIX: FLASH_* collision with libopencm3 definitions
...
Resolve collision to FLASH_* from the libopencm3 by adding STM32F1_ prefix to the L1's
2013-10-05 12:23:23 +08:00
c28350f242
FIX: u{8,16,32} -> uint{8,16,32}_t to be compatible with new library
...
The use of u8, u16, u32 has been deprecated in libopencm3.
Update it with standard uint8_t, uint16_t, uint32_t types
2013-10-05 12:23:23 +08:00
f1584b266b
[BUILD] Don't throw error on already cleaned output
2013-10-05 12:23:23 +08:00
78464c8562
[LIB] Updated to newest libopencm3
2013-10-05 12:23:23 +08:00
e5e67e5740
Made assembly notes titles
2013-09-04 22:07:08 +01:00
c04ccf3ccc
Tided up README, added note about board being proven
2013-09-04 22:05:14 +01:00
ead74c272a
Added assembly descriptions
2013-09-04 21:11:32 +01:00
ac2bc70edc
Fixed Assembly photo
2013-09-04 21:03:37 +01:00
523dbb5df9
Added photos
2013-09-04 21:01:42 +01:00
28dca4702a
Added more description about the BOOT0 pin
2013-09-04 20:46:48 +01:00
1ca1c6c470
Added assembly photos
2013-09-04 20:28:22 +01:00
3ebec5609f
Made all the board layers visible
2013-09-04 20:28:06 +01:00
bcea91a825
Renamed schematic PDF
2013-09-04 20:22:20 +01:00
af3f20a218
Fixed line endings in README
2013-08-19 15:41:31 +01:00
be5e9b1ff8
Spelling error!
2013-08-19 15:38:23 +01:00
682138e321
Added pdf of schematic
2013-08-19 15:37:36 +01:00
4567011603
Fixed relative link in README
2013-08-19 15:36:13 +01:00
7a6879c93d
Removed mouse cursor from board image!
2013-08-19 15:34:18 +01:00
3735f263f3
Fixed image in README
2013-08-19 15:32:52 +01:00
3828bae844
Added image to README
2013-08-19 15:31:44 +01:00
73139a77b7
Fixed up README
2013-08-19 15:21:36 +01:00
7e7ebfc2be
Wrote README text
2013-08-19 15:20:23 +01:00
2f59e9f3a3
Added switch on BOOT0
2013-08-19 15:04:56 +01:00
2480162c07
Changed text on the end of the board to "ARM Cortex Debug"
2013-08-19 14:26:39 +01:00
80c215627d
Added links to parts list
2013-08-19 13:45:31 +01:00
1042246ee6
Fixed final list of parts list
2013-08-19 13:30:36 +01:00
e8a423972f
Completed parts list
2013-08-19 13:24:03 +01:00
168a15e3ae
Completed board layout
2013-08-19 12:49:54 +01:00
b3dedacbf5
Schematic provisionally complete
2013-08-19 10:41:14 +01:00
Allen Ibara
Gareth McMullin
Gareth McMullin
Uwe Bonnes
Michael Tharp
Benno Leslie
Richard Eoin Meadows
Marc Singer
BuFran