Commit Graph

489 Commits

Author SHA1 Message Date
Maciej Musiał 2673e34ddd cortexm: fixed an issue with watchpoint handling and a register sanity check 2022-06-26 13:44:45 -04:00
Uwe Bonnes 80c98df2f9 stm32wxxx: CPU2 needs wake-up call and has unexpected PIDR4 in AP1
"Single" core  STM32WLE still sees AP1 but on first scan aborts gracefully
after some errors and on later runs sees AP1 as unusable. Fixes #832.

Decode the Cross trigger interface found on CPU2 on STM32WBxx.
2022-06-25 16:52:36 -04:00
Uwe Bonnes 471ba19a77 adiv5.c: Read all CIDR data in one call.
E.g on STM32WXXX AP1 with C2BOOT not set, the AP base registers have valid
values but reading them fails and turns the AP unusable. BMDA reading CIDR
with multiple calls will will loop and finally hang up BMD. Other target
devices may show similar behaviour.
Reading CIDR with a single call allows recovery from in that case and
additional spares target transactions.
2022-06-25 16:52:36 -04:00
James Turton e702afad69 rp: Clean up code a little bit 2022-06-24 20:44:00 -04:00
James Turton e67cb9f43c rp: Update rp_get_flash_length algorithm
Try to look for repeating sectors before reverting to reading the
JEDEC ID of the flash chip. This way we don't interrupt the flash
execution if a valid program is running, but can detect the flash
size if the flash memory has been erased.
2022-06-24 20:44:00 -04:00
James Turton f2cb13cf36 rp: Add rp_attach and rp_detach callbacks
Query JEDEC ID of flash chip on attach to be able to decode flash
chip size.
2022-06-24 20:44:00 -04:00
James Turton 354e37fbad rp: Tidy up some other things 2022-06-24 20:44:00 -04:00
James Turton ce273889fc rp: Refector rp_flash_write
Fix typo in debug message
2022-06-24 20:44:00 -04:00
James Turton f4261c465e rp: Refactor rp_flash_erase
Always align erase length to 4k sector size.
Check that start address and length are actually inside the flash.
2022-06-24 20:44:00 -04:00
Rafael Silva dd571467b5 target/sam: slight gpnvm command usage correctness
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-06-24 20:19:47 -04:00
James Turton af48a343a8 rp: Add description for SPI flash commands 2022-06-11 11:54:34 -04:00
James Turton b43b9a6545 rp: Add erase_sector to command list
The command can be used either by specifying the length only, or
the start address and the length like so:
monitor erase_sector <length>
monitor erase_sector <start_addr> <length>
If no start address is specified, it will begin erasing from the
start of the flash sector.
2022-06-11 11:54:34 -04:00
James Turton 53672f1fc3 rp: Remove CHIP_ERASE command from rp_flash_erase
There seems to be a bug in the bootrom for the rp2040 which means
that the chip erase command is not accepted. This is because the
CS pin must be released (set high) directly after sending the chip
erase command (0x60 or 0xC7) (see Winbond W25Q128JV datasheet for
details). Instead the bootrom sends the address after the command,
thus the SPI flash silently ignores the command. Instead, we must
erase each 64KB block one at a time, but thankfull the bootrom
handles this correctly for us.
2022-06-11 11:54:34 -04:00
James Turton b1694dfab9 rp: Always use maximum flash size (16MB) when defining flash region
There are some cases when the this old method for finding the flash
size will fail, such as if the flash chip has been erased with 0xFF
bytes (rather than blank 0x00 bytes). As this is unreliable,
setting the wrong flash size could cause problems when trying to
inspect memory regions which appear to be out of range.
2022-06-11 11:54:34 -04:00
James Turton 203c5149e7 rp: Add CORTEXM_TOPT_INHIBIT_SRST to target_options 2022-06-11 11:54:34 -04:00
James Turton 4ec68023af cortex-a: Fix compiling for native probe 2022-06-09 04:13:12 -04:00
Dag Ågren f6edb54395 Fix RP2040 memory sizes. 2022-06-01 11:41:58 -04:00
dragonmux 2914be1a67
cortexa: Fix the new Watchpoint support causing a no-build 2022-05-31 22:03:21 -04:00
Gareth McMullin 0b7dd00c77 cortexa: Indicate watchpoint as stop reason if there is only one. 2022-05-31 21:58:51 -04:00
Gareth McMullin b5ef9e5bcf Implement watchpoints on Cortex-A 2022-05-31 21:58:51 -04:00
Rafael Silva 1aadcf2678 target/samx7x: handle tcm reconfiguration
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
Rafael Silva dcc450a494 target/sam3x: rework gpnvm command
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
Rafael Silva cf6ce32371 target: split mem_map_free into ram_map_free and flash_map_free
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
2022-05-31 21:48:54 -04:00
Rafael Silva 8462f5e0d4 target/samx7x: handle tcm config on probe
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
2022-05-31 21:48:54 -04:00
Rafael Silva 508b8d90cc target/sam3x: name changes to reflect multiple supported families
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
Rafael Silva 430d306511 target: add samx7x probe method
adds support for SAME70, SAMS70, SAMV71 and SAMV70

Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
dragonmux 2d4d6aa65a ch32f1: Fixed the assumption that uint32_t is an `unsigned int` 2022-05-31 21:37:02 -04:00
dragonmux 94a0f1587d ch32f1: Cleaned up some of the formatting 2022-05-31 21:37:02 -04:00
Michal Moskal 6b465d6a77 Temporarily enable DBG clock in stm32g0_detach(); fixes #1003 2022-04-12 05:39:14 -04:00
mean e535f53981 remove static vars 2022-04-10 23:40:44 -04:00
mean 844ca65a8f cosmetic 2022-04-10 23:40:44 -04:00
mean 17dca6f791 tabify 2022-04-10 23:40:44 -04:00
mean 733cf12663 cleanup 2022-04-10 23:40:44 -04:00
mean 17d7dca9ae build ch32 in its own file 2022-04-10 23:40:44 -04:00
mean 7c120ecb58 put ch32f1 in its own file 2022-04-10 23:40:44 -04:00
mean 04eb33e039 rename to comply to naming scheme 2022-04-10 23:40:44 -04:00
mean e12939582c revert function clones_probe 2022-04-10 23:40:44 -04:00
mean 83e3d9c135 disable verification 2022-04-10 23:40:44 -04:00
mean a3feae60aa cleanup tabs 2022-04-10 23:40:44 -04:00
mean fb216a2a98 tabify 2022-04-10 23:40:44 -04:00
mean 9b23265dde add support for ch32 flash write, it is a bit hackish 2022-04-10 23:40:44 -04:00
mean 90d15e6633 add probe for ch32 + make room for other clones 2022-04-10 23:40:44 -04:00
dragonmux 804a1a4f43
stm32f4: Attach logic cleanup by making sure we only set the extra bits needed when writing DBGMCU_CR 2022-03-31 13:46:29 -04:00
Uwe Bonnes eed1cc81ff STM32F4: Move DBGMCU_handling to target specific code. Apply for F4 too. 2022-03-31 13:43:52 -04:00
dragonmux a0c77e216d adiv5_swdp: Changed the low-level access code to retry till timeout (partial revert of 61efe26)
Proper initialisation of the ack value also fixes a potential use-before-init UB
2022-03-29 15:33:23 -07:00
dragonmux d9ef3ff147 adiv5_swdp: Formatting consistency cleanup 2022-03-29 15:33:23 -07:00
dragonmux bba2bfdcf4 advi5: Raise the access timeouts as 20ms is too low in some cases 2022-03-29 15:33:23 -07:00
mean 8fb3b7b1a8 reuse exception to avoid using the stack 2022-03-22 10:10:33 -04:00
dragonmux 4fe8fd8944 samd: Fixed the hosted build as the code from #987 assumed unsigned long was 32-bit 2022-03-14 21:38:45 -07:00
dragonmux e271c16f6c Removal of MFR descriptions as requested in #978 2022-03-14 21:37:44 -07:00