2022-06-01 15:00:12 +00:00
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# mmiogrok
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Collection of Python libraries to parse, generate and convert between several
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MMIO register definition files.
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#### Parse and generate
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* ARM CMSIS-**SVD** (ARM etc.)
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* **Device tree** (source/binary, peripheral only, no registers) [*planned*]
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#### Parse only
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* NEC/Renesas **DVF** (78K, RL78, V830/RH830, RX)
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* Lauterbach TRACE32 **PER** (misc) [*work in progress*]
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* Atmel/Microchip **ATDF**/ATpack (AVR etc.) [*planned*]
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* Texas Instruments **DSLite** (MSP430 etc.) [*planned*]
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#### Convert
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* DVF → SVD
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* PER → SVD [*work in progress*]
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* ATDF → SVD [*planned*]
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* DSLite → SVD [*planned*]
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* SVD → DTS/DTB (peripherals only) [*planned*]
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* DTS/DTB → SVD (peripherals only) [*planned*]
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2022-06-01 15:15:58 +00:00
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## Usage
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#### Libraries
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* `dvf/dvfparse.py` is able to parse DVF files
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* `svd/svd.py`, `svd/svdparse.py`, `svd/svdgen.py` handle SVD files
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#### Utilities
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* `dvf/dvf2h.py` is a quick DVF-to-headerfile converter
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* `dvf2svd.py` converts DVF to SVD files using the above libraries
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## Dependencies
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Python stdlib only, though I've been using 3.10, it might be the case that some
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things aren't in eg. 3.6.
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## FAQ etc
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#### Why is it Python? Why is the Python code so hacky?
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I quickly wanted to get something to work so that I could import MMIO stuff in
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Ghidra. Yes the code could be cleaner/faster (especially with a resp. Racket or
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Rust rewrite), but I just wanted to Get Things Done.
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#### Why is it not a proper Python module?
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I started from a script and things evolved from there. I should probably
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restructure the codebase a bit, the current method of importing stuff (by
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adding things to the Python module path...) is, not a good idea.
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#### Why are the converters inaccurate?
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For DVF, the main problem lies in the file format: all registers are laid out
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without peripheral associations, so no peripheral information (and peripheral ↔
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interrupt) mapping is available. Furthermore, the file format is binary, so
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figuring out which exact bits correspond to which register properties (eg.
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'write-to-clear') is pretty hard. The basics are still there, though. The code
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is currently untested for V830 and RX DVF files, which might differ in some
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ways.
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For TRACE32 PER, a large problem is that these files mix UI elements,
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conditionals and loops, and actual peripheral and register definitions, in a
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quite shitty to parse text-based format, making things quite complicated. The
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conditionals depend on outside knowledge (eg. exact chip names, Xtensa TRAX
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register bases, ...) which I don't have, so those are currently left ignored.
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2022-06-01 15:21:51 +00:00
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#### Where do I get these files?
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CMSIS-SVD files can be obtained from eg.
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[here](https://github.com/posborne/cmsis-svd).
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Many device tree source files can be found in the [Linux kernel source
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tree](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/).
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NEC/Renesas DVF files can be downloaded from the Renesas website (per chip as
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"Device File" or "Parameter File"), or in bulk from Renesas toolchain updates
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or from messing around with the search tool on the Renesas webiste.
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TRACE32 PER files can be obtained from the Lauterbach website by going through
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the "Other Updates" section of the TRACE32 downloadables.
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ATpack files (which are zip files containing ATDFs) can be downloaded from
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[here](http://packs.download.atmel.com/).
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TI DSLite files come with a CCStudio installation.
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2022-06-01 15:15:58 +00:00
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## License
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Eh, idk yet.
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