v3hil: handle new protocol versions
This commit is contained in:
parent
c375f74c51
commit
43f9d7bc54
233
drivers/v3hil.c
233
drivers/v3hil.c
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@ -170,12 +170,30 @@ typedef enum {
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HAL_PROTO_CONFIG_JTAG_LOCK_5XX = 0x17,
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} hal_proto_config_t;
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static hal_proto_fid_t map_ver(const struct v3hil *h, hal_proto_fid_t src)
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{
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hal_proto_fid_t dst;
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if (h->proto_ver < 0x0300 && src > HAL_PROTO_FID_GET_DEVICE_ID_PTR) {
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dst = src - 1;
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} else {
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dst = src;
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}
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dbg_printc("map ver: %02x -> %02x\n", src, dst);
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return dst;
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}
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static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src)
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{
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hal_proto_fid_t dst = h->chip->v3_functions[src];
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if (dst == 0) {
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dst = src;
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}
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dbg_printc("map fid: %02x -> %02x\n", src, dst);
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return dst;
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return map_ver(h, dst);
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}
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void v3hil_init(struct v3hil *h, transport_t trans,
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@ -191,7 +209,7 @@ int v3hil_set_vcc(struct v3hil *h, int vcc_mv)
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w16le(data, vcc_mv);
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dbg_printc("Setting VCC...\n");
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return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_VCC, data, 2);
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return hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_SET_VCC), data, 2);
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}
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int v3hil_comm_init(struct v3hil *h)
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@ -206,6 +224,43 @@ int v3hil_comm_init(struct v3hil *h)
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return -1;
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if (h->hal.length < 8) {
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printc_err("warning: v3hil: short reply to version request\n");
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} else if (h->hal.length == 40) {
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#ifdef DEBUG_V3HIL
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printc_dbg("v3hil: Version:");
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for (int i = 0; i < h->hal.length; i++)
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printc_dbg(" %02x", h->hal.payload[i]);
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printc_dbg("\n");
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#endif
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const uint16_t sw_version = r32le(h->hal.payload + 0);
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const uint16_t sw_build = r32le(h->hal.payload + 2);
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const uint32_t hw_thing = r32le(h->hal.payload + 4);
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const uint32_t tool_id = r16le(h->hal.payload + 8);
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const uint16_t core_version = r16le(h->hal.payload + 10);
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const uint16_t hil_version = r16le(h->hal.payload + 12);
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const uint16_t dcdc_layer_version = r16le(h->hal.payload + 14);
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const uint16_t dcdc_mcu_version = r16le(h->hal.payload + 16);
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const uint16_t com_version = r16le(h->hal.payload + 18);
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const uint16_t hil_crc = r16le(h->hal.payload + 20);
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const uint16_t hal_crc = r16le(h->hal.payload + 22);
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const uint16_t dcdc_crc = r16le(h->hal.payload + 24);
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const uint16_t core_crc = r16le(h->hal.payload + 26);
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const uint16_t com_crc = r16le(h->hal.payload + 28);
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const uint16_t fpga_version = r16le(h->hal.payload + 30);
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const uint16_t n_rx_queues = r16le(h->hal.payload + 32);
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const uint16_t rx_queue_size = r16le(h->hal.payload + 34);
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const uint8_t major = (sw_version >> 14) + 1;
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const uint8_t minor = (sw_version >> 8) & 0x3f;
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const uint8_t patch = sw_version & 0xff;
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const uint8_t build = sw_build;
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printc_dbg("Version: %d.%d.%d.%d Core version: 0x%02x, HIL version: 0x%02x, HW: 0x%04x\n",
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major, minor, patch, build,
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core_version, hil_version, hw_thing);
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h->proto_ver = (major << 8) | minor;
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} else {
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const uint8_t major = h->hal.payload[1] >> 6;
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const uint8_t minor = h->hal.payload[1] & 0x3f;
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@ -215,11 +270,13 @@ int v3hil_comm_init(struct v3hil *h)
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printc_dbg("Version: %d.%d.%d.%d, HW: 0x%04x\n",
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major, minor, patch, flavour,
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r32le(h->hal.payload + 4));
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h->proto_ver = (major << 8) | minor;
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}
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printc_dbg("Reset firmware...\n");
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if (hal_proto_execute(&h->hal,
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HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS, NULL, 0) < 0)
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map_ver(h, HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS), NULL, 0) < 0)
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return -1;
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return 0;
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@ -231,7 +288,7 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
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uint8_t chain_id[2] = {0, 0};
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dbg_printc("Start JTAG...\n");
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if (hal_proto_execute(&h->hal, HAL_PROTO_FID_START_JTAG,
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if (hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_START_JTAG),
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&data, 1) < 0)
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return -1;
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@ -246,19 +303,30 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
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}
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printc_dbg("Device count: %d\n", h->hal.payload[0]);
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return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO,
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chain_id, 2);
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return hal_proto_execute(&h->hal,
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map_ver(h, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO), chain_id, 2);
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}
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int v3hil_stop_jtag(struct v3hil *h)
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{
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dbg_printc("Stop JTAG...\n");
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return hal_proto_execute(&h->hal, HAL_PROTO_FID_STOP_JTAG, NULL, 0);
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if (hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_STOP_JTAG), NULL, 0) < 0)
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return -1;
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dbg_printc("Reset communications...\n");
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h->hal.ref_id = 0;
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if (hal_proto_send(&h->hal, HAL_PROTO_TYPE_EXCEPTION, NULL, 0) < 0) {
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h->hal.ref_id = 0;
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return -1;
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}
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h->hal.ref_id = 0;
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return 0;
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}
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int v3hil_sync(struct v3hil *h)
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{
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uint8_t data[32];
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uint8_t data[32], datalen = 21;
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h->cal.is_cal = 0;
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@ -273,8 +341,21 @@ int v3hil_sync(struct v3hil *h)
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if (h->chip) {
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int i;
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for (i = 0; i < 16; i++)
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data[i + 20 - i] = h->chip->clock_map[i].value;
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for (i = 0; i < 16; i++) {
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dbg_printc("clock map %d = %02x -> %d\n",
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i, h->chip->clock_map[i].value, 20-i);
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data[16 + 4 - i] = h->chip->clock_map[i].value;
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}
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if (h->proto_ver >= 0x0308) {
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datalen = 21+16;
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for (i = 16; i < 32; i++) {
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dbg_printc("clock map2 %d = %02x -> %d\n",
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i, h->chip->clock_map[i].value, 16+4+16*2 - i);
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data[16+4+16*2 - i] = h->chip->clock_map[i].value;
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}
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}
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} else {
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data[5] = 1;
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data[15] = 40;
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@ -283,13 +364,36 @@ int v3hil_sync(struct v3hil *h)
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/* We can't use map_fid() because h->chip might be NULL -- this
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* function will be called before identification is complete.
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*/
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dbg_printc("Sync: assert POR\n");
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if (hal_proto_execute(&h->hal,
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(h->jtag_id == 0x89)
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hal_proto_fid_t cmdid = (h->jtag_id == 0x89/*0x90*/)
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? HAL_PROTO_FID_SJ_ASSERT_POR_SC
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: HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2,
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data, 21) < 0)
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: HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2;
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dbg_printc("Sync: assert POR\n");
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if (h->chip) {
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if (hal_proto_execute(&h->hal, map_fid(h, cmdid), data, datalen) < 0) {
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return -1;
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}
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} else {
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/* Need to do something for X/Xv2 devices, so try each in turn... */
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cmdid = map_ver(h, cmdid);
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if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
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cmdid = map_ver(h, HAL_PROTO_FID_SJ_ASSERT_POR_SC_X);
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if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
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cmdid = map_ver(h, HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2);
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if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
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return -1;
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}
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}
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}
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}
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#ifdef DEBUG_V3HIL
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printc_dbg("v3hil: POR result: (len %d) ", h->hal.length);
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for (int i = 0; i < h->hal.length; ++i) {
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printc_dbg("%02x%s", h->hal.payload[i],
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(i == h->hal.length - 1) ? "\n" : " ");
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}
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#endif
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if (h->hal.length < 8) {
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printc_err("v3hil: short reply: %d\n", h->hal.length);
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@ -599,17 +703,24 @@ static int write_ram(struct v3hil *h, const struct chipinfo_memory *m,
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address_t addr, const uint8_t *mem, address_t size)
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{
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uint8_t data[256];
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bool fram = false;
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if (h->chip->features & CHIPINFO_FEATURE_FRAM) {
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if (!strcmp(m->name, "Main") || !strcmp(m->name, "Info")) {
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dbg_printc("write ram: to FRAM!\n");
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fram = true;
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}
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}
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w32le(data, addr);
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w32le(data + 4, (m->bits == 8) ? size : (size >> 1));
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w32le(data + 4, (m->bits == 8 || fram) ? size : (size >> 1));
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memcpy(data + 8, mem, size);
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dbg_printc("write ram\n");
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if (hal_proto_execute(&h->hal,
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map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES
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: HAL_PROTO_FID_WRITE_MEM_WORDS),
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data, size + 8) < 0) {
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hal_proto_fid_t fid = (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES
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: HAL_PROTO_FID_WRITE_MEM_WORDS;
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if (fram) fid = HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2;
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if (hal_proto_execute(&h->hal, map_fid(h, fid), data, size + 8) < 0) {
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printc_err("v3hil: failed writing %d bytes to 0x%05x\n",
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size, addr);
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return -1;
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@ -632,11 +743,12 @@ int v3hil_write(struct v3hil *h, address_t addr,
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if (size > 128)
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size = 128;
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if (m->type == CHIPINFO_MEMTYPE_FLASH) {
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dbg_printc("write: call write flash\n");
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if (m->type == CHIPINFO_MEMTYPE_FLASH)
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return write_flash(h, addr, mem, size);
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}
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dbg_printc("call write ram\n");
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dbg_printc("write: call write ram\n");
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return write_ram(h, m, addr, mem, size);
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}
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@ -729,9 +841,11 @@ int v3hil_erase(struct v3hil *h, address_t segment)
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int v3hil_update_regs(struct v3hil *h)
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{
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const hal_proto_fid_t fid =
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map_fid(h, HAL_PROTO_FID_READ_ALL_CPU_REGS);
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const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS) ? 2 : 3;
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const hal_proto_fid_t fid = map_fid(h, HAL_PROTO_FID_READ_ALL_CPU_REGS);
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const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS
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|| fid == HAL_PROTO_FID_READ_ALL_CPU_REGS - 1)
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? 2 : 3;
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int i;
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int sptr = 0;
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@ -767,9 +881,10 @@ int v3hil_update_regs(struct v3hil *h)
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int v3hil_flush_regs(struct v3hil *h)
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{
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const hal_proto_fid_t fid =
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map_fid(h, HAL_PROTO_FID_WRITE_ALL_CPU_REGS);
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const int reg_size = (fid == HAL_PROTO_FID_WRITE_ALL_CPU_REGS) ? 2 : 3;
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const hal_proto_fid_t fid = map_fid(h, HAL_PROTO_FID_WRITE_ALL_CPU_REGS);
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const int reg_size = (fid == HAL_PROTO_FID_WRITE_ALL_CPU_REGS
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|| fid == HAL_PROTO_FID_WRITE_ALL_CPU_REGS - 1)
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? 2 : 3;
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int i;
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int dptr = 0;
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uint8_t data[64];
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@ -905,7 +1020,7 @@ static int set_param(struct v3hil *fet, hal_proto_config_t cfg,
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data[0] = cfg;
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dbg_printc("Set param 0x%02x to 0x%08x\n", cfg, value);
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if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_CONFIGURE,
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if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_CONFIGURE),
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data, 8) < 0) {
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printc_err("v3hil: can't set param 0x%02x to 0x%08x\n",
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cfg, value);
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@ -925,7 +1040,7 @@ static int idproc_89(struct v3hil *fet, uint32_t id_data_addr,
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memset(data, 0, 8);
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w32le(data, id_data_addr);
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data[4] = 8;
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if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_WORDS,
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if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_WORDS),
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data, 8) < 0)
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return -1;
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if (fet->hal.length < 16) {
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@ -941,7 +1056,7 @@ static int idproc_89(struct v3hil *fet, uint32_t id_data_addr,
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id->config = fet->hal.payload[13] & 0x7f;
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printc_dbg("Read fuses...\n");
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if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_FUSES, NULL, 0) < 0)
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if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_FUSES), NULL, 0) < 0)
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return -1;
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if (!fet->hal.length) {
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printc_err("v3hil: short reply: %d\n", fet->hal.length);
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@ -965,7 +1080,7 @@ static int idproc_9x(struct v3hil *fet, uint32_t dev_id_ptr,
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memset(data, 0, 8);
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w32le(data, dev_id_ptr);
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data[4] = 4;
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if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2,
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if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_QUICK_XV2),
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data, 8) < 0)
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return -1;
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if (fet->hal.length < 8) {
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@ -989,7 +1104,7 @@ static int idproc_9x(struct v3hil *fet, uint32_t dev_id_ptr,
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w32le(data, dev_id_ptr);
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w32le(data + 4, tlv_size >> 1);
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w32le(data + 8, fet->regs[MSP430_REG_PC]);
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if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2,
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if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_QUICK_XV2),
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data, 8) < 0)
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return -1;
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if (fet->hal.length < tlv_size) {
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@ -1023,26 +1138,56 @@ int v3hil_identify(struct v3hil *fet)
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int i;
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printc_dbg("Fetching JTAG ID...\n");
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if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_JTAG_ID,
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if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_JTAG_ID),
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NULL, 0) < 0)
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return -1;
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if (fet->hal.length < 12) {
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printc_err("v3hil: short reply: %d\n", fet->hal.length);
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return -1;
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}
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printc_dbg("ID:");
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for (i = 0; i < fet->hal.length; i++)
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printc_dbg(" %02x", fet->hal.payload[i]);
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printc_dbg("\n");
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if (fet->hal.length < 12) {
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if (fet->hal.length == 2) {
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fet->jtag_id = fet->hal.payload[0];
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if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_DEVICE_ID_PTR),
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NULL, 0) < 0)
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return -1;
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#ifdef DEBUG_V3HIL
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dbg_printc("len: %d\n", fet->hal.length);
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printc_dbg("v3hil: IDPtr:");
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for (i = 0; i < fet->hal.length; i++)
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printc_dbg(" %02x", fet->hal.payload[i]);
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printc_dbg("\n");
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#endif
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if (fet->hal.length < 10) {
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printc_err("v3hil: short reply: %d\n", fet->hal.length);
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return -1;
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} else {
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dev_id_ptr = r32le(fet->hal.payload + 0);
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|
||||
if (dev_id_ptr == 0) {
|
||||
/* welp sometimes it's this instead (JTAG ID == 0x89?) */
|
||||
dev_id_ptr = r32le(fet->hal.payload + 4);
|
||||
}
|
||||
|
||||
id_data_addr = dev_id_ptr; /* idk */
|
||||
}
|
||||
} else {
|
||||
printc_err("v3hil: short reply: %d\n", fet->hal.length);
|
||||
return -1;
|
||||
}
|
||||
} else {
|
||||
/* Byte at 0 is JTAG ID. 0x91, 0x95, 0x99 means CPUxV2. 0x89
|
||||
* means old CPU.
|
||||
*/
|
||||
fet->jtag_id = fet->hal.payload[0];
|
||||
dev_id_ptr = r32le(fet->hal.payload + 4);
|
||||
id_data_addr = r32le(fet->hal.payload + 8);
|
||||
}
|
||||
|
||||
/* Pick fail-safe configuration */
|
||||
printc_dbg("Reset parameters...\n");
|
||||
|
|
@ -1053,12 +1198,12 @@ int v3hil_identify(struct v3hil *fet)
|
|||
set_param(fet, HAL_PROTO_CONFIG_PSA_TCKL_HIGH, 0) < 0 ||
|
||||
set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG_MASK, 0) < 0 ||
|
||||
set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG3V_MASK, 0) < 0 ||
|
||||
set_param(fet, HAL_PROTO_CONFIG_NO_BSL, 0) < 0 ||
|
||||
set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ, 0) < 0)
|
||||
return -1;
|
||||
set_param(fet, HAL_PROTO_CONFIG_NO_BSL, 0); /* is allowed to fail */
|
||||
|
||||
printc_dbg("Check JTAG fuse...\n");
|
||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN,
|
||||
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN),
|
||||
NULL, 0) < 0)
|
||||
return -1;
|
||||
if ((fet->hal.length >= 2) &&
|
||||
|
|
@ -1127,13 +1272,13 @@ int v3hil_configure(struct v3hil *fet)
|
|||
fet->chip->power.enable_lpm5_3v) < 0 ||
|
||||
set_param(fet, HAL_PROTO_CONFIG_TESTREG3V_DISABLE_LPMX5,
|
||||
fet->chip->power.disable_lpm5_3v) < 0 ||
|
||||
set_param(fet, HAL_PROTO_CONFIG_NO_BSL,
|
||||
(fet->chip->features &
|
||||
CHIPINFO_FEATURE_NO_BSL) ? 1 : 0) < 0 ||
|
||||
set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ,
|
||||
(fet->chip->features &
|
||||
CHIPINFO_FEATURE_1337) ? 1 : 0) < 0)
|
||||
return -1;
|
||||
/* is allowed to fail */
|
||||
set_param(fet, HAL_PROTO_CONFIG_NO_BSL,
|
||||
(fet->chip->features & CHIPINFO_FEATURE_NO_BSL) ? 1 : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,6 +44,9 @@ struct v3hil {
|
|||
/* Lower 8 bits of saved WDTCTL */
|
||||
uint8_t wdtctl;
|
||||
|
||||
/* Is this a v2 or v3 firmware running on the eZ-FET? */
|
||||
uint16_t proto_ver;
|
||||
|
||||
/* Register cache: this must be flushed before restoring context
|
||||
* and updated after saving context.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue