[simio] support Timer_B compare latch grouping
This commit is contained in:
Tadashi G. Takaoka
Tadashi G. Takaoka
parent
c53f697b76
commit
8564f42b66
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@ -92,6 +92,8 @@ struct timer {
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uint16_t ccrs[MAX_CCRS];
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/* Compare latch for Timer_B */
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uint16_t bcls[MAX_CCRS];
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/* True if ccrs[index] has a value set. Used for compare latch grouping */
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bool valid_ccrs[MAX_CCRS];
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};
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static struct simio_device *timer_create(char **arg_text)
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@ -151,6 +153,7 @@ static void timer_reset(struct simio_device *dev)
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memset(tr->ccrs, 0, sizeof(tr->ccrs));
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memset(tr->ctls, 0, sizeof(tr->ctls));
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memset(tr->bcls, 0, sizeof(tr->bcls));
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memset(tr->valid_ccrs, false, sizeof(tr->valid_ccrs));
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}
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static int config_addr(address_t *addr, char **arg_text)
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@ -362,6 +365,49 @@ static uint16_t tar_mask(struct timer *tr)
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return 0xffff;
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}
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static void set_bcl(struct timer *tr, int index)
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{
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tr->bcls[index] = tr->ccrs[index];
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tr->valid_ccrs[index] = false;
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}
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static bool no_double_buffer(struct timer *tr, int index)
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{
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uint16_t clgrp = tr->tactl & (TBCLGRP1 | TBCLGRP0);
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if (clgrp == TBCLGRP0 && (index == 2 || index == 4 || index == 6))
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return (tr->ctls[index - 1] & (CLLD1 | CLLD0)) == 0;
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if (clgrp == TBCLGRP1 && (index == 2 || index == 5))
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return (tr->ctls[index - 1] & (CLLD1 | CLLD0)) == 0;
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if (clgrp == TBCLGRP1 && (index == 3 || index == 6))
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return (tr->ctls[index - 2] & (CLLD1 | CLLD0)) == 0;
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if (clgrp == (TBCLGRP1 | TBCLGRP0))
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return (tr->ctls[1] & (CLLD1 | CLLD0)) == 0;
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return (tr->ctls[index] & (CLLD1 | CLLD0)) == 0;
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}
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static void set_ccr(struct timer *tr, int index, uint16_t data)
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{
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tr->ccrs[index] = data;
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tr->valid_ccrs[index] = true;
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if (tr->timer_type == TIMER_TYPE_A) {
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/* When CCR[0] set is less than TAR in up mode, TAR rolls to
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* 0. */
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if (index == 0 && data < tr->tar &&
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(tr->tactl & (MC1 | MC0)) == MC0) {
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tr->go_down = true;
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}
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}
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if (tr->timer_type == TIMER_TYPE_B) {
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/* Writing TBCCRx triggers update TBCLx immediately. No
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* grouping. */
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if (no_double_buffer(tr, index)) {
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set_bcl(tr, index);
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}
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}
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}
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static int timer_write(struct simio_device *dev,
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address_t addr, uint16_t data)
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{
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@ -401,20 +447,7 @@ static int timer_write(struct simio_device *dev,
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addr < tr->base_addr + (tr->size << 1) + 0x12) {
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int index = ((addr & 0xf) - 2) >> 1;
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tr->ccrs[index] = data;
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if (tr->timer_type == TIMER_TYPE_A &&
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index == 0 && data < tr->tar &&
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(tr->tactl & (MC1 | MC0)) == MC0) {
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/* When CCR[0] is set less than current TAR in up
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* mode, TAR rolls to 0. */
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tr->go_down = true;
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}
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if (tr->timer_type == TIMER_TYPE_B &&
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(tr->ctls[index] & (CLLD1 | CLLD0)) == 0) {
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/* Writing TBCCRx triggers update TBCLx immediately.
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* No grouping. */
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tr->bcls[index] = tr->ccrs[index];
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}
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set_ccr(tr, index, data);
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return 0;
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}
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@ -545,6 +578,48 @@ static void tar_step(struct timer *tr)
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}
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}
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static void update_bcls(struct timer *tr, int start, int n)
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{
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int index;
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const int end = start + n;
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for (index = start; index < end; index++) {
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if (!tr->valid_ccrs[index])
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return;
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}
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for (index = start; index < end; index++)
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set_bcl(tr, index);
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}
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static void update_bcl_group(struct timer *tr, int index)
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{
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switch (tr->tactl & (TBCLGRP1 | TBCLGRP0)) {
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case 0: /* Individual */
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set_bcl(tr, index);
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return;
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case TBCLGRP0: /* 0, 1&2, 3&4, 5&6 */
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if (index == 0) {
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update_bcls(tr, index, 1);
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} else if (index == 1 || index == 3 || index == 5) {
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update_bcls(tr, index, 2);
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}
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return;
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case TBCLGRP1: /* 0, 1&2&3, 4&5&6 */
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if (index == 0) {
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update_bcls(tr, index, 1);
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} else if (index == 1 || index == 4) {
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update_bcls(tr, index, 3);
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}
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return;
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case TBCLGRP1 | TBCLGRP0: /* All at once */
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if (index == 1) {
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update_bcls(tr, 0, tr->size);
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}
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return;
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}
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}
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static void comparator_step(struct timer *tr, int index)
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{
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if (tr->timer_type == TIMER_TYPE_A) {
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@ -562,14 +637,14 @@ static void comparator_step(struct timer *tr, int index)
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const uint16_t clld = tr->ctls[index] & (CLLD1 | CLLD0);
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if (tr->tar == 0) {
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if (clld == CLLD0 || (clld == CLLD1 && mc != 0)) {
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tr->bcls[index] = tr->ccrs[index];
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update_bcl_group(tr, index);
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}
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}
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if (tr->tar == get_ccr(tr, index)) {
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tr->ctls[index] |= CCIFG;
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if ((clld == CLLD1 && mc == (MC1 | MC0)) ||
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clld == (CLLD1 | CLLD0)) {
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tr->bcls[index] = tr->ccrs[index];
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update_bcl_group(tr, index);
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}
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}
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}
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@ -1223,6 +1223,263 @@ static void test_timer_b_compare_latch_3_up()
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assert(check_noirq(dev));
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}
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static void test_timer_b_grouping_1()
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{
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dev = create_timer("7");
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config_timer(dev, "type", "B");
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/* Continuous mode, SMCLK, pair grouping */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | TBCLGRP0);
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write_timer(dev, TxCCR(0), 2);
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write_timer(dev, TxCCR(1), 4);
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write_timer(dev, TxCCR(2), 5);
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write_timer(dev, TxCCR(3), 6);
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write_timer(dev, TxCCR(4), 7);
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write_timer(dev, TxCCR(5), 8);
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write_timer(dev, TxCCR(6), 9);
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/* Load TBCL when TBR reaches old TBCL value, compare interrupt */
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write_timer(dev, TxCCTL(0), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCR(0), 10);
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// Both CCR[1] and CCR[2] are set.
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write_timer(dev, TxCCTL(1), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCTL(2), CCIE);
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write_timer(dev, TxCCR(1), 12);
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write_timer(dev, TxCCR(2), 13);
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// CCR[3] is set but CCR[4] keep unset.
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write_timer(dev, TxCCTL(3), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCTL(4), CCIE);
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write_timer(dev, TxCCR(3), 14);
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// Both CCR[5] and CCR[6] are set, but CCTL[5] has CCLD=0.
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write_timer(dev, TxCCTL(5), CCIE);
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write_timer(dev, TxCCTL(6), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCR(5), 16);
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write_timer(dev, TxCCR(6), 17);
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step_smclk(dev, 2);
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// TBCL[0] becomes 10.
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assert(read_timer(dev, TxR) == 2);
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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// TBCL[1] and TBCL[2] becomes 12 and 13.
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assert(read_timer(dev, TxR) == 3);
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(1));
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assert(check_noirq(dev));
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// TBCL[3] and TBCL[4] keep previous value.
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// because TBCCR[4] has no valid value set.
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assert(read_timer(dev, TxR) == 5);
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(3));
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assert(check_noirq(dev));
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(4));
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assert(check_noirq(dev));
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// TBCL[5] and TBCL[6] is already 16 and 17 because TBCTL[5]
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// has CLLD=0 set, thus no interrupts at TBR=8,9.
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assert(read_timer(dev, TxR) == 8);
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step_smclk(dev, 1);
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assert(check_noirq(dev));
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step_smclk(dev, 1);
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assert(check_noirq(dev));
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// TBCL[0] will match.
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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assert(read_timer(dev, TxCCTL(0)) & CCIFG);
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert_not(read_timer(dev, TxCCTL(0)) & CCIFG);
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// TBCL[1]will match.
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_timer(dev, TxCCTL(1)) & CCIFG);
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assert(read_iv(dev) == TxIV_TxIFG(1));
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assert(check_noirq(dev));
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assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
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// Because TBCL[2] is also loaded as group with TBCL[1].
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_timer(dev, TxCCTL(2)) & CCIFG);
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assert(read_iv(dev) == TxIV_TxIFG(2));
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assert(check_noirq(dev));
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assert_not(read_timer(dev, TxCCTL(2)) & CCIFG);
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// TBCL[3] and TBCL[4] didn't updated since TBCCR[4] has
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// no value set, thus no compare interrupts at TBR=14,15.
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assert(read_timer(dev, TxR) == 14);
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step_smclk(dev, 1);
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assert(check_noirq(dev));
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step_smclk(dev, 1);
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assert(check_noirq(dev));
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// TBCL[5] and TBCL[6] have set to 16 and 17, thus two compare
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// interrupts at TBR=16,17
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_timer(dev, TxCCTL(5)) & CCIFG);
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assert(read_iv(dev) == TxIV_TxIFG(5));
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assert(check_noirq(dev));
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assert_not(read_timer(dev, TxCCTL(5)) & CCIFG);
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_timer(dev, TxCCTL(6)) & CCIFG);
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assert(read_iv(dev) == TxIV_TxIFG(6));
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assert(check_noirq(dev));
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assert_not(read_timer(dev, TxCCTL(6)) & CCIFG);
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}
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static void test_timer_b_grouping_2()
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{
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dev = create_timer("7");
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config_timer(dev, "type", "B");
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/* Continuous mode, SMCLK, triplet grouping */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | TBCLGRP1);
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write_timer(dev, TxCCR(0), 2);
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write_timer(dev, TxCCR(1), 4);
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write_timer(dev, TxCCR(2), 5);
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write_timer(dev, TxCCR(3), 6);
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write_timer(dev, TxCCR(4), 7);
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write_timer(dev, TxCCR(5), 8);
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write_timer(dev, TxCCR(6), 9);
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/* Load TBCL when TBR reaches old TBCL value, compare interrupt */
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write_timer(dev, TxCCTL(0), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCR(0), 10);
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// All CCR[1], CCR[2], and CCR[3] are set.
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write_timer(dev, TxCCTL(1), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCTL(2), CCIE);
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write_timer(dev, TxCCTL(3), CCIE);
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write_timer(dev, TxCCR(1), 12);
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write_timer(dev, TxCCR(2), 6);
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write_timer(dev, TxCCR(3), 5);
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// CCR[4] and CCR[6] are set but CCR[5] keep unset.
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write_timer(dev, TxCCTL(4), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCTL(5), CCIE);
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write_timer(dev, TxCCTL(6), CCIE);
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write_timer(dev, TxCCR(4), 14);
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write_timer(dev, TxCCR(6), 8);
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step_smclk(dev, 2);
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// TBCL[0] becomes 10.
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assert(read_timer(dev, TxR) == 2);
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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// TBCL[1], TBCL[2], and TBCL[3] becomes 12, 6, and 5.
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assert(read_timer(dev, TxR) == 3);
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(1));
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 5);
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(3));
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assert(check_noirq(dev));
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(2));
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assert(check_noirq(dev));
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// TBCL[4], TBCL[5] and TBC[6] keep previous value.
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// because TBCCR[5] has no valid value set.
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assert(read_timer(dev, TxR) == 7);
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(4));
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assert(check_noirq(dev));
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(5));
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assert(check_noirq(dev));
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(6));
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assert(check_noirq(dev));
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// TBCL[0] is updated to 10 and TBCL[1] has 12.
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assert(read_timer(dev, TxR) == 10);
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(1));
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assert(check_noirq(dev));
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}
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static void test_timer_b_grouping_3()
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{
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dev = create_timer("7");
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config_timer(dev, "type", "B");
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/* Continuous mode, SMCLK, triplet grouping */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | TBCLGRP1 | TBCLGRP0);
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write_timer(dev, TxCCR(0), 3);
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write_timer(dev, TxCCR(1), 2);
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write_timer(dev, TxCCR(2), 4);
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write_timer(dev, TxCCR(3), 5);
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write_timer(dev, TxCCR(4), 6);
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write_timer(dev, TxCCR(5), 7);
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write_timer(dev, TxCCR(6), 8);
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/* Load TBCL when TBR reaches old TBCL value, compare interrupt */
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCTL(1), CLLD1 | CLLD0 | CCIE);
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write_timer(dev, TxCCTL(6), CCIE);
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write_timer(dev, TxCCR(0), 9);
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write_timer(dev, TxCCR(1), 10);
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write_timer(dev, TxCCR(2), 11);
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write_timer(dev, TxCCR(3), 12);
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write_timer(dev, TxCCR(4), 13);
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write_timer(dev, TxCCR(5), 14);
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write_timer(dev, TxCCR(6), 15);
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step_smclk(dev, 2);
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// TBCL[1] becomes 10.
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assert(read_timer(dev, TxR) == 2);
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(1));
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assert(check_noirq(dev));
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// The least valued TBCL is TBCL[9].
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step_smclk(dev, 6);
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assert(read_timer(dev, TxR) == 9);
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assert(check_noirq(dev));
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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ack_irq0(dev);
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step_smclk(dev, 1);
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assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TxIV_TxIFG(1));
|
||||
step_smclk(dev, 4);
|
||||
assert(check_noirq(dev));
|
||||
assert(read_timer(dev, TxCCTL(2)) & CCIFG);
|
||||
assert(read_timer(dev, TxCCTL(3)) & CCIFG);
|
||||
assert(read_timer(dev, TxCCTL(4)) & CCIFG);
|
||||
assert(read_timer(dev, TxCCTL(5)) & CCIFG);
|
||||
step_smclk(dev, 1);
|
||||
assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TxIV_TxIFG(6));
|
||||
assert(check_noirq(dev));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test runner.
|
||||
|
|
@ -1277,4 +1534,7 @@ int main(int argc, char **argv)
|
|||
RUN_TEST(test_timer_b_compare_latch_2_up);
|
||||
RUN_TEST(test_timer_b_compare_latch_2_updown);
|
||||
RUN_TEST(test_timer_b_compare_latch_3_up);
|
||||
RUN_TEST(test_timer_b_grouping_1);
|
||||
RUN_TEST(test_timer_b_grouping_2);
|
||||
RUN_TEST(test_timer_b_grouping_3);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue