hal_proto, v3hil: add missing command and status IDs
This commit is contained in:
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9d1a2528de
commit
9484b1cff6
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@ -37,6 +37,11 @@ typedef enum {
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HAL_PROTO_TYPE_DCDC_POWER_DOWN = 0x60,
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HAL_PROTO_TYPE_DCDC_SET_VCC = 0x61,
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HAL_PROTO_TYPE_DCDC_RESTART = 0x62,
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HAL_PROTO_TYPE_CORE_SET_VCC = 0x63,
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HAL_PROTO_TYPE_CORE_GET_VCC = 0x64,
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HAL_PROTO_TYPE_CORE_SWITCH_FET = 0x65,
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HAL_PROTO_TYPE_CMP_VERSIONS = 0x66,
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HAL_PROTO_TYPE_CMD_LEGACY = 0x7e,
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HAL_PROTO_TYPE_CMD_SYNC = 0x80,
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HAL_PROTO_TYPE_CMD_EXECUTE = 0x81,
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@ -52,6 +57,9 @@ typedef enum {
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HAL_PROTO_TYPE_CMD_COM_RESET = 0x8b,
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HAL_PROTO_TYPE_CMD_PAUSE_LOOP = 0x8c,
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HAL_PROTO_TYPE_CMD_RESUME_LOOP = 0x8d,
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HAL_PROTO_TYPE_CMD_KILL_ALL = 0x8e,
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HAL_PROTO_TYPE_CMD_OVER_CURRENT = 0x8f,
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HAL_PROTO_TYPE_ACKNOWLEDGE = 0x91,
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HAL_PROTO_TYPE_EXCEPTION = 0x92,
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HAL_PROTO_TYPE_DATA = 0x93,
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@ -63,6 +71,121 @@ typedef enum {
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HAL_PROTO_CHECKSUM = 0x01
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} hal_proto_flags_t;
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typedef enum {
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HAL_PROTO_ERR_NONE = 0x00,
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HAL_PROTO_ERR_UNDEFINED = 0xffff,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_RAM_START = 0xFFFE,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_RAM_SIZE = 0xFFFD,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_OFFSET = 0xFFFC,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_ADDRESS = 0xFFFB,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_LENGTH = 0xFFFA,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_TYPE = 0xFFF9,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_LOCKA = 0xFFF8,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_TIMEOUT = 0xFFF7,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_ERROR = 0xFFF6,
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+
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HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_ADDRESS = 0xFFF5,
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HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_SIZE = 0xFFF4,
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HAL_PROTO_ERR_WRITE_MEM_WORD_UNKNOWN = 0xFFF3,
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+
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HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_ADDRESS = 0xFFF2,
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HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_SIZE = 0xFFF1,
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HAL_PROTO_ERR_WRITE_MEM_BYTES_UNKNOWN = 0xFFF0,
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+
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HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_ADDRESS = 0xFFEF,
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HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_SIZE = 0xFFEE,
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HAL_PROTO_ERR_WRITE_FLASH_WORD_UNKNOWN = 0xFFED,
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+
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HAL_PROTO_ERR_WRITE_FLASH_QUICK_UNKNOWN = 0xFFEC,
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+
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HAL_PROTO_ERR_START_JTAG_NO_PROTOCOL = 0xFFEB,
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HAL_PROTO_ERR_START_JTAG_PROTOCOL_UNKNOWN = 0xFFEA,
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+
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HAL_PROTO_ERR_SET_CHAIN_CONFIGURATION_STREAM = 0xFFE9,
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+
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_ADDRESS = 0xFFE8,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_VALUE = 0xFFE7,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_PC = 0xFFE6,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_SR = 0xFFE5,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_CONTROL_MASK = 0xFFE4,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_MDB = 0xFFE3,
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+
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HAL_PROTO_ERR_READ_MEM_WORD_NO_ADDRESS = 0xFFF2,
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HAL_PROTO_ERR_READ_MEM_WORD_NO_SIZE = 0xFFF1,
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+
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HAL_PROTO_ERR_READ_MEM_UNKNOWN = 0xFFE0,
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+
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HAL_PROTO_ERR_READ_MEM_BYTES_NO_ADDRESS = 0xFFDF,
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HAL_PROTO_ERR_READ_MEM_BYTES_NO_SIZE = 0xFFDE,
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+
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HAL_PROTO_ERR_PSA_NO_ADDRESS = 0xFFDD,
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HAL_PROTO_ERR_PSA_NO_SIZE = 0xFFDC,
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+
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HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_JTAG_TIMEOUT = 0xFFDB,
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HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_ADDRESS = 0xFFDA,
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HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_VALUE = 0xFFD9,
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+
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HAL_PROTO_ERR_WRITE_ALL_CPU_REGISTERS_STREAM = 0xFFD8,
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+
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HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_ADDRESS = 0xFFD7,
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HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_SIZE = 0xFFD6,
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+
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HAL_PROTO_ERR_SECURE_NO_TGT_HAS_TEST_PIN = 0xFFD5,
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+
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HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_JTAG_TIMEOUT = 0xFFD4,
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HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_ADDRESS = 0xFFD3,
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HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_VALUE = 0xFFD2,
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+
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HAL_PROTO_ERR_INSTRUCTION_BOUNDARY_ERROR = 0xFFD1,
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HAL_PROTO_ERR_JTAG_VERSION_MISMATCH = 0xFFD0,
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+
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HAL_PROTO_ERR_JTAG_MAILBOX_IN_TIMOUT = 0xFFCF,
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HAL_PROTO_ERR_JTAG_PASSWORD_WRONG = 0xFFCE,
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+
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HAL_PROTO_ERR_START_JTAG_NO_ACTIVATION_CODE = 0xFFCD,
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HAL_PROTO_ERR_SINGLESTEP_WAITFOREEM_TIMEOUT = 0xFFCC,
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+
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HAL_PROTO_ERR_CONFIG_NO_PARAMETER = 0xFFCB,
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HAL_PROTO_ERR_CONFIG_NO_VALUE = 0xFFCA,
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HAL_PROTO_ERR_CONFIG_PARAM_UNKNOWN_PARAMETER = 0xFFC9,
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+
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HAL_PROTO_ERR_NO_NUM_BITS = 0xFFC8,
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HAL_PROTO_ERR_ARRAY_SIZE_MISMATCH = 0xFFC7,
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+
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HAL_PROTO_ERR_NO_COMMAND = 0xFFC6,
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HAL_PROTO_ERR_UNKNOWN_COMMAND = 0xFFC5,
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HAL_PROTO_ERR_NO_DATA = 0xFFC4,
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HAL_PROTO_ERR_NO_BIT_SIZE = 0xFFC3,
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HAL_PROTO_ERR_INVALID_BIT_SIZE = 0xFFC2,
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+
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HAL_PROTO_ERR_UNLOCK_NO_PASSWORD_LENGTH = 0xFFC1,
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HAL_PROTO_ERR_UNLOCK_INVALID_PASSWORD_LENGTH = 0xFFC0,
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+
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HAL_PROTO_ERR_EXECUTE_FUNCLET_FINISH_TIMEOUT = 0xFFBF,
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+
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_MAXRSEL = 0xFFBE,
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+
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HAL_PROTO_ERR_API_CALL_NOT_SUPPORTED = 0xFFBD,
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+
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HAL_PROTO_ERR_MAGIC_PATTERN = 0xFFBC,
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HAL_PROTO_ERR_MAGIC_PATTERN_BOOT_DATA_CRC_WRONG = 0xFFBB,
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HAL_PROTO_ERR_DAP_NACK = 0xFFBA,
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+
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HAL_PROTO_MESSAGE_NO_RESPONSE = 0x8000,
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HAL_PROTO_EXCEPTION_NOT_IMPLEMENT_ERR = 0x8001,
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HAL_PROTO_EXCEPTION_MSGID_ERR = 0x8002,
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HAL_PROTO_EXCEPTION_CRC_ERR = 0x8003,
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HAL_PROTO_EXCEPTION_RX_TIMEOUT_ERR = 0x8004,
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HAL_PROTO_EXCEPTION_TX_TIMEOUT_ERR = 0x8005,
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HAL_PROTO_EXCEPTION_RX_OVERFLOW_ERR = 0x8006,
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HAL_PROTO_EXCEPTION_TX_NO_BUFFER = 0x8007,
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HAL_PROTO_EXCEPTION_COM_RESET = 0x8008,
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HAL_PROTO_EXCEPTION_RX_NO_BUFFER = 0x8009,
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HAL_PROTO_EXCEPTION_RX_TO_SMALL_BUFFER = 0x800A,
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HAL_PROTO_EXCEPTION_RX_LENGTH = 0x800B,
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} hal_proto_error_t;
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#define HAL_MAX_PAYLOAD 253
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struct hal_proto {
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170
drivers/v3hil.c
170
drivers/v3hil.c
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@ -41,73 +41,99 @@ typedef enum {
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HAL_PROTO_FID_SET_CHAIN_CONFIGURATION = 0x0e,
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HAL_PROTO_FID_GET_NUM_DEVICES = 0x0f,
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HAL_PROTO_FID_GET_INTERFACE_MODE = 0x10,
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HAL_PROTO_FID_SJ_ASSERT_POR_SC = 0x11,
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HAL_PROTO_FID_SJ_CONDITIONAL_SC = 0x12,
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HAL_PROTO_FID_RC_RELEASE_JTAG = 0x13,
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HAL_PROTO_FID_READ_MEM_BYTES = 0x14,
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HAL_PROTO_FID_READ_MEM_WORDS = 0x15,
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HAL_PROTO_FID_READ_MEM_QUICK = 0x16,
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HAL_PROTO_FID_WRITE_MEM_BYTES = 0x17,
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HAL_PROTO_FID_WRITE_MEM_WORDS = 0x18,
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HAL_PROTO_FID_EEM_DX = 0x19,
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HAL_PROTO_FID_EEM_DX_AFE2XX = 0x1a,
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HAL_PROTO_FID_SINGLE_STEP = 0x1b,
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HAL_PROTO_FID_READ_ALL_CPU_REGS = 0x1c,
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HAL_PROTO_FID_WRITE_ALL_CPU_REGS = 0x1d,
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HAL_PROTO_FID_PSA = 0x1e,
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HAL_PROTO_FID_EXECUTE_FUNCLET = 0x1f,
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HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG = 0x20,
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HAL_PROTO_FID_GET_DCO_FREQUENCY = 0x21,
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HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG = 0x22,
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HAL_PROTO_FID_GET_FLL_FREQUENCY = 0x23,
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HAL_PROTO_FID_GET_FLL_FREQUENCY_JTAG = 0x24,
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HAL_PROTO_FID_WAIT_FOR_STORAGE = 0x25,
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HAL_PROTO_FID_SJ_ASSERT_POR_SC_X = 0x26,
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HAL_PROTO_FID_SJ_CONDITIONAL_SC_X = 0x27,
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HAL_PROTO_FID_RC_RELEASE_JTAG_X = 0x28,
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HAL_PROTO_FID_READ_MEM_BYTES_X = 0x29,
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HAL_PROTO_FID_READ_MEM_WORDS_X = 0x2a,
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HAL_PROTO_FID_READ_MEM_QUICK_X = 0x2b,
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HAL_PROTO_FID_WRITE_MEM_BYTES_X = 0x2c,
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HAL_PROTO_FID_WRITE_MEM_WORDS_X = 0x2d,
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HAL_PROTO_FID_EEM_DX_X = 0x2e,
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HAL_PROTO_FID_SINGLE_STEP_X = 0x2f,
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HAL_PROTO_FID_READ_ALL_CPU_REGS_X = 0x30,
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HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X = 0x31,
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HAL_PROTO_FID_PSA_X = 0x32,
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HAL_PROTO_FID_EXECUTE_FUNCLET_X = 0x33,
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HAL_PROTO_FID_GET_DCO_FREQUENCY_X = 0x34,
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HAL_PROTO_FID_GET_FLL_FREQUENCY_X = 0x35,
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HAL_PROTO_FID_WAIT_FOR_STORAGE_X = 0x36,
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HAL_PROTO_FID_BLOW_FUSE_XV2 = 0x37,
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HAL_PROTO_FID_BLOW_FUSE_FRAM = 0x38,
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HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2 = 0x39,
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HAL_PROTO_FID_SJ_CONDITIONAL_SC_XV2 = 0x3a,
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HAL_PROTO_FID_RC_RELEASE_JTAG_XV2 = 0x3b,
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HAL_PROTO_FID_READ_MEM_WORDS_XV2 = 0x3c,
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HAL_PROTO_FID_READ_MEM_QUICK_XV2 = 0x3d,
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HAL_PROTO_FID_WRITE_MEM_WORDS_XV2 = 0x3e,
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HAL_PROTO_FID_EEM_DX_XV2 = 0x3f,
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HAL_PROTO_FID_SINGLE_STEP_XV2 = 0x40,
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HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2 = 0x41,
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HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2 = 0x42,
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HAL_PROTO_FID_PSA_XV2 = 0x43,
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HAL_PROTO_FID_EXECUTE_FUNCLET_XV2 = 0x44,
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HAL_PROTO_FID_UNLOCK_DEVICE_XV2 = 0x45,
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HAL_PROTO_FID_MAGIC_PATTERN = 0x46,
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HAL_PROTO_FID_UNLOCK_C092 = 0x47,
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HAL_PROTO_FID_HIL_COMMAND = 0x48,
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HAL_PROTO_FID_POLL_JSTATE_REG = 0x49,
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HAL_PROTO_FID_POLL_JSTATE_REG_FR57XX = 0x4a,
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HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN = 0x4b,
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HAL_PROTO_FID_RESET_XV2 = 0x4c,
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HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2 = 0x4d,
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HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2 = 0x4e,
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HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2 = 0x4f,
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HAL_PROTO_FID_POLL_JSTATE_REG_ET8 = 0x50,
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HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS = 0x51,
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HAL_PROTO_FID_RESET_430I = 0x52,
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HAL_PROTO_FID_POLL_JSTATE_REG_430I = 0x53
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HAL_PROTO_FID_GET_DEVICE_ID_PTR = 0x11,
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HAL_PROTO_FID_SJ_ASSERT_POR_SC ,
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HAL_PROTO_FID_SJ_CONDITIONAL_SC ,
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HAL_PROTO_FID_RC_RELEASE_JTAG ,
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HAL_PROTO_FID_READ_MEM_BYTES ,
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HAL_PROTO_FID_READ_MEM_WORDS ,
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HAL_PROTO_FID_READ_MEM_QUICK ,
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HAL_PROTO_FID_WRITE_MEM_BYTES ,
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HAL_PROTO_FID_WRITE_MEM_WORDS ,
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HAL_PROTO_FID_EEM_DX ,
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HAL_PROTO_FID_EEM_DX_AFE2XX ,
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HAL_PROTO_FID_SINGLE_STEP ,
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HAL_PROTO_FID_READ_ALL_CPU_REGS ,
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HAL_PROTO_FID_WRITE_ALL_CPU_REGS ,
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HAL_PROTO_FID_PSA ,
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HAL_PROTO_FID_EXECUTE_FUNCLET , /* 0x20 */
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HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG ,
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HAL_PROTO_FID_GET_DCO_FREQUENCY ,
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HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG ,
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HAL_PROTO_FID_GET_FLL_FREQUENCY ,
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HAL_PROTO_FID_GET_FLL_FREQUENCY_JTAG ,
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HAL_PROTO_FID_WAIT_FOR_STORAGE ,
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HAL_PROTO_FID_SJ_ASSERT_POR_SC_X ,
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HAL_PROTO_FID_SJ_CONDITIONAL_SC_X ,
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HAL_PROTO_FID_RC_RELEASE_JTAG_X ,
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HAL_PROTO_FID_READ_MEM_BYTES_X ,
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HAL_PROTO_FID_READ_MEM_WORDS_X ,
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HAL_PROTO_FID_READ_MEM_QUICK_X ,
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HAL_PROTO_FID_WRITE_MEM_BYTES_X ,
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HAL_PROTO_FID_WRITE_MEM_WORDS_X ,
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HAL_PROTO_FID_EEM_DX_X ,
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HAL_PROTO_FID_SINGLE_STEP_X ,
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HAL_PROTO_FID_READ_ALL_CPU_REGS_X ,
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HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X , /* 0x30 */
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HAL_PROTO_FID_PSA_X ,
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HAL_PROTO_FID_EXECUTE_FUNCLET_X ,
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HAL_PROTO_FID_GET_DCO_FREQUENCY_X ,
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HAL_PROTO_FID_GET_FLL_FREQUENCY_X ,
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HAL_PROTO_FID_WAIT_FOR_STORAGE_X ,
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HAL_PROTO_FID_BLOW_FUSE_XV2 ,
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HAL_PROTO_FID_BLOW_FUSE_FRAM ,
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HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2 ,
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HAL_PROTO_FID_SJ_CONDITIONAL_SC_XV2 ,
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HAL_PROTO_FID_RC_RELEASE_JTAG_XV2 ,
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HAL_PROTO_FID_READ_MEM_WORDS_XV2 ,
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HAL_PROTO_FID_READ_MEM_QUICK_XV2 ,
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HAL_PROTO_FID_WRITE_MEM_WORDS_XV2 ,
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HAL_PROTO_FID_EEM_DX_XV2 ,
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HAL_PROTO_FID_SINGLE_STEP_XV2 , /* 0x40 */
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HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2 ,
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HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2 ,
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HAL_PROTO_FID_PSA_XV2 ,
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HAL_PROTO_FID_EXECUTE_FUNCLET_XV2 ,
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HAL_PROTO_FID_UNLOCK_DEVICE_XV2 ,
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HAL_PROTO_FID_MAGIC_PATTERN ,
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HAL_PROTO_FID_UNLOCK_C092 ,
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HAL_PROTO_FID_HIL_COMMAND ,
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HAL_PROTO_FID_POLL_JSTATE_REG ,
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HAL_PROTO_FID_POLL_JSTATE_REG_FR57XX ,
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HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN ,
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HAL_PROTO_FID_RESET_XV2 ,
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HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2 ,
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HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2 ,
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HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2 ,
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HAL_PROTO_FID_POLL_JSTATE_REG_ET8 ,
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HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS , /* 0x50 */
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HAL_PROTO_FID_RESET_430I ,
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HAL_PROTO_FID_POLL_JSTATE_REG_430I ,
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HAL_PROTO_FID_POLL_JSTATE_REG_20 ,
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HAL_PROTO_FID_SWITCH_MOSFET ,
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HAL_PROTO_FID_RESET_L092 ,
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HAL_PROTO_FID_DUMMY_MACRO ,
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HAL_PROTO_FID_RESET_5438XV2 ,
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HAL_PROTO_FID_LEA_SYNC_COND ,
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HAL_PROTO_FID_GET_JTAG_ID_CODE_ARM ,
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HAL_PROTO_FID_SCAN_AP_ARM ,
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HAL_PROTO_FID_MEM_AP_TRANSACTION_ARM ,
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HAL_PROTO_FID_READ_ALL_CPU_REGS_ARM ,
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HAL_PROTO_FID_WRITE_ALL_CPU_REGS_ARM ,
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HAL_PROTO_FID_ENABLE_DEBUG_ARM ,
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HAL_PROTO_FID_DISABLE_DEBUG_ARM ,
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HAL_PROTO_FID_RUN_ARM , /* 0x60 */
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HAL_PROTO_FID_HALT_ARM ,
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HAL_PROTO_FID_RESET_ARM ,
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HAL_PROTO_FID_SINGLE_STEP_ARM ,
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HAL_PROTO_FID_WAIT_FOR_DEBUG_HALT_ARM ,
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HAL_PROTO_FID_MEM_AP_TRANSACTION_ARM_SWD,
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HAL_PROTO_FID_GET_ITF_MODE_ARM ,
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HAL_PROTO_FID_POLL_DSTATE_PCREG_ET ,
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HAL_PROTO_FID_GET_CPU_ID_ARM ,
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HAL_PROTO_FID_CHECK_DAP_LOCK_ARM ,
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HAL_PROTO_FID_UNLOCK_DAP ,
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HAL_PROTO_FID_USS_SYNC_COND , /* 0x6b */
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} hal_proto_fid_t;
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/* Argument types for HAL_PROTO_FID_CONFIGURE */
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@ -126,7 +152,15 @@ typedef enum {
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HAL_PROTO_CONFIG_SFLLDEH = 0x0c,
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HAL_PROTO_CONFIG_NO_BSL = 0x0d,
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HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ = 0x0e,
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HAL_PROTO_CONFIG_ASSERT_BSL_VALID_BIT = 0x0f
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||||
HAL_PROTO_CONFIG_ASSERT_BSL_VALID_BIT = 0x0f,
|
||||
HAL_PROTO_CONFIG_POWER_TESTREG_DEFAULT = 0x10,
|
||||
HAL_PROTO_CONFIG_POWER_TESTREGV3_DEFAULT = 0x11,
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||||
HAL_PROTO_CONFIG_WDT_ADDRESS_5XX = 0x12,
|
||||
HAL_PROTO_CONFIG_SCS_BASE_ADDRESS = 0x13,
|
||||
HAL_PROTO_CONFIG_FPB_BASE_ADDRESS = 0x14,
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||||
HAL_PROTO_CONFIG_INTERRUPT_OPTIONS = 0x15,
|
||||
HAL_PROTO_CONFIG_ULP_MSP432 = 0x16,
|
||||
HAL_PROTO_CONFIG_JTAG_LOCK_5XX = 0x17,
|
||||
} hal_proto_config_t;
|
||||
|
||||
static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src)
|
||||
|
|
|
|||
Loading…
Reference in New Issue