v3hil: add debug logging

This commit is contained in:
Triss 2022-05-19 00:46:45 +02:00
parent 9484b1cff6
commit c375f74c51
3 changed files with 68 additions and 31 deletions

View File

@ -225,6 +225,6 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
return 0; return 0;
fail: fail:
printc_err("hal_proto_execute: fid: 0x%02x\n", fid); printc_err("hal_proto_execute: fid: 0x%02x: failed\n", fid);
return -1; return -1;
} }

View File

@ -84,94 +84,94 @@ typedef enum {
HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_LOCKA = 0xFFF8, HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_LOCKA = 0xFFF8,
HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_TIMEOUT = 0xFFF7, HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_TIMEOUT = 0xFFF7,
HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_ERROR = 0xFFF6, HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_ERROR = 0xFFF6,
+
HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_ADDRESS = 0xFFF5, HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_ADDRESS = 0xFFF5,
HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_SIZE = 0xFFF4, HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_SIZE = 0xFFF4,
HAL_PROTO_ERR_WRITE_MEM_WORD_UNKNOWN = 0xFFF3, HAL_PROTO_ERR_WRITE_MEM_WORD_UNKNOWN = 0xFFF3,
+
HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_ADDRESS = 0xFFF2, HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_ADDRESS = 0xFFF2,
HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_SIZE = 0xFFF1, HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_SIZE = 0xFFF1,
HAL_PROTO_ERR_WRITE_MEM_BYTES_UNKNOWN = 0xFFF0, HAL_PROTO_ERR_WRITE_MEM_BYTES_UNKNOWN = 0xFFF0,
+
HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_ADDRESS = 0xFFEF, HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_ADDRESS = 0xFFEF,
HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_SIZE = 0xFFEE, HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_SIZE = 0xFFEE,
HAL_PROTO_ERR_WRITE_FLASH_WORD_UNKNOWN = 0xFFED, HAL_PROTO_ERR_WRITE_FLASH_WORD_UNKNOWN = 0xFFED,
+
HAL_PROTO_ERR_WRITE_FLASH_QUICK_UNKNOWN = 0xFFEC, HAL_PROTO_ERR_WRITE_FLASH_QUICK_UNKNOWN = 0xFFEC,
+
HAL_PROTO_ERR_START_JTAG_NO_PROTOCOL = 0xFFEB, HAL_PROTO_ERR_START_JTAG_NO_PROTOCOL = 0xFFEB,
HAL_PROTO_ERR_START_JTAG_PROTOCOL_UNKNOWN = 0xFFEA, HAL_PROTO_ERR_START_JTAG_PROTOCOL_UNKNOWN = 0xFFEA,
+
HAL_PROTO_ERR_SET_CHAIN_CONFIGURATION_STREAM = 0xFFE9, HAL_PROTO_ERR_SET_CHAIN_CONFIGURATION_STREAM = 0xFFE9,
+
HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_ADDRESS = 0xFFE8, HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_ADDRESS = 0xFFE8,
HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_VALUE = 0xFFE7, HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_VALUE = 0xFFE7,
HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_PC = 0xFFE6, HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_PC = 0xFFE6,
HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_SR = 0xFFE5, HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_SR = 0xFFE5,
HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_CONTROL_MASK = 0xFFE4, HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_CONTROL_MASK = 0xFFE4,
HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_MDB = 0xFFE3, HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_MDB = 0xFFE3,
+
HAL_PROTO_ERR_READ_MEM_WORD_NO_ADDRESS = 0xFFF2, HAL_PROTO_ERR_READ_MEM_WORD_NO_ADDRESS = 0xFFF2,
HAL_PROTO_ERR_READ_MEM_WORD_NO_SIZE = 0xFFF1, HAL_PROTO_ERR_READ_MEM_WORD_NO_SIZE = 0xFFF1,
+
HAL_PROTO_ERR_READ_MEM_UNKNOWN = 0xFFE0, HAL_PROTO_ERR_READ_MEM_UNKNOWN = 0xFFE0,
+
HAL_PROTO_ERR_READ_MEM_BYTES_NO_ADDRESS = 0xFFDF, HAL_PROTO_ERR_READ_MEM_BYTES_NO_ADDRESS = 0xFFDF,
HAL_PROTO_ERR_READ_MEM_BYTES_NO_SIZE = 0xFFDE, HAL_PROTO_ERR_READ_MEM_BYTES_NO_SIZE = 0xFFDE,
+
HAL_PROTO_ERR_PSA_NO_ADDRESS = 0xFFDD, HAL_PROTO_ERR_PSA_NO_ADDRESS = 0xFFDD,
HAL_PROTO_ERR_PSA_NO_SIZE = 0xFFDC, HAL_PROTO_ERR_PSA_NO_SIZE = 0xFFDC,
+
HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_JTAG_TIMEOUT = 0xFFDB, HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_JTAG_TIMEOUT = 0xFFDB,
HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_ADDRESS = 0xFFDA, HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_ADDRESS = 0xFFDA,
HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_VALUE = 0xFFD9, HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_VALUE = 0xFFD9,
+
HAL_PROTO_ERR_WRITE_ALL_CPU_REGISTERS_STREAM = 0xFFD8, HAL_PROTO_ERR_WRITE_ALL_CPU_REGISTERS_STREAM = 0xFFD8,
+
HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_ADDRESS = 0xFFD7, HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_ADDRESS = 0xFFD7,
HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_SIZE = 0xFFD6, HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_SIZE = 0xFFD6,
+
HAL_PROTO_ERR_SECURE_NO_TGT_HAS_TEST_PIN = 0xFFD5, HAL_PROTO_ERR_SECURE_NO_TGT_HAS_TEST_PIN = 0xFFD5,
+
HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_JTAG_TIMEOUT = 0xFFD4, HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_JTAG_TIMEOUT = 0xFFD4,
HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_ADDRESS = 0xFFD3, HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_ADDRESS = 0xFFD3,
HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_VALUE = 0xFFD2, HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_VALUE = 0xFFD2,
+
HAL_PROTO_ERR_INSTRUCTION_BOUNDARY_ERROR = 0xFFD1, HAL_PROTO_ERR_INSTRUCTION_BOUNDARY_ERROR = 0xFFD1,
HAL_PROTO_ERR_JTAG_VERSION_MISMATCH = 0xFFD0, HAL_PROTO_ERR_JTAG_VERSION_MISMATCH = 0xFFD0,
+
HAL_PROTO_ERR_JTAG_MAILBOX_IN_TIMOUT = 0xFFCF, HAL_PROTO_ERR_JTAG_MAILBOX_IN_TIMOUT = 0xFFCF,
HAL_PROTO_ERR_JTAG_PASSWORD_WRONG = 0xFFCE, HAL_PROTO_ERR_JTAG_PASSWORD_WRONG = 0xFFCE,
+
HAL_PROTO_ERR_START_JTAG_NO_ACTIVATION_CODE = 0xFFCD, HAL_PROTO_ERR_START_JTAG_NO_ACTIVATION_CODE = 0xFFCD,
HAL_PROTO_ERR_SINGLESTEP_WAITFOREEM_TIMEOUT = 0xFFCC, HAL_PROTO_ERR_SINGLESTEP_WAITFOREEM_TIMEOUT = 0xFFCC,
+
HAL_PROTO_ERR_CONFIG_NO_PARAMETER = 0xFFCB, HAL_PROTO_ERR_CONFIG_NO_PARAMETER = 0xFFCB,
HAL_PROTO_ERR_CONFIG_NO_VALUE = 0xFFCA, HAL_PROTO_ERR_CONFIG_NO_VALUE = 0xFFCA,
HAL_PROTO_ERR_CONFIG_PARAM_UNKNOWN_PARAMETER = 0xFFC9, HAL_PROTO_ERR_CONFIG_PARAM_UNKNOWN_PARAMETER = 0xFFC9,
+
HAL_PROTO_ERR_NO_NUM_BITS = 0xFFC8, HAL_PROTO_ERR_NO_NUM_BITS = 0xFFC8,
HAL_PROTO_ERR_ARRAY_SIZE_MISMATCH = 0xFFC7, HAL_PROTO_ERR_ARRAY_SIZE_MISMATCH = 0xFFC7,
+
HAL_PROTO_ERR_NO_COMMAND = 0xFFC6, HAL_PROTO_ERR_NO_COMMAND = 0xFFC6,
HAL_PROTO_ERR_UNKNOWN_COMMAND = 0xFFC5, HAL_PROTO_ERR_UNKNOWN_COMMAND = 0xFFC5,
HAL_PROTO_ERR_NO_DATA = 0xFFC4, HAL_PROTO_ERR_NO_DATA = 0xFFC4,
HAL_PROTO_ERR_NO_BIT_SIZE = 0xFFC3, HAL_PROTO_ERR_NO_BIT_SIZE = 0xFFC3,
HAL_PROTO_ERR_INVALID_BIT_SIZE = 0xFFC2, HAL_PROTO_ERR_INVALID_BIT_SIZE = 0xFFC2,
+
HAL_PROTO_ERR_UNLOCK_NO_PASSWORD_LENGTH = 0xFFC1, HAL_PROTO_ERR_UNLOCK_NO_PASSWORD_LENGTH = 0xFFC1,
HAL_PROTO_ERR_UNLOCK_INVALID_PASSWORD_LENGTH = 0xFFC0, HAL_PROTO_ERR_UNLOCK_INVALID_PASSWORD_LENGTH = 0xFFC0,
+
HAL_PROTO_ERR_EXECUTE_FUNCLET_FINISH_TIMEOUT = 0xFFBF, HAL_PROTO_ERR_EXECUTE_FUNCLET_FINISH_TIMEOUT = 0xFFBF,
+
HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_MAXRSEL = 0xFFBE, HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_MAXRSEL = 0xFFBE,
+
HAL_PROTO_ERR_API_CALL_NOT_SUPPORTED = 0xFFBD, HAL_PROTO_ERR_API_CALL_NOT_SUPPORTED = 0xFFBD,
+
HAL_PROTO_ERR_MAGIC_PATTERN = 0xFFBC, HAL_PROTO_ERR_MAGIC_PATTERN = 0xFFBC,
HAL_PROTO_ERR_MAGIC_PATTERN_BOOT_DATA_CRC_WRONG = 0xFFBB, HAL_PROTO_ERR_MAGIC_PATTERN_BOOT_DATA_CRC_WRONG = 0xFFBB,
HAL_PROTO_ERR_DAP_NACK = 0xFFBA, HAL_PROTO_ERR_DAP_NACK = 0xFFBA,
+
HAL_PROTO_MESSAGE_NO_RESPONSE = 0x8000, HAL_PROTO_MESSAGE_NO_RESPONSE = 0x8000,
HAL_PROTO_EXCEPTION_NOT_IMPLEMENT_ERR = 0x8001, HAL_PROTO_EXCEPTION_NOT_IMPLEMENT_ERR = 0x8001,
HAL_PROTO_EXCEPTION_MSGID_ERR = 0x8002, HAL_PROTO_EXCEPTION_MSGID_ERR = 0x8002,

View File

@ -16,6 +16,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <stdbool.h>
#include <string.h> #include <string.h>
#include "bytes.h" #include "bytes.h"
#include "v3hil.h" #include "v3hil.h"
@ -23,6 +24,12 @@
#include "output.h" #include "output.h"
#include "opdb.h" #include "opdb.h"
#ifdef DEBUG_V3HIL
#define dbg_printc(fmt, ...) printc_dbg("v3hil: " fmt, ##__VA_ARGS__)
#else
#define dbg_printc(fmt, ...) do{}while(0)
#endif
/* HAL function IDs */ /* HAL function IDs */
typedef enum { typedef enum {
HAL_PROTO_FID_INIT = 0x01, HAL_PROTO_FID_INIT = 0x01,
@ -167,7 +174,8 @@ static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src)
{ {
hal_proto_fid_t dst = h->chip->v3_functions[src]; hal_proto_fid_t dst = h->chip->v3_functions[src];
return dst ? dst : src; dbg_printc("map fid: %02x -> %02x\n", src, dst);
return dst;
} }
void v3hil_init(struct v3hil *h, transport_t trans, void v3hil_init(struct v3hil *h, transport_t trans,
@ -182,6 +190,7 @@ int v3hil_set_vcc(struct v3hil *h, int vcc_mv)
uint8_t data[2]; uint8_t data[2];
w16le(data, vcc_mv); w16le(data, vcc_mv);
dbg_printc("Setting VCC...\n");
return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_VCC, data, 2); return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_VCC, data, 2);
} }
@ -221,6 +230,7 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
uint8_t data = type; uint8_t data = type;
uint8_t chain_id[2] = {0, 0}; uint8_t chain_id[2] = {0, 0};
dbg_printc("Start JTAG...\n");
if (hal_proto_execute(&h->hal, HAL_PROTO_FID_START_JTAG, if (hal_proto_execute(&h->hal, HAL_PROTO_FID_START_JTAG,
&data, 1) < 0) &data, 1) < 0)
return -1; return -1;
@ -242,6 +252,7 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
int v3hil_stop_jtag(struct v3hil *h) int v3hil_stop_jtag(struct v3hil *h)
{ {
dbg_printc("Stop JTAG...\n");
return hal_proto_execute(&h->hal, HAL_PROTO_FID_STOP_JTAG, NULL, 0); return hal_proto_execute(&h->hal, HAL_PROTO_FID_STOP_JTAG, NULL, 0);
} }
@ -272,6 +283,7 @@ int v3hil_sync(struct v3hil *h)
/* We can't use map_fid() because h->chip might be NULL -- this /* We can't use map_fid() because h->chip might be NULL -- this
* function will be called before identification is complete. * function will be called before identification is complete.
*/ */
dbg_printc("Sync: assert POR\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
(h->jtag_id == 0x89) (h->jtag_id == 0x89)
? HAL_PROTO_FID_SJ_ASSERT_POR_SC ? HAL_PROTO_FID_SJ_ASSERT_POR_SC
@ -308,6 +320,7 @@ int v3hil_read(struct v3hil *h, address_t addr,
w32le(req + 4, (m->bits == 8) ? size : (size >> 1)); w32le(req + 4, (m->bits == 8) ? size : (size >> 1));
w32le(req + 8, h->regs[MSP430_REG_PC]); w32le(req + 8, h->regs[MSP430_REG_PC]);
dbg_printc("do read\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_READ_MEM_BYTES : map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_READ_MEM_BYTES :
HAL_PROTO_FID_READ_MEM_WORDS), HAL_PROTO_FID_READ_MEM_WORDS),
@ -366,6 +379,7 @@ static int calibrate_dco(struct v3hil *h, uint8_t max_bcs)
w16le(data, ram->offset); w16le(data, ram->offset);
w16le(data + 2, max_bcs); w16le(data + 2, max_bcs);
dbg_printc("calibrate dco: get freq\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY), map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
data, 6) < 0) data, 6) < 0)
@ -384,6 +398,7 @@ static int calibrate_dco(struct v3hil *h, uint8_t max_bcs)
mem_write[9] = data[2]; /* BCS1 */ mem_write[9] = data[2]; /* BCS1 */
mem_write[10] = data[4]; /* BCS2 */ mem_write[10] = data[4]; /* BCS2 */
mem_write[11] = 0; /* pad */ mem_write[11] = 0; /* pad */
dbg_printc("calibrate dco: write\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES), map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
mem_write, 12) < 0) { mem_write, 12) < 0) {
@ -412,6 +427,7 @@ static int calibrate_fll(struct v3hil *h)
w16le(data, ram->offset); w16le(data, ram->offset);
w16le(data + 2, 0); w16le(data + 2, 0);
dbg_printc("calibrate fll: get dco freq\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY), map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
data, 10) < 0) data, 10) < 0)
@ -433,6 +449,7 @@ static int calibrate_fll(struct v3hil *h)
mem_write[12] = data[8]; /* FLLCTL1 */ mem_write[12] = data[8]; /* FLLCTL1 */
mem_write[13] = 0; /* pad */ mem_write[13] = 0; /* pad */
dbg_printc("calibrate fll: write\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES), map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
mem_write, 14) < 0) { mem_write, 14) < 0) {
@ -504,6 +521,7 @@ static int upload_funclet(struct v3hil *h,
for (i = 0; i < n; i++) for (i = 0; i < n; i++)
w16le(data + 8 + i * 2, code[i]); w16le(data + 8 + i * 2, code[i]);
dbg_printc("upload funclet: %d\n", n);
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_WRITE_MEM_WORDS), map_fid(h, HAL_PROTO_FID_WRITE_MEM_WORDS),
data, n * 2 + 8) < 0) { data, n * 2 + 8) < 0) {
@ -537,8 +555,10 @@ static int write_flash(struct v3hil *h, address_t addr,
return -1; return -1;
} }
dbg_printc("write flash: calibrate\n");
if (calibrate(h) < 0) if (calibrate(h) < 0)
return -1; return -1;
dbg_printc("write flash: upload funclet\n");
if (upload_funclet(h, ram, f) < 0) if (upload_funclet(h, ram, f) < 0)
return -1; return -1;
@ -563,6 +583,7 @@ static int write_flash(struct v3hil *h, address_t addr,
w16le(data + 20, h->cal.cal1); w16le(data + 20, h->cal.cal1);
memcpy(data + 22, mem, size); memcpy(data + 22, mem, size);
dbg_printc("exec write flash funclet\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET), map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
data, size + 22) < 0) { data, size + 22) < 0) {
@ -584,6 +605,7 @@ static int write_ram(struct v3hil *h, const struct chipinfo_memory *m,
memcpy(data + 8, mem, size); memcpy(data + 8, mem, size);
dbg_printc("write ram\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES
: HAL_PROTO_FID_WRITE_MEM_WORDS), : HAL_PROTO_FID_WRITE_MEM_WORDS),
@ -610,9 +632,11 @@ int v3hil_write(struct v3hil *h, address_t addr,
if (size > 128) if (size > 128)
size = 128; size = 128;
dbg_printc("write: call write flash\n");
if (m->type == CHIPINFO_MEMTYPE_FLASH) if (m->type == CHIPINFO_MEMTYPE_FLASH)
return write_flash(h, addr, mem, size); return write_flash(h, addr, mem, size);
dbg_printc("call write ram\n");
return write_ram(h, m, addr, mem, size); return write_ram(h, m, addr, mem, size);
} }
@ -637,6 +661,7 @@ static int call_erase(struct v3hil *h,
w16le(data + 20, h->cal.cal1); w16le(data + 20, h->cal.cal1);
w32le(data + 22, 0xdeadbeef); w32le(data + 22, 0xdeadbeef);
dbg_printc("erase: call funclet\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET), map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
data, 26) < 0) { data, 26) < 0) {
@ -670,8 +695,10 @@ int v3hil_erase(struct v3hil *h, address_t segment)
if (!flash) if (!flash)
printc_err("v3hil: can't find appropriate flash region\n"); printc_err("v3hil: can't find appropriate flash region\n");
dbg_printc("erase: calibrate\n");
if (calibrate(h) < 0) if (calibrate(h) < 0)
return -1; return -1;
dbg_printc("erase: upload funclet\n");
if (upload_funclet(h, ram, f) < 0) if (upload_funclet(h, ram, f) < 0)
return -1; return -1;
@ -682,10 +709,13 @@ int v3hil_erase(struct v3hil *h, address_t segment)
if (flash->banks) if (flash->banks)
bank_size /= flash->banks; bank_size /= flash->banks;
for (i = flash->banks; i >= 0; i--) for (i = flash->banks; i >= 0; i--) {
dbg_printc("Erase bank %d\n", i);
if (call_erase(h, ram, f, if (call_erase(h, ram, f,
flash->offset + i * bank_size - 2, 0xa502) < 0) flash->offset + i * bank_size - 2, 0xa502) < 0)
return -1; return -1;
}
} else { } else {
segment &= ~(flash->seg_size - 1); segment &= ~(flash->seg_size - 1);
segment |= flash->seg_size - 2; segment |= flash->seg_size - 2;
@ -705,6 +735,7 @@ int v3hil_update_regs(struct v3hil *h)
int i; int i;
int sptr = 0; int sptr = 0;
dbg_printc("Read regs\n");
if (hal_proto_execute(&h->hal, fid, NULL, 0) < 0) { if (hal_proto_execute(&h->hal, fid, NULL, 0) < 0) {
printc_err("v3hil: can't read CPU registers\n"); printc_err("v3hil: can't read CPU registers\n");
return -1; return -1;
@ -758,6 +789,7 @@ int v3hil_flush_regs(struct v3hil *h)
} }
} }
dbg_printc("Write regs\n");
if (hal_proto_execute(&h->hal, fid, data, reg_size * 13) < 0) { if (hal_proto_execute(&h->hal, fid, data, reg_size * 13) < 0) {
printc_err("v3hil: can't write CPU registers\n"); printc_err("v3hil: can't write CPU registers\n");
return -1; return -1;
@ -781,6 +813,7 @@ int v3hil_context_restore(struct v3hil *h, int free)
data[10] = free ? 7 : 6; data[10] = free ? 7 : 6;
data[14] = free ? 1 : 0; data[14] = free ? 1 : 0;
dbg_printc("Context restore\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_RC_RELEASE_JTAG), map_fid(h, HAL_PROTO_FID_RC_RELEASE_JTAG),
data, 18) < 0) { data, 18) < 0) {
@ -803,6 +836,7 @@ int v3hil_context_save(struct v3hil *h)
data[2] = h->wdtctl | 0x80; data[2] = h->wdtctl | 0x80;
data[3] = 0x5a; /* WDTPW */ data[3] = 0x5a; /* WDTPW */
dbg_printc("Context save\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_SJ_CONDITIONAL_SC), map_fid(h, HAL_PROTO_FID_SJ_CONDITIONAL_SC),
data, 8) < 0) data, 8) < 0)
@ -834,6 +868,7 @@ int v3hil_single_step(struct v3hil *h)
data[9] = h->regs[MSP430_REG_SR] >> 8; data[9] = h->regs[MSP430_REG_SR] >> 8;
data[10] = 7; data[10] = 7;
dbg_printc("Single-stepping...\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_SINGLE_STEP), map_fid(h, HAL_PROTO_FID_SINGLE_STEP),
data, 18) < 0) { data, 18) < 0) {
@ -868,6 +903,8 @@ static int set_param(struct v3hil *fet, hal_proto_config_t cfg,
} }
data[0] = cfg; data[0] = cfg;
dbg_printc("Set param 0x%02x to 0x%08x\n", cfg, value);
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_CONFIGURE, if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_CONFIGURE,
data, 8) < 0) { data, 8) < 0) {
printc_err("v3hil: can't set param 0x%02x to 0x%08x\n", printc_err("v3hil: can't set param 0x%02x to 0x%08x\n",