[simio] support Timer_B
Timer_B is identical to Timer_A with the following exceptions. 1. The SCCI bit function is not implemented in Timer_B. 2. The interrupt vector word of TBIFG is different than TAIFG one. 3. The length of Timer_B is programable to be 8, 10, 12, or 16 bits. 4. Timer_B TBCCRx registers can be double-buffered. 5. Timer_B TBCCRx registers can be grouped. This change implements 1, 2, and 3. Double-buffering and grouping TBCCRx will be following.
This commit is contained in:
Tadashi G. Takaoka
parent
8db02ae3d4
commit
f9f897e95e
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@ -36,13 +36,18 @@
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#define TACLR 0x0004 /* Timer A counter clear */
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#define TAIE 0x0002 /* Timer A counter interrupt enable */
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#define TAIFG 0x0001 /* Timer A counter interrupt flag */
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/* TBCTL bits */
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#define TBCLGRP1 0x4000 /* Timer B Compare latch load group 1 */
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#define TBCLGRP0 0x2000 /* Timer B Compare latch load group 0 */
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#define CNTL1 0x1000 /* Timer B Counter length 1 */
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#define CNTL0 0x0800 /* Timer B Counter length 0 */
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/* TACCTLx flags (taken from mspgcc) */
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#define CM1 0x8000 /* Capture mode 1 */
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#define CM0 0x4000 /* Capture mode 0 */
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#define CCIS1 0x2000 /* Capture input select 1 */
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#define CCIS0 0x1000 /* Capture input select 0 */
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#define SCS 0x0800 /* Capture sychronize */
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#define SCS 0x0800 /* Capture synchronize */
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#define SCCI 0x0400 /* Latched capture signal (read) */
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#define CAP 0x0100 /* Capture mode: 1 /Compare mode : 0 */
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#define OUTMOD2 0x0080 /* Output mode 2 */
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@ -53,9 +58,20 @@
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/* #define OUT 0x0004 PWM Output signal if output mode 0 */
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#define COV 0x0002 /* Capture/compare overflow flag */
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#define CCIFG 0x0001 /* Capture/compare interrupt flag */
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/* TBCCTLx flags */
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#define CLLD1 0x0400 /* Compare latch load source 1 */
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#define CLLD0 0x0200 /* Compare latch load source 0 */
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/* Timer IV words */
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#define TAIV_TAIFG 0x000A /* Interrupt vector word for TAIFG */
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#define TBIV_TBIFG 0x000E /* Interrupt vector word for TBIFG */
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#define MAX_CCRS 7
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typedef enum {
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TIMER_TYPE_A,
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TIMER_TYPE_B,
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} timer_type_t;
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struct timer {
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struct simio_device base;
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@ -67,6 +83,7 @@ struct timer {
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address_t iv_addr;
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int irq0;
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int irq1;
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timer_type_t timer_type;
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/* IO registers */
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uint16_t tactl;
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@ -110,6 +127,7 @@ static struct simio_device *timer_create(char **arg_text)
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tr->iv_addr = 0x12e;
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tr->irq0 = 9;
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tr->irq1 = 8;
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tr->timer_type = TIMER_TYPE_A;
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return (struct simio_device *)tr;
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}
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@ -149,6 +167,28 @@ static int config_addr(address_t *addr, char **arg_text)
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return 0;
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}
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static int config_type(timer_type_t *timer_type, char **arg_text)
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{
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char *text = get_arg(arg_text);
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if (!text) {
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printc_err("timer: config: expected type\n");
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return -1;
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}
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if (!strcasecmp(text, "A")) {
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*timer_type = TIMER_TYPE_A;
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return 0;
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}
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if (!strcasecmp(text, "B")) {
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*timer_type = TIMER_TYPE_B;
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return 0;
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}
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printc_err("timer: can't parse type: %s\n", text);
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return -1;
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}
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static int config_irq(int *irq, char **arg_text)
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{
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char *text = get_arg(arg_text);
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@ -237,6 +277,8 @@ static int timer_config(struct simio_device *dev,
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if (!strcasecmp(param, "base"))
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return config_addr(&tr->base_addr, arg_text);
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if (!strcasecmp(param, "type"))
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return config_type(&tr->timer_type, arg_text);
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if (!strcasecmp(param, "iv"))
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return config_addr(&tr->iv_addr, arg_text);
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if (!strcasecmp(param, "irq0"))
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@ -266,7 +308,8 @@ static uint16_t calc_iv(struct timer *tr, int update)
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if ((tr->tactl & (TAIFG | TAIE)) == (TAIFG | TAIE)) {
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if (update)
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tr->tactl &= ~TAIFG;
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return 0xa;
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return (tr->timer_type == TIMER_TYPE_A) ?
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TAIV_TAIFG : TBIV_TBIFG;
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}
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return 0;
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@ -276,24 +319,44 @@ static int timer_info(struct simio_device *dev)
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{
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struct timer *tr = (struct timer *)dev;
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int i;
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char timer_type = (tr->timer_type == TIMER_TYPE_A) ? 'A' : 'B';
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printc("Base address: 0x%04x\n", tr->base_addr);
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printc("IV address: 0x%04x\n", tr->iv_addr);
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printc("IRQ0: %d\n", tr->irq0);
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printc("IRQ1: %d\n", tr->irq1);
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printc("\n");
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printc("TACTL: 0x%04x\n", tr->tactl);
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printc("TAR: 0x%04x\n", tr->tar);
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printc("TAIV: 0x%02x\n", calc_iv(tr, 0));
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printc("T%cCTL: 0x%04x\n", timer_type, tr->tactl);
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printc("T%cR: 0x%04x\n", timer_type, tr->tar);
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printc("T%cIV: 0x%02x\n", timer_type, calc_iv(tr, 0));
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printc("\n");
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for (i = 0; i < tr->size; i++)
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printc("Channel %2d, TACCTL = 0x%04x, TACCR = 0x%04x\n",
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i, tr->ctls[i], tr->ccrs[i]);
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for (i = 0; i < tr->size; i++) {
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printc("T%cCCTL%d = 0x%04x, T%cCCR%d = 0x%04x",
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timer_type, i, tr->ctls[i], timer_type, i, tr->ccrs[i]);
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printc("\n");
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}
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return 0;
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}
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static uint16_t tar_mask(struct timer *tr)
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{
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if (tr->timer_type == TIMER_TYPE_B) {
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switch (tr->tactl & (CNTL1 | CNTL0)) {
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case 0: /* 16 bits */
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break;
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case CNTL0: /* 12 bits */
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return 0x0fff;
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case CNTL1: /* 10 bits */
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return 0x03ff;
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case CNTL1 | CNTL0: /* 8 bits */
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return 0x00ff;
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}
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}
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return 0xffff;
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}
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static int timer_write(struct simio_device *dev,
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address_t addr, uint16_t data)
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{
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@ -308,7 +371,7 @@ static int timer_write(struct simio_device *dev,
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}
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if (addr == tr->base_addr + 0x10) {
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tr->tar = data;
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tr->tar = data & tar_mask(tr);
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return 0;
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}
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@ -316,8 +379,13 @@ static int timer_write(struct simio_device *dev,
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addr < tr->base_addr + (tr->size << 1) + 2) {
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int index = ((addr & 0xf) - 2) >> 1;
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uint16_t oldval = tr->ctls[index];
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uint16_t mask;
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tr->ctls[index] = (data & 0xf9f7) | (oldval & 0x0608);
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if (tr->timer_type == TIMER_TYPE_A)
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mask = 0x0608;
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if (tr->timer_type == TIMER_TYPE_B)
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mask = 0x0008;
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tr->ctls[index] = (data & ~mask) | (oldval & mask);
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/* Check capture initiated by Software */
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if ((data & (CAP | CCIS1)) == (CAP | CCIS1))
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trigger_capture(tr, index, oldval & CCI, data & CCIS0);
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@ -409,23 +477,37 @@ static void timer_ack_interrupt(struct simio_device *dev, int irq)
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/* By design irq1 does not clear CCIFG or TAIFG automatically */
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}
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static uint16_t tar_increment(struct timer *tr)
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{
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tr->tar++;
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tr->tar &= tar_mask(tr);
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return tr->tar;
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}
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static uint16_t tar_decrement(struct timer *tr)
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{
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tr->tar--;
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tr->tar &= tar_mask(tr);
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return tr->tar;
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}
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static void tar_step(struct timer *tr)
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{
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switch ((tr->tactl >> 4) & 3) {
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case 0: break;
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case 0:
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break;
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case 1:
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if (tr->tar == tr->ccrs[0] || tr->go_down) {
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tr->tar = 0;
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tr->tactl |= TAIFG;
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tr->go_down = false;
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} else {
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tr->tar++;
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tar_increment(tr);
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}
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break;
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case 2:
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tr->tar++;
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if (!tr->tar)
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if (tar_increment(tr) == 0)
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tr->tactl |= TAIFG;
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break;
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@ -436,16 +518,34 @@ static void tar_step(struct timer *tr)
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tr->go_down = false;
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if (tr->go_down) {
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tr->tar--;
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if (!tr->tar)
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if (tar_decrement(tr) == 0)
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tr->tactl |= TAIFG;
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} else {
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tr->tar++;
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tar_increment(tr);
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}
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break;
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}
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}
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static void comparator_step(struct timer *tr, int index)
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{
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if (tr->timer_type == TIMER_TYPE_A) {
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if (tr->tar == tr->ccrs[index]) {
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tr->ctls[index] |= CCIFG;
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if (tr->ctls[index] & CCI)
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tr->ctls[index] |= SCCI;
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else
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tr->ctls[index] &= ~SCCI;
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}
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}
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if (tr->timer_type == TIMER_TYPE_B) {
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if (tr->tar == tr->ccrs[index]) {
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tr->ctls[index] |= CCIFG;
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}
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}
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}
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static void timer_step(struct simio_device *dev,
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uint16_t status, const int *clocks)
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{
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@ -471,16 +571,10 @@ static void timer_step(struct simio_device *dev,
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for (i = 0; i < pulse_count; i++) {
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int j;
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for (j = 0; j < tr->size; j++)
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if (!(tr->ctls[j] & CAP) && (tr->tar == tr->ccrs[j])) {
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if (tr->ctls[j] & CCI)
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tr->ctls[j] |= SCCI;
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else
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tr->ctls[j] &= ~SCCI;
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tr->ctls[j] |= CCIFG;
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for (j = 0; j < tr->size; j++) {
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if (!(tr->ctls[j] & CAP))
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comparator_step(tr, j);
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}
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tar_step(tr);
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}
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}
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@ -488,22 +582,24 @@ static void timer_step(struct simio_device *dev,
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const struct simio_class simio_timer = {
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.name = "timer",
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.help =
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"This peripheral implements the Timer_A module.\n"
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"\n"
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"Constructor arguments: [size]\n"
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" Specify the number of capture/compare registers.\n"
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"\n"
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"Config arguments are:\n"
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" base <address>\n"
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" Set the peripheral base address.\n"
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" irq0 <interrupt>\n"
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" Set the interrupt vector for CCR0.\n"
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" irq1 <interrupt>\n"
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" Set the interrupt vector for CCR1.\n"
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" iv <address>\n"
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" Set the interrupt vector register address.\n"
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" set <channel> <0|1>\n"
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" Set the capture input value on the given channel.\n",
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"This peripheral implements the Timer_A and Timer_B module.\n"
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"\n"
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"Constructor arguments: [size]\n"
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" Specify the number of capture/compare registers.\n"
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"\n"
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"Config arguments are:\n"
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" base <address>\n"
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" Set the peripheral base address.\n"
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" type <A|B>\n"
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" Set timer type.\n"
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" irq0 <interrupt>\n"
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" Set the interrupt vector for CCR0.\n"
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" irq1 <interrupt>\n"
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" Set the interrupt vector for CCR1.\n"
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" iv <address>\n"
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" Set the interrupt vector register address.\n"
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" set <channel> <0|1>\n"
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" Set the capture input value on the given channel.\n",
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.create = timer_create,
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.destroy = timer_destroy,
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@ -71,7 +71,6 @@ static int config_timer(struct simio_device *dev, const char *param,
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#define TxCCTL(index) (0x02 + (index) * 2)
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#define TxCCR(index) (0x12 + (index) * 2)
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#define TxIV_TxIFG(index) ((index) * 2)
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#define TAIV_TAIFG 0x0a
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static uint16_t read_timer(struct simio_device *dev, int offset)
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{
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@ -185,6 +184,7 @@ static void test_create_no_option()
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// Check default values.
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->size == 3);
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assert(tmr->timer_type == TIMER_TYPE_A);
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assert(tmr->base_addr == 0x0160);
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assert(tmr->iv_addr == 0x012e);
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assert(tmr->irq0 == 9);
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@ -226,6 +226,53 @@ static void test_create_with_size_1()
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assert(dev == NULL);
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}
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static void test_config_type_default()
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{
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dev = create_timer("");
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// Default timer type is A.
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->timer_type == TIMER_TYPE_A);
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}
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static void test_config_type_A()
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{
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dev = create_timer("");
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// Timer can configured as type A.
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assert(config_timer(dev, "type", "A") == 0);
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->timer_type == TIMER_TYPE_A);
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}
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static void test_config_type_B()
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{
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dev = create_timer("");
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// Timer can configured as type B.
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struct timer *tmr = (struct timer *)dev;
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assert(config_timer(dev, "type", "B") == 0);
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assert(tmr->timer_type == TIMER_TYPE_B);
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}
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static void test_config_type_bad()
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{
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dev = create_timer("");
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struct timer *tmr = (struct timer *)dev;
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// Timer can't configured other than A/B.
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assert(config_timer(dev, "type", "bad") != 0);
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}
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static void test_config_type_empty()
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{
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dev = create_timer("");
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struct timer *tmr = (struct timer *)dev;
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// Timer type can't be empty.
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assert(config_timer(dev, "type", "") != 0);
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}
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static void test_address_space()
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{
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dev = create_timer("7");
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@ -319,7 +366,7 @@ static void test_timer_updown_stop()
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assert(read_timer(dev, TxR) == 0);
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}
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static void test_timer_up()
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static void test_timer_a_up()
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{
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dev = create_timer("");
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@ -348,7 +395,7 @@ static void test_timer_up()
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assert(check_noirq(dev));
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}
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static void test_timer_up_change_period()
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static void test_timer_a_up_change_period()
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{
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dev = create_timer("");
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@ -396,7 +443,7 @@ static void test_timer_up_change_period()
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assert_not(read_timer(dev, TxCTL) & TAIFG);
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}
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static void test_timer_updown_change_period()
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static void test_timer_a_updown_change_period()
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{
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dev = create_timer("");
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@ -657,7 +704,7 @@ static void test_timer_capture_by_signal()
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assert(read_timer(dev, TxCCR(2)) == 50);
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}
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static void test_timer_compare()
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static void test_timer_a_compare()
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{
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dev = create_timer("");
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@ -722,6 +769,142 @@ static void test_timer_compare()
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assert_not(read_timer(dev, TxCCTL(1)) & SCCI);
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}
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static void test_timer_b_compare()
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{
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dev = create_timer("");
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config_timer(dev, "type", "B");
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/* Continuous mode, ACLK, interrupt enable, clear */
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write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR | TAIE);
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write_timer(dev, TxR, 0xffff);
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/* Compare mode, enable interrupts */
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCR(0), 200);
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write_timer(dev, TxCCTL(1), CCIE);
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write_timer(dev, TxCCR(1), 100);
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write_timer(dev, TxCCTL(2), CCIE);
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write_timer(dev, TxCCR(2), 200);
|
||||
|
||||
// Timer_B overflow interrupt should happen.
|
||||
step_aclk(dev, 1);
|
||||
assert(check_irq1(dev));
|
||||
// Timer_B overflow vector is 0x0e.
|
||||
assert(TBIV_TBIFG == 0x0e);
|
||||
assert(read_iv(dev) == TBIV_TBIFG);
|
||||
assert(check_noirq(dev));
|
||||
assert(read_timer(dev, TxR) == 0);
|
||||
|
||||
step_aclk(dev, 100);
|
||||
assert(check_noirq(dev));
|
||||
// Set CCI of CCTL[1] to 1.
|
||||
config_timer(dev, "set", "1 1");
|
||||
// Timer_B comparator interrupt should happen.
|
||||
step_aclk(dev, 1);
|
||||
assert(check_irq1(dev));
|
||||
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
||||
assert(read_iv(dev) == TxIV_TxIFG(1));
|
||||
assert(check_noirq(dev));
|
||||
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
||||
|
||||
// Timer_B comparator interrupts should happen.
|
||||
step_aclk(dev, 100);
|
||||
assert(check_irq0(dev));
|
||||
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
||||
ack_irq0(dev);
|
||||
assert_not(check_noirq(dev));
|
||||
assert_not(read_timer(dev, TxCCTL(0)) & CCIFG);
|
||||
// Lower priority interrupt.
|
||||
assert(check_irq1(dev));
|
||||
assert(read_timer(dev, TxCCTL(2)) & CCIFG);
|
||||
assert(read_iv(dev) == TxIV_TxIFG(2));
|
||||
assert(check_noirq(dev));
|
||||
assert_not(read_timer(dev, TxCCTL(2)) & CCIFG);
|
||||
|
||||
// Set CCI of CCTL[1] to 0.
|
||||
config_timer(dev, "set", "1 0");
|
||||
write_timer(dev, TxCCR(1), 300);
|
||||
step_aclk(dev, 100);
|
||||
// Timer_B comparator interrupt should happen.
|
||||
assert(check_irq1(dev));
|
||||
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
||||
assert(read_iv(dev) == TxIV_TxIFG(1));
|
||||
assert(check_noirq(dev));
|
||||
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
||||
}
|
||||
|
||||
static void test_timer_capture()
|
||||
{
|
||||
dev = create_timer("");
|
||||
|
||||
/* Continuous mode, ACLK, clear */
|
||||
write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR);
|
||||
/* Capture mode, enable interrupts */
|
||||
}
|
||||
|
||||
static void test_timer_b_length_8()
|
||||
{
|
||||
dev = create_timer("");
|
||||
config_timer(dev, "type", "B");
|
||||
|
||||
/* Continuous 8 bit, SMCLK, interrupt enable, clear */
|
||||
write_timer(dev, TxCTL, MC1 | CNTL1 | CNTL0 | TACLR | TAIE | TASSEL1);
|
||||
write_timer(dev, TxR, 0x00ff);
|
||||
step_smclk(dev, 2);
|
||||
|
||||
// Timer B can configured as 8 bit length.
|
||||
assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TBIV_TBIFG);
|
||||
assert(read_timer(dev, TxR) == 1);
|
||||
}
|
||||
|
||||
static void test_timer_b_length_10()
|
||||
{
|
||||
dev = create_timer("");
|
||||
config_timer(dev, "type", "B");
|
||||
|
||||
/* Continuous 10 bit, ACLK, interrupt enable, clear */
|
||||
write_timer(dev, TxCTL, MC1 | CNTL1 | TACLR | TAIE | TASSEL0);
|
||||
write_timer(dev, TxR, 0x03ff);
|
||||
step_aclk(dev, 3);
|
||||
|
||||
// Timer B can configured as 10 bit length.
|
||||
assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TBIV_TBIFG);
|
||||
assert(read_timer(dev, TxR) == 2);
|
||||
}
|
||||
|
||||
static void test_timer_b_length_12()
|
||||
{
|
||||
dev = create_timer("");
|
||||
config_timer(dev, "type", "B");
|
||||
|
||||
/* Continuous 12 bit, SMCLK, interrupt enable, clear */
|
||||
write_timer(dev, TxCTL, MC1 | CNTL0 | TACLR | TAIE | TASSEL1);
|
||||
write_timer(dev, TxR, 0x0fff);
|
||||
step_smclk(dev, 4);
|
||||
|
||||
// Timer B can configured as 12 bit length.
|
||||
assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TBIV_TBIFG);
|
||||
assert(read_timer(dev, TxR) == 3);
|
||||
}
|
||||
|
||||
static void test_timer_b_length_16()
|
||||
{
|
||||
dev = create_timer("");
|
||||
config_timer(dev, "type", "B");
|
||||
|
||||
/* Continuous 16 bit, SMCLK, interrupt enable, clear */
|
||||
write_timer(dev, TxCTL, MC1 | TACLR | TAIE | TASSEL1);
|
||||
write_timer(dev, TxR, 0xffff);
|
||||
step_smclk(dev, 5);
|
||||
|
||||
// Timer B can configured as 16 bit length.
|
||||
assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TBIV_TBIFG);
|
||||
assert(read_timer(dev, TxR) == 4);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test runner.
|
||||
|
|
@ -748,16 +931,26 @@ int main(int argc, char **argv)
|
|||
RUN_TEST(test_create_with_size_2);
|
||||
RUN_TEST(test_create_with_size_8);
|
||||
RUN_TEST(test_create_with_size_1);
|
||||
RUN_TEST(test_config_type_default);
|
||||
RUN_TEST(test_config_type_A);
|
||||
RUN_TEST(test_config_type_B);
|
||||
RUN_TEST(test_config_type_bad);
|
||||
RUN_TEST(test_config_type_empty);
|
||||
RUN_TEST(test_address_space);
|
||||
RUN_TEST(test_timer_continuous);
|
||||
RUN_TEST(test_timer_stop);
|
||||
RUN_TEST(test_timer_up_stop);
|
||||
RUN_TEST(test_timer_updown_stop);
|
||||
RUN_TEST(test_timer_up);
|
||||
RUN_TEST(test_timer_up_change_period);
|
||||
RUN_TEST(test_timer_updown_change_period);
|
||||
RUN_TEST(test_timer_a_up);
|
||||
RUN_TEST(test_timer_a_up_change_period);
|
||||
RUN_TEST(test_timer_a_updown_change_period);
|
||||
RUN_TEST(test_timer_divider);
|
||||
RUN_TEST(test_timer_capture_by_software);
|
||||
RUN_TEST(test_timer_capture_by_signal);
|
||||
RUN_TEST(test_timer_compare);
|
||||
RUN_TEST(test_timer_a_compare);
|
||||
RUN_TEST(test_timer_b_compare);
|
||||
RUN_TEST(test_timer_b_length_8);
|
||||
RUN_TEST(test_timer_b_length_10);
|
||||
RUN_TEST(test_timer_b_length_12);
|
||||
RUN_TEST(test_timer_b_length_16);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue