f311831c27
Coverity fixes.
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280252, 314742, 314745, 314747, 314755, 314756, 314757, 314758,
314935, 314936
2020-12-20 13:24:47 -05:00
bc484784fc
Make sure zones are triangulated for DRC.
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Normally this happens as a side-effect of rendering them but if done
from a script (or test case) this won't happen.
Fixes https://gitlab.com/kicad/code/kicad/issues/6635
2020-12-12 15:27:46 +00:00
b1f0bf7334
More consistent naming.
2020-12-08 13:05:39 +00:00
09bfb76545
Make sure dissallow constraints get added to rule.
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Also improves some error reporting.
Fixes https://gitlab.com/kicad/code/kicad/issues/6566
2020-12-03 23:08:51 +00:00
3a9a6e22bc
Fix issues in reporting netclasses.
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1) make sure we get the default netclass when we want it
2) escape for HTML (particularly important for "<invalid>", but also
for reporting user rule names, netclass names, etc.)
2020-11-30 14:38:06 +00:00
e09271ca0e
Fixes for hole clearance and hole-to-hole tests.
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1) Separate out CONSTRAINT types
2) Filter both source and dest pads/vias for drilled holes when doing
hole-to-hole checks. We were checking the items being put into the
DRC RTree, but not the items we were scanning.
3) Add hole clearance to Board Setup Constraints panel.
Fixes https://gitlab.com/kicad/code/kicad/issues/6546
Fixes https://gitlab.com/kicad/code/kicad/issues/4683
2020-11-29 23:35:23 +00:00
0d850f98cd
Cleanup.
2020-11-19 22:48:18 +00:00
6e0c58adec
Include local clearances even if no implicit rule was found.
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The real test should be to apply it any time an explicit rule is
*not* found.
Fixes https://gitlab.com/kicad/code/kicad/issues/6426
2020-11-19 22:48:18 +00:00
795e45836d
Fix assert in DRC.
2020-11-17 17:41:57 +00:00
1ce1e493d6
A rule zone is not really a BOARD_CONNECTED_ITEM.
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Or at least it shouldn't always be treated as one.
Fixes https://gitlab.com/kicad/code/kicad/issues/6382
2020-11-15 20:23:15 +00:00
bdbb68f813
MODULE -> FOOTPRINT.
2020-11-13 16:04:03 +00:00
3451ac3088
PCB_MODULE_T -> PCB_FOOTPRINT_T
2020-11-13 15:16:24 +00:00
63a54d003e
More module -> footprint.
2020-11-13 15:16:24 +00:00
52a46341db
More module -> footprint.
2020-11-13 15:16:24 +00:00
f5443de7f9
D_PAD -> PAD.
2020-11-13 15:16:24 +00:00
84dd5108ba
Remove some "class_" prefixes from files.
2020-11-13 15:16:23 +00:00
f7333ad64a
Update some classnames including archaic zone names.
2020-11-12 10:31:25 +00:00
d88eaaf477
Fix various compiler and Coverity warnings
2020-11-11 00:41:02 +00:00
81ea71fb80
More safety when fetching via sizes.
2020-11-07 18:50:30 +00:00
ae9afdd169
SNR. (Mostly for progammers, but a little for user messages.)
2020-11-02 16:20:00 +00:00
115fd1d7f3
Move track-to-zone testing to RTrees.
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Also implemente pad-to-zone testing and removes the control in the
GUI (now that it's fast).
2020-10-31 15:45:41 +00:00
2ee61f52ca
Implement correct layer handling for keepout constraints.
2020-10-25 22:47:47 +00:00
8c93fc76ae
Don't require keepout zones to be named.
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insideArea() now takes A, B, a UUID or a zone name. (Only the UUID
is new.)
2020-10-25 21:08:09 +00:00
386cefbe84
Do footprint keepouts by courtyard.
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Fixes https://gitlab.com/kicad/code/kicad/issues/6162
2020-10-25 18:17:58 +00:00
7674d2ba91
Free allocated DRC structures when re-initializing.
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Fixes https://gitlab.com/kicad/code/kicad/issues/6147
2020-10-24 22:39:53 +01:00
66bcfb3ffc
drc_engine: Fix via type names
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There was a mismatch between the via type names used in the DRC engine
and the via type names defined in the class_track.cpp ENUM_MAP for
VIATYPE.
This fixes the discrepancy; which was breaking microvias altogether as
the route tool also uses the DRC code to determine the correct
diameter/drill (without this patch it was incorrectly using regular
dimensions for microvias.)
2020-10-24 15:46:47 +00:00
41fd8293e8
Don't apply clearance to keepout zones.
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Also improves the clearance and keepout reporting.
Fixes https://gitlab.com/kicad/code/kicad/issues/6118
2020-10-22 21:29:04 +01:00
9ff49277e1
Add implicit rule generation for keepout areas.
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Also implements collision detection for SHAPE_POLY_SET.
Fixes https://gitlab.com/kicad/code/kicad/issues/6105
2020-10-22 10:41:21 +01:00
c5d45f8a78
Move DRC dialog to same DRC rule reporting mechanism as inspectors.
2020-10-17 20:40:05 +01:00
1b2168af1e
Don't throw implicit rules out after failing to compile user rules.
2020-10-16 12:44:20 +01:00
eea7957e16
Inform user of bad DRC rules when filling zones.
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ADDED: facility for hypertext links in infobar.
Also made use of this for via constraint errors when routing.
Fixes https://gitlab.com/kicad/code/kicad/issues/5800
2020-10-16 12:44:20 +01:00
6b7749658e
Report all implicit rules for resolution reports.
2020-10-15 20:53:27 +01:00
8c4197db2a
Netclass track widths and via sizes are opts, not mins.
2020-10-13 00:34:10 +01:00
af90642440
Hook board edge clearance constraints up to zone filling.
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Also hooks them up to the clearance resolution reporter, and makes
some general improvements to reporting.
Fixes https://gitlab.com/kicad/code/kicad/issues/5947
2020-10-12 18:31:00 +01:00
32dffd27ab
Add silk clearance to board setup constraints.
2020-10-12 18:31:00 +01:00
8e70381be3
Don't try and infer optimum widths for board minimums.
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It doesn't work well with sorting the implicit rules by clearance.
Fixes https://gitlab.com/kicad/code/kicad/issues/5951
2020-10-11 17:17:21 +01:00
af28ef9d56
Add silk clearance checking to Resolve Clearances...
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Also fixes a bug in order of RTrees in silk collision checker.
2020-10-11 14:18:11 +01:00
42eecdfd3a
Collapse silk constraints down to one.
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Also updates the rule syntax help and code-completion with a bunch
of diff-pair and other stuff that hadn't been updated yet.
2020-10-11 13:19:23 +01:00
bcebb19665
Add implied diffpair netclass rules.
2020-10-11 13:19:23 +01:00
04c4012ee6
Make track/via sizes UI more predictable and compatible with DRC.
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Two main changes: netclass values need to go through the DRC engine
so they can interact with other rules. They're also now dependent
on the layer being routed as well as the start object.
Also make the controls adjust to each other better. For instance,
copy-track-width needs to turn off when you select a particular
track width, and a particular track width needs to zero out when
you choose copy-track-width.
Fixes https://gitlab.com/kicad/code/kicad/issues/5951
2020-10-10 19:32:30 +01:00
fdeb340d21
Defensive code against missing nets.
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Also adds net re-parenting code to Repair Board.
Fixes https://gitlab.com/kicad/code/kicad/issues/5935
2020-10-10 16:54:19 +01:00
0c7630f8b4
Get rid of wxWidgets assert.
2020-10-09 00:31:29 +01:00
4f2e574f4b
Move IsADiffPair to drc_engine.cpp for now.
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Otherwise we have to include drc_test_provider_diff_pair_coupling.cpp
in CVPCB, which isn't ideal either.
I'll let Tom figure out the best plan going forward, but this should
at least get things compiling/linking again.
2020-10-09 00:05:22 +01:00
6550e01318
Sort synthetic netclass rules by min clearance.
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This way when 'A' and 'B' have different netclasses the largest will
fire (rather than just a random one of the two).
Fixes https://gitlab.com/kicad/code/kicad/issues/5926
2020-10-08 23:41:27 +01:00
5c2c66dd07
drc: sane default rules for via diameters/diff pair widths/diff pair gaps (required by the P&S)
2020-10-09 00:01:26 +02:00
85c6cebd77
Rework silk-to-pad checker to handle all solder mask clipping of silk.
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Fixes https://gitlab.com/kicad/code/kicad/issues/5851
2020-10-04 13:21:01 +01:00
400c15b8eb
Add mils to units, remove useMils variables
2020-10-03 20:06:56 +00:00
0b23cb7dbb
more cleanup about removing useless include
2020-10-03 15:26:03 +02:00
bd0bd5b84b
drc: support for skew & via_count constraints. Length test now generates a length report
2020-09-27 16:45:46 +02:00
b215361b30
drc: default constraints for silk2pad, silk2silk
2020-09-27 16:45:46 +02:00
Wayne Stambaugh
Jeff Young
Ian McInerney
David Shah
Tomasz Wlostowski
Mikolaj Wielgus
jean-pierre charras