Commit Graph

40 Commits

Author SHA1 Message Date
jean-pierre charras 19fef1e9ba Fixes: lp:1664349 (DRC complaining about not connected pads even if they are not on a copper layer)
(happens when creating pads with complex shapes)
https://bugs.launchpad.net/kicad/+bug/1664349
2017-02-14 14:40:34 +01:00
Dick Hollenbeck e24990146d Pcbnew: major swig fix.
* Switched hashtables.h over to std::undordered_map from boost version.

* Added new macros DECL_VEC_FOR_SWIG() and DECL_MAP_FOR_SWIG() in macros.h.
  These along with future DECL_HASH_FOR_SWIG() unify the declaration to swig
  and C++ so that the resultant type name is common in both languages, and
  the types AGREE.

* Fixed swigging of NETINFO_ITEM and NETINFO_LIST via magic.

* Newly exposed (python wrapped) are: D_PADS, TRACKS (was TRACK_PTRS),
  NETNAME_MAP, NETCODE_MAP, wxString (without constructor purposely, read
  comment in wx.i), MARKERS, ZONE_CONTAINERS, NETCLASSPTR, KICAD_T types.

* std::vector<SOMETHING*> tends to end up named SOMETHINGS in C++ and python.
  Having the name consistent between like types is helpful, and between
  languages.  std::map<> ends up as SOMETHING_MAP.

* NETINFO_LIST::m_netNames and NETINFO_LIST::m_netCodes are now std::map
  instead of hashtables, because swig does not yet support std::unordered_map.

* You can now get to any netclass or net info.   NETNAMES_MAP and NETCODES_MAP
  are traversable basically the same as a python dictionary using a python
  string (not wsString) as the key!  The wxString typemap converts python
  string to wxString before the lookup happens.  Iteration also works.
2016-07-18 13:23:09 -04:00
Tomasz Wlostowski ee3418e90b One-click PCB update improvements
- Fix repetitive undo/redo segfaults & assertions.
- Add Update menu entry on PCB side.
- Fix Python build error
- Add spread footprints after updating
2016-01-29 15:43:40 +01:00
Tomasz Wlostowski 5ef6001e06 pcbnew: support for removing NETINFO_ITEMS from BOARD for proper netlist undo 2016-01-29 11:29:56 +01:00
Dick Hollenbeck b27176f230 Pcbnew: fix segfault after deleting a pad from a footprint then performing a DRC action such as a via drag. 2015-09-23 19:02:40 -04:00
jean-pierre charras 39497b109e Pcbnew: fix Bug #1422093 (pcbnew crashes after editing a footprint cominng from the board with the fp editor and saving it on a librray and trying to load it to the board)
Some other very minor fixes.
2015-02-17 17:32:47 +01:00
Maciej Suminski fa846932c1 bugfix 1325375: pcbnew crash while append a board 2014-06-02 11:41:54 +02:00
jean-pierre charras 9c1f6b7307 Pcbnew: fix Bug #1304418 . Fix also a related issue which crashes Pcbnew in some corner cases.
(for instance, when a footprint from the currently edited board is loaded in the footprint editor, and when the board is cleared or reloaded)
In footprint editor, the net names are no more shown od modifiable (becuase the footprint editor does not know anything about net names.
This change should allow the changes planned in pcbnew.
2014-04-24 20:54:49 +02:00
Maciej Suminski 75026d8754 Renamed BOARD_CONNECTED_ITEM::GetNet() -> GetNetCode()
Renamed BOARD_CONNECTED_ITEM::SetNet() -> SetNetCode()
Added BOARD_CONNECTED_ITEM::GetNet() for accessing NETINFO_ITEM* of a given item.
Fixed module editor crash when launched to edit a module from a PCB.
Replaced some BOARD::FindNet( item->GetNet() ) calls with BOARD_CONNECTED_ITEM::GetNet().
2014-02-25 11:40:34 +01:00
Maciej Suminski ec763dfede NETINFO_ITEM for orphaned items now have empty netname and net code = 0 (to avoid problems).
Fixed case for the footprint legacy plugin when added module's do not have set parent (BOARD).
Added copyright notice for pcbnew/class_netinfolist.cpp (feel free to correct, it is just copied from corresponding header file).
2014-02-12 18:01:03 +01:00
Maciej Suminski 15b8d3d20a Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).

Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.

- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).

- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.

- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok

Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 10:19:51 +01:00
Maciej Suminski 441e03172c Added iterators for NETINFO_LIST (as net codes for existing net codes may be not consecutive). 2014-01-16 16:47:31 +01:00
Maciej Suminski af7520ccb9 wxWidgets 2.8 fix 2014-01-16 14:36:09 +01:00
Maciej Suminski 8a4e723504 NETINFO_ITEMs are not stored in a vector anymore, instead they are held in a unordered_map. Now, the net codes may be not consecutive. There is another way for assigning net codes (using a static int that holds a possible empty net code and a function that makes sure it is not used [getFreeNetCode()]).
Removed some unused fields (NETINFO_ITEM::m_NbNodes, m_NbLink, m_NbNoconn, m_Flag).
2014-01-16 14:20:51 +01:00
Maciej Suminski d62b47a0df BOARD_CONNECTED_ITEMs do not store net code anymore (m_NetCode field), instead net info is stored using a pointer to NETINFO_ITEM.
GetNet() refers to the net code stored in the NETINFO_ITEM. SetNet() finds an appropriate NETINFO_ITEM and uses it.
Removing GetNet() & SetNet() (and the whole net code idea) requires too many changes in the code (~250 references to the mentioned functions).
BOARD_CONNECTED_ITEMs by default get a pointer to NETINFO_ITEM that stores unconnected items. This requires for all BOARD_CONNECTED_ITEMs to have a parent (so BOARD* is accessible). The only orphaned item is BOARD_DESIGN_SETTINGS::m_Pad_Master, but it does not cause any issues so far.
Items that do not have access to a BOARD (do not have set parents) and therefore cannot get net assigned, by default get const static NETINFO_LIST::ORPHANED.

Performed tests:
- loaded .kicad_pcb, KiCad legacy board, Eagle 6.0 board, P-CAD board - all ok
- load a simple project, reload netlist after changing connections in eeschema - ok
- save & reload a board - ok, but still contain empty nets
- remove everything, restore with undo - ok
- remove everything, reload netlist - ok
- changing net names (all possibilites: empty->existing, empty->not existing, existing->empty, existing->not existing) - all ok
- zones: when net is changed to a net that does not have any nodes besides the zone itself, it does not get filled
2014-01-15 18:03:06 +01:00
Maciej Suminski 3017b61711 Added NETINFO_LIST::UNCONNECTED constant. 2014-01-15 09:34:16 +01:00
Maciej Suminski bf80cc770e Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map.
Net codes are updated upon net list update. (BOARD::ReplaceNetlist())
Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes.
On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net).
Removed COMPONENT_NET::m_netNumber, as it was not used anywhere.
Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique.

It seems that at this point:
- Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well.
- Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList())

Performed tests:
- Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps.
- Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above.
- Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit.
- Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied.
- Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 18:04:07 +01:00
Maciej Suminski 487b609e76 Removed NETINFO_ITEM::SetNet() and NETINFO_ITEM::SetNetname() methods.
NETINFO_ITEM::m_Net and NETINFO_ITEM::m_Netname are const.

Changes to be verified:
- pcbnew/minimun_spanning_tree.cpp: It segfaults is m_Size == 0
- pcbnew/exporters/export_gencad.cpp: I removed the SetNetname() call, as it changes only the unconnected net and in the next line it returns if the net is unconnected. Still, I wonder if name for the unconnected net matters. What about tests that check if a net name is empty to decide if it is unconnected net or not.
2014-01-09 15:51:47 +01:00
jean-pierre charras 8cca89ffbe Pcbnew: read netlist enhancements: add option to remove single pads nets, add enforce tests to report non existing netnames in zones.
Fix also some very minor errors in comments.
2013-08-24 10:08:55 +02:00
Lorenzo Marcantonio 78e41187b3 Moved utilities for angles in trigo.h
New conversion routines and sin/cos implementation for angles in decidegrees
2013-05-02 20:06:58 +02:00
Wayne Stambaugh 7d0ec1a138 More encapsulation work.
* Complete encapsulation of the MODULE class.
* Complete encapsulation of the EDA_TEXT class.
* Encapsulate most of the ZONE_CONTAINER class.
* Add pcbcommon library as a dependency for reSWIGging the scripting
  support.  This should cover most dependency cases.
2013-03-18 15:36:07 -04:00
Dick Hollenbeck 76e21c28a4 EAGLE_PLUGIN now establishes (trace_min), (via_min_size), (via_min_drill), and Default Net's (clearance)
by groking the eagle *.brd info.  This makes it more probable that fewer DRC errors come about on first 
DRC attempt.
2013-03-14 17:54:47 -05:00
Wayne Stambaugh 8a5ea7ec0d Pcbnew BOARD object encapsulation improvements. 2013-01-09 13:52:44 -05:00
Dick Hollenbeck 5cda6bc1a6 eagle plugin first work 2012-05-20 08:14:46 -05:00
Dick Hollenbeck b8a0ab4c52 switch to <> for includes from "" per conversation with Jean-Pierre and Wayne, adjust search paths 2012-01-22 22:33:36 -06:00
jean-pierre charras 2c150e4817 All: fix compatibility issues with wxWidgets 2.9.3
Minor cosmetic enhancements.
Pcbnew: more workd abput connection algorithms (work in progress)
2011-12-17 22:21:03 +01:00
Dick Hollenbeck 4c2a1dd5d1 more kicad_plugin work, make BOARD::m_NetInfo private 2011-12-09 23:33:24 -06:00
Wayne Stambaugh edd35b4e90 PCB common library header rationalization.
* All header files used to create the PCB common library now compile as
  stand alone code.  This prevents the need to define them in a specific
  order to make source code compile properly.  It should also now be
  possible to relocate the source code to build the common PCB library
  to a separate folder.
2011-09-23 09:57:12 -04:00
jean-pierre charras cdd9e8cabe Pcbnew: code cleanup 2010-11-26 18:47:35 +01:00
Dick Hollenbeck 636b2d301e function comments, fix ones in *.cpp files until they can be deleted if they exist in the headers 2010-11-12 10:36:43 -06:00
charras ae12e69860 fixed a minor problem in pcbnew compiled in DEBUG mode, that prints a lot of error messages when loading a board 2009-10-13 16:29:02 +00:00
charras 7776dd61eb use kbool 2.1 in zones calculations. see CHANGELOG for others changes and more info 2009-09-17 17:48:40 +00:00
dickelbeck 85dc98a58a more netclass work 2009-08-17 02:59:38 +00:00
charras e7c9ae2b45 First work about net classes. This is a work in progress and a moving target 2009-07-18 11:44:19 +00:00
charras 96e0bebd0e code cleaning 2009-06-20 19:09:43 +00:00
charras f43d1aaa54 Added text justification for graphic texts in libedit and more(see changelog) 2009-06-11 14:26:17 +00:00
charras edb48d461b Fixed minor bugs. Code cleaning 2009-06-06 18:08:49 +00:00
charras 483359b39a fixed a problem when loading a module from lib having some pads with an old netname 2009-06-05 15:57:41 +00:00
charras b1d1a71101 Finished code cleaning about ratsnets calculations and handling.
Minor others changes.
2009-05-28 08:42:24 +00:00
charras e073bdc042 Pcbnew: cleaned code in ratsnet calculations (work in progress). The new code is also faster. 2009-05-24 18:28:36 +00:00