Rename GetPolyPoint() to BuildPolyPointsList(), because GetPolyPoint() looks like an accessor, but it is not an accessor.
(Using it as accessor can creates a *very long calculation time* for very basic access to polygon vertices)
Fixes: lp:1745050
https://bugs.launchpad.net/kicad/+bug/1745050
- Reverts behaviour of 3e71ed2421
- 3D model offset now explicitly written in mm, using "offset" tag
- Any read "at" tag is converted from inches to mm
- This will not break any 3D model offset when reading files
- It will however render files incompatible with old versions
This commit was too broad and not cognizant of the purpose of the class
UTF8.
Add MAYBE_VERIFY_UTF8() macro, which can trap non-UTF8 encoded strings in
debug builds.
Use that macro conditionally in class UTF8 to trap non-UTF8 encoded strings
being put into UTF8 instances.
Removes the need of using the legacy code in polygon/PolyLine.{h,cpp},
refactoring all CPolyLine instances with SHAPE_POLY_SET instances.
The remaining legacy methods have been ported to SHAPE_POLY_SET;
mainly: Chamfer, Fillet, {,Un}Hatch.
The iteration over the polygon vertices have been simplified using the
family of ITERATOR classes.
Make all EDA_TEXT data private and rename accessors to avoid function
name collisions in derived classes.
Overload EDA_TEXT's SetTextAngle() and SetEffects() in TEXTE_PCB.
Add support for preserving Reference text position, size, orientation
during a netlist import into a BOARD, as well as the one off footprint
update dialog.
Rename FPID to LIB_ID as is now used as a generic library identifier and
is no longer specific to footprints.
Remove all mention of footprint from the new LIB_ID doxygen comments and
code.
Rename files fpid.h and fpid.cpp to lib_id.h and lib_id.cpp.
Rename fp_lib_table.keywords file to lib_table.keywords and adjust CMake
build dependencies accordingly.
Update all source files effected by the code and file name changes.
Update .gitignore for file name changes.
When opening a board file and storing it again, the pads in all
embedded modules get reversed. This is generally not really nice
if the PCB is managed by version control as it creates churn and
could make merges hard.
*) Extend SWIG support deeper into the BOARD class.
*) Move swig *.i files into a directory identified for SWIG, in preparation
for a parallel universe involving Phoenix's SIP.
*) Move swig files which will be common to both eeschema and pcbnew into
common/swig.
*) Sketch out a "common" python module, and plan on dovetailing that into a
libkicad_shared.{dll,so}
*) Add common/swig/ki_exceptions.i and define a macro HANDLE_EXCEPTIONS()
which is to be applied to any function which needs C++ to python
exception translation.
*) Move the test for SWIG tool into top level CMakeLists.txt file for use
in all python modules beyond pcbnew, i.e. eeschema and common.
*) Add SWIG_MODULE_pcbnew_EXTRA_DEPS which generates a better Makefile, one
which rebuilds the swig generated *.cxx file when one of its dependencies
change.
*) Re-architect the board.i file so that it can be split into multiple *.i
files easily.
*) Make some KIWAY from python progress, in preparation for Modular KiCad
phase III.
* Split and rewrite the preview window and canvas.
* Create a new class for handling the board information.
* Adds new render targets: openGL, legacy, and ray tracing.
* Render targets take full advantage of the new 3D plugins system and 3D cache
for a fast 3D model loading.
* Faster board loading.
* New OpenGL render is faster than the old one.
* New ray tracing render target with a post processing shader.
* Use of new 3D plugins (WRL, X3D, STEP and IGES) and 3D model caching.
* Preview of 3D model while browsing the file name.
* 3D preview of the footprint while adding / align 3D shapes.
* Render of 3D models according to attributes: Normal, Normal+Insert, Virtual.
* Pivot rotation centered in one point over the PCB board.
* Shortcuts keys improved for XYZ orientation..
* Animated camera.
Currently, kicad_pcb files have a (version ...) tag, but it is ignored. This
commit does the following:
1. Parse the version. If it's later than the last supported version, present an
alternative error message suggesting an upgrade if the file does not load
correctly. The version will be interpreted as an integer YYYYMMDD to suggest
a KiCad release date.
2. Accept a (version ...) tag also in kicad_mod files, but do not write them
yet. If no version tag is present in these files, assume the version to be that
of the current format version at the time of this commit.
This is meant to be merged to the 4.x stable series, and preps for KiCad 5
which will start emitting version tags also in footprints - users with what
will then be 'old stable' will not get a parse error when we introduce this for
footprints, and we can safely increment the format version later.
* Fix a StrPrintf() %s count mismatch bug
* Better comments
* Use std::string::data() instead of a ref to the first char to get the str::string buffer (should not change anything with GNU lib)
PAD_SHAPE_T and PAD_ATTR_T still have a double definition (new names and old names) to be sure python scripts are nor broken by the change.
PAD_DRILL_SHAPE_T does not have a double definition, because it is unlikely oblong holes are used in python scripts.
Double definitions will be removed in the (next) future.
* Cleanup namespace in enum ZoneConnection in pcbnew/zones.h to self-explained names unification: PAD_ZONE_CONN_INHERITED, PAD_ZONE_CONN_NONE,PAD_ZONE_CONN_THERMAL,PAD_ZONE_CONN_FULL, PAD_ZONE_CONN_THT_THERMAL
these options are used in GAL mode, but the usercannot control this visibility. So if the board file does not have these visibility flags set, the GAL never show them.
Fix also a compil warning.
legacy plugin: better compatibility with old brd files (current track width and current vias size, stored in SETUP section, were not read from file and incorrectly set)
* Delete Single Pad Net option does not delete the net if a zone use this net (i.e. is attached to this pad).
* pcb_parser accept now negative netcodes in zones (can happen with old files, which previously could crash Pcbnew)
* pcb_parser accept now files with incorrect or missing net count (can happen with old files, which previously could crash Pcbnew)
* if a zone has a non-existent net name it now keep this net name, and DRC detect it (previously, the net name was lost, and the DRC did not tected this issue).
* Drc test: now detect a "dead" net, i.e. a net with 0 pads, but still used by a zone. It happens easily after a schematic modification, when a net disappears or is renamed.
Looked like a minor issue, but was due to a more serious bug, when using 2 different DSN_LEXERS which were not synchronized.
The fix is not perfect, but unfortunately, the parser used to read the PCB_PLOT_PARAMS in .kicad_pcb files is also used in legacy board file reader.
Therefore it is better than write 2 parser functions, one for legacy files, the other for the .kicad_pcb files, which make the same thing.
*) When kicad.exe closes a project, close any open KIFACEs so that they cannot
get disassociated from their true PROJECT.
*) Allow loading eeschema library editor from kicad.exe
*) Allow loading pcbnew library editor from kicad.exe
*) Rename LIB_COMPONENT to LIB_PART.
*) Add class PART_LIBS, and PART_LIB.
*) Make PART_LIBS non-global, i.e. PROJECT specific.
*) Implement "data on demand" for PART_LIBS
*) Implement "data on demand" for schematic SEARCH_STACK.
*) Use RSTRINGs to retain eeschema editor's notion of last library and part being edited.
*) Get rid of library search on every SCH_COMPONENT::Draw() call, instead use
a weak pointer.
*) Remove all chdir() calls so projects don't need to be CWD.
*) Romove APPEND support from OpenProjectFiles().
*) Make OpenProjectFiles() robust, even for creating new projects.
*) Load EESCHEMA colors in the KIWAY::OnKiwayStart() rather in window open,
and save them in the .eeschema config file, not in the project file.
*) Fix bug with wxDir() while accessing protected dirs in kicad.exe
*) Consolidate template copying into PROJECT class, not in kicad.exe source.
*) Generally untangle eeschema, making its libraries not global but rather
held in the PROJECT.
2) Fix passing wxString to common/config_params so lookup keys
can be dynamically generated. This gives ~/.kicad files all the colors.
3) Fix LEGACY_PLUGIN so it loads all layer types and masks properly.
4) Extend the table in router/pns_index.h to 128 from 64.
2) Change from legacy Cu stack to counting down from top=(F_Cu or 0).
The old Cu stack required knowing the count of Cu layers to make
sense of the layer number when converting to many exported file types.
The new Cu stack is more commonly used, although ours still gives
B_Cu a fixed number.
3) Introduce class LSET and enum LAYER_ID.
4) Change *.kicad_pcb file format version to 4 from 3.
5) Change fixed names Inner1_Cu-Inner14_Cu to In1_Cu-In30_Cu and their
meanings are typically flipped.
6) Moved the #define LAYER_N_* stuff into legacy_plugin.cpp where they
can die a quiet death, and switch to enum LAYER_ID symbols throughout.
7) Removed the LEGACY_PLUGIN::Save() and FootprintSave() functions.
You will need to convert to the format immediately, *.kicad_pcb and
*.kicad_mod (=pretty) since legacy format was never going to know
about 32 Cu layers and additional technical layers and the reversed Cu
stack.
Removed SetCurrentClassName() (it was not used anywhere and less safe than SetCurrentClass()).
Added BOARD_DESIGN_SETTIGNS::GetDefault() to make some pieces of shorter and clearer.
Most of the changes are just adding GetDesignSettings() before every occurence of m_NetClasses.
More complex changes:
class_netclass.cpp - NETCLASS does not store the pointer to the parent BOARD anymore. Added function SetParams( BOARD_DESIGN_SETTINGS& ).
class_netclass.h - Removed GetTrackMinWidth(), GetViaMinDiameter(), GetViaMinDrill(), GetuViaMinDiameter(), GetuViaMinDrill() as they were refering to BOARD_DESIGN_SETTINGS anyway (they are not net class specific).
kicad_plugin.cpp - filters out empty nets (that are anyway not saved) when storing net class information. Previously it was done in NETCLASS::Format() function.
- SEGVIA becomes VIA
- Drill size moved from TRACK to VIA
- Removed shape from TRACK, becomes ViaType in VIA
- GetTrace becomes GetTrack, for uniformity
- Some minor constification and typo fixes
Renamed BOARD_CONNECTED_ITEM::SetNet() -> SetNetCode()
Added BOARD_CONNECTED_ITEM::GetNet() for accessing NETINFO_ITEM* of a given item.
Fixed module editor crash when launched to edit a module from a PCB.
Replaced some BOARD::FindNet( item->GetNet() ) calls with BOARD_CONNECTED_ITEM::GetNet().
Renamed BOARD_CONNECTED_ITEM::SetNet() -> SetNetCode()
Added BOARD_CONNECTED_ITEM::GetNet() for accessing NETINFO_ITEM* of a given item.
Fixed module editor crash when launched to edit a module from a PCB.
Replaced some BOARD::FindNet( item->GetNet() ) calls with BOARD_CONNECTED_ITEM::GetNet().
Added DIMENSION::SetOrigin(), DIMENSION::SetEnd(), DIMENSION::GetOrigin(), DIMENSION::GetEnd(), DIMENSION::GetHeight().
Fixed flipping for DIMENSION class.
Added an information that helps to understand roles of the points in the DIMENSION class.
Some minor changes to PCB_PAINTER (mainly using const COLOR4D& for taking the result of GetColor() function).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
GetNet() refers to the net code stored in the NETINFO_ITEM. SetNet() finds an appropriate NETINFO_ITEM and uses it.
Removing GetNet() & SetNet() (and the whole net code idea) requires too many changes in the code (~250 references to the mentioned functions).
BOARD_CONNECTED_ITEMs by default get a pointer to NETINFO_ITEM that stores unconnected items. This requires for all BOARD_CONNECTED_ITEMs to have a parent (so BOARD* is accessible). The only orphaned item is BOARD_DESIGN_SETTINGS::m_Pad_Master, but it does not cause any issues so far.
Items that do not have access to a BOARD (do not have set parents) and therefore cannot get net assigned, by default get const static NETINFO_LIST::ORPHANED.
Performed tests:
- loaded .kicad_pcb, KiCad legacy board, Eagle 6.0 board, P-CAD board - all ok
- load a simple project, reload netlist after changing connections in eeschema - ok
- save & reload a board - ok, but still contain empty nets
- remove everything, restore with undo - ok
- remove everything, reload netlist - ok
- changing net names (all possibilites: empty->existing, empty->not existing, existing->empty, existing->not existing) - all ok
- zones: when net is changed to a net that does not have any nodes besides the zone itself, it does not get filled
- ZONE_CONTAINER::m_Netname field
- ZONE_CONTAINER::SetNetName()
- ZONE_CONTAINER::SetNet() [it uses the one in BOARD_CONNECTED_ITEM]
- ZONE_CONTAINER::GetNetName() [instead BOARD_CONNECTED_ITEM::GetNetname is used]
- ZONE_CONTAINER::SetNetNameFromNetCode()
Performed tests:
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
D_PAD::GetNetname() and D_PAD::GetShortNetname() were moved to BOARD_CONNECTED_ITEM. Now they use the net name stored in NETINFO_ITEM.
Moved some one-line functions from class_board_connected_item.cpp to class_board_connected_item.h.
Added a copyright notice, moved Doxygen comments from class_board_connected_item.cpp to class_board_connected_item.h.
I have some doubts if changes introduced pcbnew/dialogs/dialog_pad_properties.cpp do not break anything, but I could not find a test case that breaks the pcbnew.
Performed tests:
- changed pad's net name from empty to existent - ok, name was changed
- changed pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty
- changed pad's net name from existent to empty - ok, net name became empty
- changed pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed
- (re)reading netlists, including net changes - fine, changes are applied, but empty nets are still kept
- loaded pcbnew/pcad2kicadpcb_plugin/examples/CK1202_V1.pcb to test P-CAD import plugin - ok, net names are correct
- imported an Eagle 6.0 board (Arduino Uno; http://arduino.cc/en/uploads/Main/arduino_Uno_Rev3-02-TH.zip) then saved in .kicad_pcb format and reloaded - ok, net names are correct
- saved demos/video/video.kicad_pcb in legacy format and then loaded it again - ok, net names are correct
jean-pierre charras
Oliver Walters
Simon Richter
Tomasz Włostowski
Chris Pavlina
Oliver Walters
Maciej Suminski
Dick Hollenbeck
Kristoffer Ödmark
Jon Evans
Alejandro García Montoro
Wayne Stambaugh
Henner Zeller
Cirilo Bernardo
Mrio Luzeiro
Wayne Stambaugh
unknown
Lorenzo Marcantonio