ix the problem with the original template-based implementation to limit
the amount of things that could be forgotten by new panel creators
(since we can't just have a static fail method warning about things
beinf forgotten).
This reverts commit a92516bcd2.
This avoids conflict with existing kicad installations. Older version
files are preferentially opened by older KiCad installations while new
KiCad files get opened by version 6
The rebuildLayerStackPanel() reads from the current board to setup the
panel. We maintain the board swap until after the setup is completed
Fixes https://gitlab.com/kicad/code/kicad/issues/9370
We were already checking for zone-zone overlap but missing checks when
running against (possibly) buried vias as well as the general check
Fixes https://gitlab.com/kicad/code/kicad/issues/9366
The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
Changes a dot to be a square pixel (linewidth x linewidth). This allows
the removal of IU dependencies and ensures that a dot is always visible
on screen. Also makes sure that cairo is setting the current linewidth
during its stroke routines
Fixes https://gitlab.com/kicad/code/kicad/issues/9362
Labels are the true structure. Extracting purely just shapes won't get you instances of shapes that are virtually placed by reference labels.
Note, this may break the 3d placement of existing user models but they were most likely wrong loaded in the first place and losing any location data as simple as a boring offset from 0. There's no way to preserve the broken behavior and still allow complex step assemblies to locate correctly.
Fixes https://gitlab.com/kicad/code/kicad/issues/4181
Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).
This removes a large amount of DRC violations on imported designs.
Rather than detaching and re-attaching the layer panels with the
attendant overhead, we keep each panel intact and only update its
contents. Since the bindings are the same, this saves substantial time
on pcb loading as well as when closing the board setup dialog
Use KiCad default stackup for older CADSTAR boards that do not
define any dielectric layers between the electrical layers.
Also fix default stackup calculation to ensure finished board thickness
is 1.6mm
This was happening in two cases:
- Loading documentation symbols (CADSTAR on purpose defines these in an
invalid layer)
- When an item was in a "layer set" such as ALLELEC or ALLLAYER - need to
make sure we remove the copper layers that are not active in the design
On wxWidgets 3.0, SetSizeHints must be called once the panel is fully populated.
On wxWidgets 3.1.5, SetSizeHints is not mandatory but can be called to ensure
right sizes once the panel is fully populated.
Cases where fp was left open could lead to dangling files until KiCad is
closed. Stack-based file stream automatically closes after parsing and
on exception
Fixes https://gitlab.com/kicad/code/kicad/issues/9336
Cadstar areas have a line width but this is only for display purposes.
Instead CADSTAR uses the center line when determining whether a DRC
violation occurred.
The form builder window only contained the notebook control, so it was
basically pointless. This removes the base frame and instead makes
PCB_CALCULATOR_FRAME inherit directly from KIWAY_PLAYER.
Seth Hillbrand
Ian McInerney
Mikolaj Wielgus
Marek Roszko
Roberto Fernandez Bautista
jean-pierre charras