KiCad breaks a bit when dealing with 360° arcs, so convert them to
circles on import. The break happens when converting to polygons for
viewing, the arc is passed from start->mid->end format to
center->start->angle format. At 360°, the angle is normalized to 0
The previously used line number threshold was causing (on some systems) severe slowdown in loading
due to relatively long redraw time of the progress bar window.
Symbol library IDs included the library nickname which is incorrect
and meaningless since it will be overwritten by the symbol library
table code. This is not a file format change as there are no behavioral
differences.
If the THROUGH_HOLE attribute isn't set, it just means that the pads
are only present on one side of the board, but there can still be a
plated / non-plated hole.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/9579
When importing, we should not use Eco1 for other purposes as the
importer uses it to place unknown layer objects. We also need to avoid
placing objects on the courtyard layers that do not relate to the layer
purpose in DRC
Fixes https://gitlab.com/kicad/code/kicad/issues/9442
We no longer have any knowledge of the original start/end of the arc,
since SetArcAngleAndEnd swaps the start and end to ensure the arc is
always clockwise at the end.
Adds a method EDA_SHAPE::EndsSwapped() to notify whether the start/end
point of the shape were swapped.
The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).
This removes a large amount of DRC violations on imported designs.
Use KiCad default stackup for older CADSTAR boards that do not
define any dielectric layers between the electrical layers.
Also fix default stackup calculation to ensure finished board thickness
is 1.6mm
This was happening in two cases:
- Loading documentation symbols (CADSTAR on purpose defines these in an
invalid layer)
- When an item was in a "layer set" such as ALLELEC or ALLLAYER - need to
make sure we remove the copper layers that are not active in the design
Cadstar areas have a line width but this is only for display purposes.
Instead CADSTAR uses the center line when determining whether a DRC
violation occurred.
Steffen Mauch
Wayne Stambaugh
Thomas Pointhuber
Seth Hillbrand
Jeff Young
Roberto Fernandez Bautista
Tomasz Wlostowski
david-beinder
Jon Evans