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1407 Commits

Author SHA1 Message Date
Uwe Bonnes acec489647 adiv5_jtagdp: Always set idcode. 2020-11-29 21:11:11 +01:00
Uwe Bonnes 9e1b7fdac0 jlink/swd_low_access: Fix data direction during response read phase. 2020-11-29 15:48:50 +01:00
Uwe Bonnes 8903026c14 jlink/swd: swd frequency is fixed, not need to set. 2020-11-29 15:48:50 +01:00
Uwe Bonnes f45c56af83 adiv5/swdp: Check early for valid DP idcode. 2020-11-29 15:48:50 +01:00
Uwe Bonnes 3b6432912d jlink: Catch another error with no target connected. 2020-11-29 15:48:50 +01:00
Uwe Bonnes 7df314e265 Firmware/Jlink: Fix double free when debug power-up fails (#780) 2020-11-29 15:48:50 +01:00
Uwe Bonnes e1329499de platform_adiv5_swdp_scan: Do not double free with early errors. 
adiv5_dp_init() clean up itself if errors happen
 2020-11-29 15:48:50 +01:00
Stefan Agner 77025d4b6b Make dfu-convert.py Python 3 capable 2020-11-29 15:45:08 +01:00
Uwe Bonnes bf548e92c0 swd: After write low_access, always append 8 clk to move data through SW-DP. 
Especially needed when leaving the debugger or during debug unit power-up.

ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
tells to clock the data through SW-DP to either :
- immediate start a new transaction
- continue to drive idle cycles
- or clock at least 8 idle cycles

Implement last option to favour correctness over slight speed decrease

Implement only for adapters where we assemble the seq_out_parity in our code,
as on firmware, ftdi and jlink. Hopefully the high level adapters do it right.

Reverts 2c33cde63f and
cde7726b87
 2020-11-27 22:26:48 +01:00
Uwe Bonnes 139e5d7e22 f4discovery: Compile time option to compile with ST bootloader 
Just to keep things active. Prepare for F72 bootloader.
 2020-11-27 22:26:48 +01:00
Uwe Bonnes 636bcee355 stlink/swlink: Remove the DFU upgrade utility. 
Hopefully no old bootloaders are around. If otherwise, revert to last
commit before this and update the DFU bootloader.
 2020-11-27 22:26:48 +01:00
Uwe Bonnes 03a7b06eb8 Makefile: Remove no longer needed code pathes. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 27ef4569ca stm32/dfucore.c: Use libopencm3 provided defines and functions. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 9d55128ab8 cl_utils: Get voltage only once. 2020-11-27 22:26:48 +01:00
Uwe Bonnes e6823f39de Hosted: Print version with "-h" and "-t" option. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 3ee31473c6 cortexm.c: LPC15xx has designer 43b and Partno 4c3 
Thanks to JojoS!
 2020-11-27 22:26:48 +01:00
Uwe Bonnes 62d9f60f03 hosted/firmware: Waits for read response as long as cortexm_wait_timeout. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 26a23dd1cb stlinkv2: Try harder to open an AP. 
Problem seen on STM32L0 with probably long sleep periods.
 2020-11-27 22:26:48 +01:00
Uwe Bonnes 19e1fddba2 adiv5: Remove unnescessary read. 2020-11-27 22:26:48 +01:00
Uwe Bonnes cda83d3084 Fix memleaks. 
Happened e.g. when Stlink could not enter debug or when cortexm_prepare timed out.
 2020-11-27 22:26:48 +01:00
Uwe Bonnes 9ac5adfcef adiv5: Additional decoding. 2020-11-27 22:26:48 +01:00
Uwe Bonnes d78d7838d3 stm32f1: Always read DBGMCU_IDCODE for t->idcode (#770) 
At least STM32F042 has 0x440 as romtable partno vs 0x445 as DBGMCU_IDCODE.
Thanks to Andrey Melnikov(aam335) for pointing out!
 2020-11-27 22:26:48 +01:00
Uwe Bonnes 653d486ee2 cortexm: Store CPUID in target structure. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 824a1d8abc hosted/find_debuggers: Do not check hubs. Print class of devices unable to open. 2020-11-27 22:26:48 +01:00
Uwe Bonnes e68dd25813 cl_utils: Clarify -d option is BMP/firmware only and deprecate -d. 2020-11-27 22:26:48 +01:00
Uwe Bonnes f71e18948a GPIO for SWD: Slow down edges on more platforms. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 80154c5c7a adiv5_swdp: Fix more memory leak. 2020-11-27 22:26:48 +01:00
Noah Pendleton 35bcb4f7c6 Switch on the lpc546xx target 
Enable the lpc546xx target. Tested on the LPCXpresso54628 dev board,
able to flash and debug.
 2020-11-24 21:32:39 +01:00
Sean Cross e9c02296f2 target: kinetis: add S32K118 
This adds support for the NXP S32K118. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-11-14 13:06:23 +01:00
jbuonagurio f18be6ef7a Add support for Kinetis K12 and placeholders for other K-series MCUs 2020-11-07 12:44:05 +01:00
Uwe Bonnes 2c33cde63f cortexm.c/cortexm_halt_resume: Add some clock cycles to always get CPU going (#768) 2020-11-01 21:53:23 +01:00
Uwe Bonnes d75f3124b9 ftdi_bmp.c: Reapply fix from #715: Check for libftdi 1.5 2020-11-01 12:09:27 +01:00
Stoyan Shopov 99142d1c0e Add documentation details for building PC-hosted BMP in msys2. 2020-11-01 11:33:54 +01:00
Uwe Bonnes 1f7a716710 adiv5.c: Run cortexm_prepare on all suspected CortexM instances. 
Gets all debug units of the second CPU of a STM32H745 visible.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes 18673d9a56 adiv5: Rework DP/AP refcounting. 
ASAN non longer reports leaks with the STM32H745.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes f76a7c4e92 adiv5: Release devices after scan. 
Before, scanning only kept device stopped until POR or attach/detach cycle.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes 73e6b540b2 command: When debug channel is available, print morse messages readable. 2020-10-23 09:40:15 +02:00
Uwe Bonnes 776861c6a0 Makefile: Fix version.h generation for make all_platforms 
Same fix as 0ae65cc10f.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes 80ddafc2f8 Jtag/High Level : Transfer dp->dp_jd_index with every HL command. 
- Add REMOTE_HL_VERSION, now at 1. Fall back to hosted/low-level
  when wrong version is found and give hint to user.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes 59dc1b7eb4 cortex-m7: Give hint about buggy core revision. 2020-10-23 09:40:15 +02:00
Uwe Bonnes 976c763747 jtag remote: Start fixing handling M0 (second jtag) for LPC4322 in high-level 
- LPC11: Only print none-null unknown idcodes.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes 0995fe1288 cmsis-dap: Various fixes 
- decrease report size to 64, otherwise MIMRXT10x0-EVK crashed when
  reading larger memory block
- dp_read_reg acts direct, fixing CortexM core register read.
- length of data to write with read_block.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes f15b1d7763 cl_utils: Clip opt_flash_start only when not set. 2020-10-23 09:40:15 +02:00
Uwe Bonnes c161521c26 cortexm: Designer ARM must be in the default path when probing. 2020-10-23 09:40:15 +02:00
Uwe Bonnes cdd07544d5 Cortexm: Allow pure debug on devices not yet handled for flashing 
- Recognize STM32L552 and MIMXRT10XX
- Fix another PIDR
- Fix bad debug print string.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes 3270138ec2 Revert 69e577c9243ce027b628e96881ce2416213fef43 
What was thought to be a typo is apsel = 0xff for a dp access.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes 77c4f9d702 stlink: Rework README.md 
- Document flashing BMP Firmware and reverting to ST firmware
- Consistant nameing
 2020-10-19 14:13:29 +02:00
Uwe Bonnes 9cd3193a89 bmp_remote.c: Fix bug introduced with 8b929c12c9. 2020-10-17 12:49:37 +02:00
Uwe Bonnes 0ffb4f7b18 cortexm: Fix protected SAM detection 
- Only run cortex_prepare() if reading cidr fails
- With Atmel DSU detected, run cortexm_probe()
 2020-10-17 12:49:37 +02:00
Uwe Bonnes 5bc743d221 samd: Propagate security after setting security by chip reset. 2020-10-17 12:49:37 +02:00