Compare commits
7 Commits
jtaglib-cp
...
ezfet3-fix
Author | SHA1 | Date |
---|---|---|
Triss | 15edaf3c84 | |
Triss | b8ed9d7194 | |
Triss | fc79881203 | |
Triss | 4db31c4287 | |
Triss | 2ff6badecd | |
Triss | 3602ed39f9 | |
Triss | dc77c43d80 |
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@ -4,3 +4,5 @@ mspdebug
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mspdebug.exe
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mspdebug.exe
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inst/
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inst/
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config.mk
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config.mk
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*.pcapng
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*.pcapng.gz
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2
Makefile
2
Makefile
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@ -16,6 +16,8 @@
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# along with this program; if not, write to the Free Software
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-include config.mk
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CC ?= gcc
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CC ?= gcc
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INSTALL = /usr/bin/install
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INSTALL = /usr/bin/install
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PREFIX ?= /usr/local
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PREFIX ?= /usr/local
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@ -85045,7 +85045,7 @@ const struct chipinfo chipinfo_db[] = { {
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.id = {
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.id = {
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.ver_id = 0x82a1,
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.ver_id = 0x82a1,
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.ver_sub_id = 0x0000,
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.ver_sub_id = 0x0000,
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.revision = 0x10,
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.revision = /*0x10*/0x21,
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.fab = 0x00,
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.fab = 0x00,
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.self = 0x0000,
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.self = 0x0000,
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.config = 0x00,
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.config = 0x00,
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@ -85084,7 +85084,7 @@ const struct chipinfo chipinfo_db[] = { {
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[0x18] = 0x3f,
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[0x18] = 0x3f,
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[0x19] = 0x3f,
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[0x19] = 0x3f,
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[0x1a] = 0x40,
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[0x1a] = 0x40,
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[0x1c] = 0x50,
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[0x1c] = /*0x50*/0x41,
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[0x1d] = 0x42,
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[0x1d] = 0x42,
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[0x1e] = 0x43,
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[0x1e] = 0x43,
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[0x1f] = 0x44,
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[0x1f] = 0x44,
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@ -34,6 +34,7 @@ void hal_proto_init(struct hal_proto *p, transport_t trans,
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int hal_proto_send(struct hal_proto *p, hal_proto_type_t type,
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int hal_proto_send(struct hal_proto *p, hal_proto_type_t type,
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const uint8_t *data, int length)
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const uint8_t *data, int length)
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{
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{
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//asm volatile("int3");
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uint8_t buf[512];
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uint8_t buf[512];
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size_t len = 0;
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size_t len = 0;
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@ -77,8 +78,57 @@ int hal_proto_send(struct hal_proto *p, hal_proto_type_t type,
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return 0;
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return 0;
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}
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}
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static int hal_proto_send_ack(struct hal_proto *p, hal_proto_type_t type,
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const uint8_t *data, int length)
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{
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//asm volatile("int3");
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uint8_t buf[512];
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size_t len = 0;
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if (length > HAL_MAX_PAYLOAD) {
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printc_err("hal_proto_send_ack: payload too long: %d\n", length);
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return -1;
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}
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buf[len++] = length + 3;
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buf[len++] = type;
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buf[len++] = (p->ref_id - 1) & 0xff;
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buf[len++] = 0;
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//p->ref_id = (p->ref_id + 1) & 0x7f;
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memcpy(buf + len, data, length);
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len += length;
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if (len & 1)
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buf[len++] = 0;
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if (p->flags & HAL_PROTO_CHECKSUM) {
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size_t i;
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uint8_t sum_l = 0xff;
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uint8_t sum_h = 0xff;
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for (i = 0; i < len; i += 2) {
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sum_l ^= buf[i];
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sum_h ^= buf[i + 1];
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}
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buf[len++] = sum_l;
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buf[len++] = sum_h;
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}
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if (p->trans->ops->send(p->trans, buf, len) < 0) {
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printc_err("hal_proto_send_ack: type: 0x%02x\n", type);
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return -1;
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}
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return 0;
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}
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int hal_proto_receive(struct hal_proto *p, uint8_t *buf, int max_len)
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int hal_proto_receive(struct hal_proto *p, uint8_t *buf, int max_len)
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{
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{
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//asm volatile("int3");
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uint8_t rx_buf[512];
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uint8_t rx_buf[512];
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uint8_t sum_h = 0xff;
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uint8_t sum_h = 0xff;
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uint8_t sum_l = 0xff;
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uint8_t sum_l = 0xff;
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@ -144,10 +194,11 @@ int hal_proto_receive(struct hal_proto *p, uint8_t *buf, int max_len)
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int hal_proto_execute(struct hal_proto *p, uint8_t fid,
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int hal_proto_execute(struct hal_proto *p, uint8_t fid,
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const uint8_t *data, int len)
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const uint8_t *data, int len)
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{
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{
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//asm volatile("int3");
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uint8_t fdata[HAL_MAX_PAYLOAD];
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uint8_t fdata[HAL_MAX_PAYLOAD];
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if (len + 2 > HAL_MAX_PAYLOAD) {
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if (len + 2 > HAL_MAX_PAYLOAD) {
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printc_err("hal_proto_execute: payload too big: %d\n", len);
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printc_err("hal_proto_execute: fid 0x%02x: payload too big: %d\n", fid, len);
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return -1;
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return -1;
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}
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}
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@ -168,8 +219,8 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
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goto fail;
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goto fail;
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if ((p->type == HAL_PROTO_TYPE_EXCEPTION) && (r >= 2)) {
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if ((p->type == HAL_PROTO_TYPE_EXCEPTION) && (r >= 2)) {
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printc_err("hal_proto_execute: HAL exception: 0x%04x\n",
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printc_err("hal_proto_execute: fid 0x%02x: HAL exception: 0x%04x\n",
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LE_WORD(p->payload, p->length));
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fid, LE_WORD(p->payload, p->length));
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goto fail;
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goto fail;
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}
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}
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@ -177,12 +228,12 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
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break;
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break;
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if (p->type != HAL_PROTO_TYPE_DATA) {
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if (p->type != HAL_PROTO_TYPE_DATA) {
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printc_err("hal_proto_execute: no data "
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printc_err("hal_proto_execute: fid 0x%02x: no data "
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"(got type 0x%02x)\n", p->type);
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"(got type 0x%02x)\n", fid, p->type);
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goto fail;
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goto fail;
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}
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}
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if (hal_proto_send(p, HAL_PROTO_TYPE_ACKNOWLEDGE, NULL, 0) < 0)
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if (hal_proto_send_ack(p, HAL_PROTO_TYPE_ACKNOWLEDGE, NULL, 0) < 0)
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goto fail;
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goto fail;
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p->length += r;
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p->length += r;
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@ -191,6 +242,6 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
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return 0;
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return 0;
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fail:
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fail:
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printc_err("hal_proto_execute: fid: 0x%02x\n", fid);
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printc_err("hal_proto_execute: fid: 0x%02x: failed\n", fid);
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return -1;
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return -1;
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}
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}
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@ -37,6 +37,11 @@ typedef enum {
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HAL_PROTO_TYPE_DCDC_POWER_DOWN = 0x60,
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HAL_PROTO_TYPE_DCDC_POWER_DOWN = 0x60,
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HAL_PROTO_TYPE_DCDC_SET_VCC = 0x61,
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HAL_PROTO_TYPE_DCDC_SET_VCC = 0x61,
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HAL_PROTO_TYPE_DCDC_RESTART = 0x62,
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HAL_PROTO_TYPE_DCDC_RESTART = 0x62,
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HAL_PROTO_TYPE_CORE_SET_VCC = 0x63,
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HAL_PROTO_TYPE_CORE_GET_VCC = 0x64,
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HAL_PROTO_TYPE_CORE_SWITCH_FET = 0x65,
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HAL_PROTO_TYPE_CMP_VERSIONS = 0x66,
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HAL_PROTO_TYPE_CMD_LEGACY = 0x7e,
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HAL_PROTO_TYPE_CMD_LEGACY = 0x7e,
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HAL_PROTO_TYPE_CMD_SYNC = 0x80,
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HAL_PROTO_TYPE_CMD_SYNC = 0x80,
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HAL_PROTO_TYPE_CMD_EXECUTE = 0x81,
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HAL_PROTO_TYPE_CMD_EXECUTE = 0x81,
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@ -52,6 +57,9 @@ typedef enum {
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HAL_PROTO_TYPE_CMD_COM_RESET = 0x8b,
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HAL_PROTO_TYPE_CMD_COM_RESET = 0x8b,
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HAL_PROTO_TYPE_CMD_PAUSE_LOOP = 0x8c,
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HAL_PROTO_TYPE_CMD_PAUSE_LOOP = 0x8c,
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HAL_PROTO_TYPE_CMD_RESUME_LOOP = 0x8d,
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HAL_PROTO_TYPE_CMD_RESUME_LOOP = 0x8d,
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HAL_PROTO_TYPE_CMD_KILL_ALL = 0x8e,
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HAL_PROTO_TYPE_CMD_OVER_CURRENT = 0x8f,
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HAL_PROTO_TYPE_ACKNOWLEDGE = 0x91,
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HAL_PROTO_TYPE_ACKNOWLEDGE = 0x91,
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HAL_PROTO_TYPE_EXCEPTION = 0x92,
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HAL_PROTO_TYPE_EXCEPTION = 0x92,
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HAL_PROTO_TYPE_DATA = 0x93,
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HAL_PROTO_TYPE_DATA = 0x93,
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@ -63,6 +71,122 @@ typedef enum {
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HAL_PROTO_CHECKSUM = 0x01
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HAL_PROTO_CHECKSUM = 0x01
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} hal_proto_flags_t;
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} hal_proto_flags_t;
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typedef enum {
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HAL_PROTO_ERR_NONE = 0x00,
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HAL_PROTO_ERR_UNDEFINED = 0xffff,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_RAM_START = 0xFFFE,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_RAM_SIZE = 0xFFFD,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_OFFSET = 0xFFFC,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_ADDRESS = 0xFFFB,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_LENGTH = 0xFFFA,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_TYPE = 0xFFF9,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_LOCKA = 0xFFF8,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_TIMEOUT = 0xFFF7,
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HAL_PROTO_ERR_EXECUTE_FUNCLET_EXECUTION_ERROR = 0xFFF6,
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HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_ADDRESS = 0xFFF5,
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HAL_PROTO_ERR_WRITE_MEM_WORD_NO_RAM_SIZE = 0xFFF4,
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HAL_PROTO_ERR_WRITE_MEM_WORD_UNKNOWN = 0xFFF3,
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HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_ADDRESS = 0xFFF2,
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HAL_PROTO_ERR_WRITE_MEM_BYTES_NO_RAM_SIZE = 0xFFF1,
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HAL_PROTO_ERR_WRITE_MEM_BYTES_UNKNOWN = 0xFFF0,
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HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_ADDRESS = 0xFFEF,
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HAL_PROTO_ERR_WRITE_FLASH_WORD_NO_FLASH_SIZE = 0xFFEE,
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HAL_PROTO_ERR_WRITE_FLASH_WORD_UNKNOWN = 0xFFED,
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HAL_PROTO_ERR_WRITE_FLASH_QUICK_UNKNOWN = 0xFFEC,
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HAL_PROTO_ERR_START_JTAG_NO_PROTOCOL = 0xFFEB,
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HAL_PROTO_ERR_START_JTAG_PROTOCOL_UNKNOWN = 0xFFEA,
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HAL_PROTO_ERR_SET_CHAIN_CONFIGURATION_STREAM = 0xFFE9,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_ADDRESS = 0xFFE8,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_WDT_VALUE = 0xFFE7,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_PC = 0xFFE6,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_SR = 0xFFE5,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_CONTROL_MASK =0xFFE4,
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HAL_PROTO_ERR_RESTORECONTEXT_RELEASE_JTAG_NO_MDB = 0xFFE3,
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HAL_PROTO_ERR_READ_MEM_WORD_NO_ADDRESS = 0xFFF2,
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HAL_PROTO_ERR_READ_MEM_WORD_NO_SIZE = 0xFFF1,
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|
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HAL_PROTO_ERR_READ_MEM_UNKNOWN = 0xFFE0,
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HAL_PROTO_ERR_READ_MEM_BYTES_NO_ADDRESS = 0xFFDF,
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HAL_PROTO_ERR_READ_MEM_BYTES_NO_SIZE = 0xFFDE,
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HAL_PROTO_ERR_PSA_NO_ADDRESS = 0xFFDD,
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HAL_PROTO_ERR_PSA_NO_SIZE = 0xFFDC,
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|
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HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_JTAG_TIMEOUT = 0xFFDB,
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HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_ADDRESS = 0xFFDA,
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HAL_PROTO_ERR_SYNC_JTAG_ASSERT_POR_NO_WDT_VALUE = 0xFFD9,
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|
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HAL_PROTO_ERR_WRITE_ALL_CPU_REGISTERS_STREAM = 0xFFD8,
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|
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HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_ADDRESS = 0xFFD7,
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HAL_PROTO_ERR_WRITE_MEM_WORD_XV2_NO_RAM_SIZE = 0xFFD6,
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|
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HAL_PROTO_ERR_SECURE_NO_TGT_HAS_TEST_PIN = 0xFFD5,
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|
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HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_JTAG_TIMEOUT = 0xFFD4,
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HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_ADDRESS = 0xFFD3,
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HAL_PROTO_ERR_SYNC_JTAG_CONDITIONAL_NO_WDT_VALUE = 0xFFD2,
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|
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|
HAL_PROTO_ERR_INSTRUCTION_BOUNDARY_ERROR = 0xFFD1,
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|
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|
HAL_PROTO_ERR_JTAG_VERSION_MISMATCH = 0xFFD0,
|
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|
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|
HAL_PROTO_ERR_JTAG_MAILBOX_IN_TIMOUT = 0xFFCF,
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|
HAL_PROTO_ERR_JTAG_PASSWORD_WRONG = 0xFFCE,
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|
|
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|
HAL_PROTO_ERR_START_JTAG_NO_ACTIVATION_CODE = 0xFFCD,
|
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|
HAL_PROTO_ERR_SINGLESTEP_WAITFOREEM_TIMEOUT = 0xFFCC,
|
||||||
|
|
||||||
|
HAL_PROTO_ERR_CONFIG_NO_PARAMETER = 0xFFCB,
|
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|
HAL_PROTO_ERR_CONFIG_NO_VALUE = 0xFFCA,
|
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|
HAL_PROTO_ERR_CONFIG_PARAM_UNKNOWN_PARAMETER = 0xFFC9,
|
||||||
|
|
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|
HAL_PROTO_ERR_NO_NUM_BITS = 0xFFC8,
|
||||||
|
HAL_PROTO_ERR_ARRAY_SIZE_MISMATCH = 0xFFC7,
|
||||||
|
|
||||||
|
HAL_PROTO_ERR_NO_COMMAND = 0xFFC6,
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|
HAL_PROTO_ERR_UNKNOWN_COMMAND = 0xFFC5,
|
||||||
|
HAL_PROTO_ERR_NO_DATA = 0xFFC4,
|
||||||
|
HAL_PROTO_ERR_NO_BIT_SIZE = 0xFFC3,
|
||||||
|
HAL_PROTO_ERR_INVALID_BIT_SIZE = 0xFFC2,
|
||||||
|
|
||||||
|
HAL_PROTO_ERR_UNLOCK_NO_PASSWORD_LENGTH = 0xFFC1,
|
||||||
|
HAL_PROTO_ERR_UNLOCK_INVALID_PASSWORD_LENGTH = 0xFFC0,
|
||||||
|
|
||||||
|
HAL_PROTO_ERR_EXECUTE_FUNCLET_FINISH_TIMEOUT = 0xFFBF,
|
||||||
|
|
||||||
|
HAL_PROTO_ERR_EXECUTE_FUNCLET_NO_MAXRSEL = 0xFFBE,
|
||||||
|
|
||||||
|
HAL_PROTO_ERR_API_CALL_NOT_SUPPORTED = 0xFFBD,
|
||||||
|
|
||||||
|
HAL_PROTO_ERR_MAGIC_PATTERN = 0xFFBC,
|
||||||
|
HAL_PROTO_ERR_MAGIC_PATTERN_BOOT_DATA_CRC_WRONG = 0xFFBB,
|
||||||
|
HAL_PROTO_ERR_DAP_NACK = 0xFFBA,
|
||||||
|
|
||||||
|
HAL_PROTO_MESSAGE_NO_RESPONSE = 0x8000,
|
||||||
|
HAL_PROTO_EXCEPTION_NOT_IMPLEMENT_ERR = 0x8001,
|
||||||
|
HAL_PROTO_EXCEPTION_MSGID_ERR = 0x8002,
|
||||||
|
HAL_PROTO_EXCEPTION_CRC_ERR = 0x8003,
|
||||||
|
HAL_PROTO_EXCEPTION_RX_TIMEOUT_ERR = 0x8004,
|
||||||
|
HAL_PROTO_EXCEPTION_TX_TIMEOUT_ERR = 0x8005,
|
||||||
|
HAL_PROTO_EXCEPTION_RX_OVERFLOW_ERR = 0x8006,
|
||||||
|
HAL_PROTO_EXCEPTION_TX_NO_BUFFER = 0x8007,
|
||||||
|
HAL_PROTO_EXCEPTION_COM_RESET = 0x8008,
|
||||||
|
HAL_PROTO_EXCEPTION_RX_NO_BUFFER = 0x8009,
|
||||||
|
HAL_PROTO_EXCEPTION_RX_TO_SMALL_BUFFER = 0x800A,
|
||||||
|
HAL_PROTO_EXCEPTION_RX_LENGTH = 0x800B,
|
||||||
|
} hal_proto_error_t;
|
||||||
|
|
||||||
#define HAL_MAX_PAYLOAD 253
|
#define HAL_MAX_PAYLOAD 253
|
||||||
|
|
||||||
struct hal_proto {
|
struct hal_proto {
|
||||||
|
|
439
drivers/v3hil.c
439
drivers/v3hil.c
|
@ -16,13 +16,21 @@
|
||||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
|
#include <stdio.h>
|
||||||
#include "bytes.h"
|
#include "bytes.h"
|
||||||
#include "v3hil.h"
|
#include "v3hil.h"
|
||||||
#include "dis.h"
|
#include "dis.h"
|
||||||
#include "output.h"
|
#include "output.h"
|
||||||
#include "opdb.h"
|
#include "opdb.h"
|
||||||
|
|
||||||
|
#ifdef DEBUG_V3HIL
|
||||||
|
#define dbg_printc(fmt, ...) printc_dbg("v3hil: " fmt, ##__VA_ARGS__)
|
||||||
|
#else
|
||||||
|
#define dbg_printc(fmt, ...) do{}while(0)
|
||||||
|
#endif
|
||||||
|
|
||||||
/* HAL function IDs */
|
/* HAL function IDs */
|
||||||
typedef enum {
|
typedef enum {
|
||||||
HAL_PROTO_FID_INIT = 0x01,
|
HAL_PROTO_FID_INIT = 0x01,
|
||||||
|
@ -41,73 +49,99 @@ typedef enum {
|
||||||
HAL_PROTO_FID_SET_CHAIN_CONFIGURATION = 0x0e,
|
HAL_PROTO_FID_SET_CHAIN_CONFIGURATION = 0x0e,
|
||||||
HAL_PROTO_FID_GET_NUM_DEVICES = 0x0f,
|
HAL_PROTO_FID_GET_NUM_DEVICES = 0x0f,
|
||||||
HAL_PROTO_FID_GET_INTERFACE_MODE = 0x10,
|
HAL_PROTO_FID_GET_INTERFACE_MODE = 0x10,
|
||||||
HAL_PROTO_FID_SJ_ASSERT_POR_SC = 0x11,
|
HAL_PROTO_FID_GET_DEVICE_ID_PTR = 0x11,
|
||||||
HAL_PROTO_FID_SJ_CONDITIONAL_SC = 0x12,
|
HAL_PROTO_FID_SJ_ASSERT_POR_SC ,
|
||||||
HAL_PROTO_FID_RC_RELEASE_JTAG = 0x13,
|
HAL_PROTO_FID_SJ_CONDITIONAL_SC ,
|
||||||
HAL_PROTO_FID_READ_MEM_BYTES = 0x14,
|
HAL_PROTO_FID_RC_RELEASE_JTAG ,
|
||||||
HAL_PROTO_FID_READ_MEM_WORDS = 0x15,
|
HAL_PROTO_FID_READ_MEM_BYTES ,
|
||||||
HAL_PROTO_FID_READ_MEM_QUICK = 0x16,
|
HAL_PROTO_FID_READ_MEM_WORDS ,
|
||||||
HAL_PROTO_FID_WRITE_MEM_BYTES = 0x17,
|
HAL_PROTO_FID_READ_MEM_QUICK ,
|
||||||
HAL_PROTO_FID_WRITE_MEM_WORDS = 0x18,
|
HAL_PROTO_FID_WRITE_MEM_BYTES ,
|
||||||
HAL_PROTO_FID_EEM_DX = 0x19,
|
HAL_PROTO_FID_WRITE_MEM_WORDS ,
|
||||||
HAL_PROTO_FID_EEM_DX_AFE2XX = 0x1a,
|
HAL_PROTO_FID_EEM_DX ,
|
||||||
HAL_PROTO_FID_SINGLE_STEP = 0x1b,
|
HAL_PROTO_FID_EEM_DX_AFE2XX ,
|
||||||
HAL_PROTO_FID_READ_ALL_CPU_REGS = 0x1c,
|
HAL_PROTO_FID_SINGLE_STEP ,
|
||||||
HAL_PROTO_FID_WRITE_ALL_CPU_REGS = 0x1d,
|
HAL_PROTO_FID_READ_ALL_CPU_REGS ,
|
||||||
HAL_PROTO_FID_PSA = 0x1e,
|
HAL_PROTO_FID_WRITE_ALL_CPU_REGS ,
|
||||||
HAL_PROTO_FID_EXECUTE_FUNCLET = 0x1f,
|
HAL_PROTO_FID_PSA ,
|
||||||
HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG = 0x20,
|
HAL_PROTO_FID_EXECUTE_FUNCLET , // 0x20
|
||||||
HAL_PROTO_FID_GET_DCO_FREQUENCY = 0x21,
|
HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG ,
|
||||||
HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG = 0x22,
|
HAL_PROTO_FID_GET_DCO_FREQUENCY ,
|
||||||
HAL_PROTO_FID_GET_FLL_FREQUENCY = 0x23,
|
HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG ,
|
||||||
HAL_PROTO_FID_GET_FLL_FREQUENCY_JTAG = 0x24,
|
HAL_PROTO_FID_GET_FLL_FREQUENCY ,
|
||||||
HAL_PROTO_FID_WAIT_FOR_STORAGE = 0x25,
|
HAL_PROTO_FID_GET_FLL_FREQUENCY_JTAG ,
|
||||||
HAL_PROTO_FID_SJ_ASSERT_POR_SC_X = 0x26,
|
HAL_PROTO_FID_WAIT_FOR_STORAGE ,
|
||||||
HAL_PROTO_FID_SJ_CONDITIONAL_SC_X = 0x27,
|
HAL_PROTO_FID_SJ_ASSERT_POR_SC_X ,
|
||||||
HAL_PROTO_FID_RC_RELEASE_JTAG_X = 0x28,
|
HAL_PROTO_FID_SJ_CONDITIONAL_SC_X ,
|
||||||
HAL_PROTO_FID_READ_MEM_BYTES_X = 0x29,
|
HAL_PROTO_FID_RC_RELEASE_JTAG_X ,
|
||||||
HAL_PROTO_FID_READ_MEM_WORDS_X = 0x2a,
|
HAL_PROTO_FID_READ_MEM_BYTES_X ,
|
||||||
HAL_PROTO_FID_READ_MEM_QUICK_X = 0x2b,
|
HAL_PROTO_FID_READ_MEM_WORDS_X ,
|
||||||
HAL_PROTO_FID_WRITE_MEM_BYTES_X = 0x2c,
|
HAL_PROTO_FID_READ_MEM_QUICK_X ,
|
||||||
HAL_PROTO_FID_WRITE_MEM_WORDS_X = 0x2d,
|
HAL_PROTO_FID_WRITE_MEM_BYTES_X ,
|
||||||
HAL_PROTO_FID_EEM_DX_X = 0x2e,
|
HAL_PROTO_FID_WRITE_MEM_WORDS_X ,
|
||||||
HAL_PROTO_FID_SINGLE_STEP_X = 0x2f,
|
HAL_PROTO_FID_EEM_DX_X ,
|
||||||
HAL_PROTO_FID_READ_ALL_CPU_REGS_X = 0x30,
|
HAL_PROTO_FID_SINGLE_STEP_X ,
|
||||||
HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X = 0x31,
|
HAL_PROTO_FID_READ_ALL_CPU_REGS_X ,
|
||||||
HAL_PROTO_FID_PSA_X = 0x32,
|
HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X , // 0x30
|
||||||
HAL_PROTO_FID_EXECUTE_FUNCLET_X = 0x33,
|
HAL_PROTO_FID_PSA_X ,
|
||||||
HAL_PROTO_FID_GET_DCO_FREQUENCY_X = 0x34,
|
HAL_PROTO_FID_EXECUTE_FUNCLET_X ,
|
||||||
HAL_PROTO_FID_GET_FLL_FREQUENCY_X = 0x35,
|
HAL_PROTO_FID_GET_DCO_FREQUENCY_X ,
|
||||||
HAL_PROTO_FID_WAIT_FOR_STORAGE_X = 0x36,
|
HAL_PROTO_FID_GET_FLL_FREQUENCY_X ,
|
||||||
HAL_PROTO_FID_BLOW_FUSE_XV2 = 0x37,
|
HAL_PROTO_FID_WAIT_FOR_STORAGE_X ,
|
||||||
HAL_PROTO_FID_BLOW_FUSE_FRAM = 0x38,
|
HAL_PROTO_FID_BLOW_FUSE_XV2 ,
|
||||||
HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2 = 0x39,
|
HAL_PROTO_FID_BLOW_FUSE_FRAM ,
|
||||||
HAL_PROTO_FID_SJ_CONDITIONAL_SC_XV2 = 0x3a,
|
HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2 ,
|
||||||
HAL_PROTO_FID_RC_RELEASE_JTAG_XV2 = 0x3b,
|
HAL_PROTO_FID_SJ_CONDITIONAL_SC_XV2 ,
|
||||||
HAL_PROTO_FID_READ_MEM_WORDS_XV2 = 0x3c,
|
HAL_PROTO_FID_RC_RELEASE_JTAG_XV2 ,
|
||||||
HAL_PROTO_FID_READ_MEM_QUICK_XV2 = 0x3d,
|
HAL_PROTO_FID_READ_MEM_WORDS_XV2 ,
|
||||||
HAL_PROTO_FID_WRITE_MEM_WORDS_XV2 = 0x3e,
|
HAL_PROTO_FID_READ_MEM_QUICK_XV2 ,
|
||||||
HAL_PROTO_FID_EEM_DX_XV2 = 0x3f,
|
HAL_PROTO_FID_WRITE_MEM_WORDS_XV2 ,
|
||||||
HAL_PROTO_FID_SINGLE_STEP_XV2 = 0x40,
|
HAL_PROTO_FID_EEM_DX_XV2 ,
|
||||||
HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2 = 0x41,
|
HAL_PROTO_FID_SINGLE_STEP_XV2 , // 0x40
|
||||||
HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2 = 0x42,
|
HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2 ,
|
||||||
HAL_PROTO_FID_PSA_XV2 = 0x43,
|
HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2 ,
|
||||||
HAL_PROTO_FID_EXECUTE_FUNCLET_XV2 = 0x44,
|
HAL_PROTO_FID_PSA_XV2 ,
|
||||||
HAL_PROTO_FID_UNLOCK_DEVICE_XV2 = 0x45,
|
HAL_PROTO_FID_EXECUTE_FUNCLET_XV2 ,
|
||||||
HAL_PROTO_FID_MAGIC_PATTERN = 0x46,
|
HAL_PROTO_FID_UNLOCK_DEVICE_XV2 ,
|
||||||
HAL_PROTO_FID_UNLOCK_C092 = 0x47,
|
HAL_PROTO_FID_MAGIC_PATTERN ,
|
||||||
HAL_PROTO_FID_HIL_COMMAND = 0x48,
|
HAL_PROTO_FID_UNLOCK_C092 ,
|
||||||
HAL_PROTO_FID_POLL_JSTATE_REG = 0x49,
|
HAL_PROTO_FID_HIL_COMMAND ,
|
||||||
HAL_PROTO_FID_POLL_JSTATE_REG_FR57XX = 0x4a,
|
HAL_PROTO_FID_POLL_JSTATE_REG ,
|
||||||
HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN = 0x4b,
|
HAL_PROTO_FID_POLL_JSTATE_REG_FR57XX ,
|
||||||
HAL_PROTO_FID_RESET_XV2 = 0x4c,
|
HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN ,
|
||||||
HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2 = 0x4d,
|
HAL_PROTO_FID_RESET_XV2 ,
|
||||||
HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2 = 0x4e,
|
HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2 ,
|
||||||
HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2 = 0x4f,
|
HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2 ,
|
||||||
HAL_PROTO_FID_POLL_JSTATE_REG_ET8 = 0x50,
|
HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2 ,
|
||||||
HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS = 0x51,
|
HAL_PROTO_FID_POLL_JSTATE_REG_ET8 ,
|
||||||
HAL_PROTO_FID_RESET_430I = 0x52,
|
HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS , // 0x50
|
||||||
HAL_PROTO_FID_POLL_JSTATE_REG_430I = 0x53
|
HAL_PROTO_FID_RESET_430I ,
|
||||||
|
HAL_PROTO_FID_POLL_JSTATE_REG_430I ,
|
||||||
|
HAL_PROTO_FID_POLL_JSTATE_REG_20 ,
|
||||||
|
HAL_PROTO_FID_SWITCH_MOSFET ,
|
||||||
|
HAL_PROTO_FID_RESET_L092 ,
|
||||||
|
HAL_PROTO_FID_DUMMY_MACRO,
|
||||||
|
HAL_PROTO_FID_RESET_5438XV2,
|
||||||
|
HAL_PROTO_FID_LEA_SYNC_COND,
|
||||||
|
HAL_PROTO_FID_GET_JTAG_ID_CODE_ARM,
|
||||||
|
HAL_PROTO_FID_SCAN_AP_ARM,
|
||||||
|
HAL_PROTO_FID_MEM_AP_TRANSACTION_ARM,
|
||||||
|
HAL_PROTO_FID_READ_ALL_CPU_REGS_ARM,
|
||||||
|
HAL_PROTO_FID_WRITE_ALL_CPU_REGS_ARM,
|
||||||
|
HAL_PROTO_FID_ENABLE_DEBUG_ARM,
|
||||||
|
HAL_PROTO_FID_DISABLE_DEBUG_ARM,
|
||||||
|
HAL_PROTO_FID_RUN_ARM,
|
||||||
|
HAL_PROTO_FID_HALT_ARM,
|
||||||
|
HAL_PROTO_FID_RESET_ARM,
|
||||||
|
HAL_PROTO_FID_SINGLE_STEP_ARM,
|
||||||
|
HAL_PROTO_FID_WAIT_FOR_DEBUG_HALT_ARM,
|
||||||
|
HAL_PROTO_FID_MEM_AP_TRANSACTION_ARM_SWD,
|
||||||
|
HAL_PROTO_FID_GET_ITF_MODE_ARM,
|
||||||
|
HAL_PROTO_FID_POLL_DSTATE_PCREG_ET,
|
||||||
|
HAL_PROTO_FID_GET_CPU_ID_ARM,
|
||||||
|
HAL_PROTO_FID_CHECK_DAP_LOCK_ARM,
|
||||||
|
HAL_PROTO_FID_UNLOCK_DAP,
|
||||||
|
HAL_PROTO_FID_USS_SYNC_COND
|
||||||
} hal_proto_fid_t;
|
} hal_proto_fid_t;
|
||||||
|
|
||||||
/* Argument types for HAL_PROTO_FID_CONFIGURE */
|
/* Argument types for HAL_PROTO_FID_CONFIGURE */
|
||||||
|
@ -126,14 +160,47 @@ typedef enum {
|
||||||
HAL_PROTO_CONFIG_SFLLDEH = 0x0c,
|
HAL_PROTO_CONFIG_SFLLDEH = 0x0c,
|
||||||
HAL_PROTO_CONFIG_NO_BSL = 0x0d,
|
HAL_PROTO_CONFIG_NO_BSL = 0x0d,
|
||||||
HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ = 0x0e,
|
HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ = 0x0e,
|
||||||
HAL_PROTO_CONFIG_ASSERT_BSL_VALID_BIT = 0x0f
|
HAL_PROTO_CONFIG_ASSERT_BSL_VALID_BIT = 0x0f,
|
||||||
|
HAL_PROTO_CONFIG_POWER_TESTREG_DEFAULT = 0x10,
|
||||||
|
HAL_PROTO_CONFIG_POWER_TESTREGV3_DEFAULT = 0x11,
|
||||||
|
HAL_PROTO_CONFIG_WDT_ADDRESS_5XX = 0x12,
|
||||||
|
HAL_PROTO_CONFIG_SCS_BASE_ADDRESS = 0x13,
|
||||||
|
HAL_PROTO_CONFIG_FPB_BASE_ADDRESS = 0x14,
|
||||||
|
HAL_PROTO_CONFIG_INTERRUPT_OPTIONS = 0x15,
|
||||||
|
HAL_PROTO_CONFIG_ULP_MSP432 = 0x16,
|
||||||
|
HAL_PROTO_CONFIG_JTAG_LOCK_5XX = 0x17
|
||||||
} hal_proto_config_t;
|
} hal_proto_config_t;
|
||||||
|
|
||||||
|
static hal_proto_fid_t map_ver(const struct v3hil *h, hal_proto_fid_t src) {
|
||||||
|
hal_proto_fid_t dst;
|
||||||
|
|
||||||
|
if (h->proto_ver < 0x0300 && src > HAL_PROTO_FID_GET_DEVICE_ID_PTR) {
|
||||||
|
dst = src - 1;
|
||||||
|
} else {
|
||||||
|
dst = src;
|
||||||
|
}
|
||||||
|
|
||||||
|
dbg_printc("map ver: %02x -> %02x\n", src, dst);
|
||||||
|
return dst;
|
||||||
|
}
|
||||||
static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src)
|
static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src)
|
||||||
{
|
{
|
||||||
hal_proto_fid_t dst = h->chip->v3_functions[src];
|
hal_proto_fid_t src2 = src, dst, dst2;
|
||||||
|
|
||||||
return dst ? dst : src;
|
if (src > HAL_PROTO_FID_GET_DEVICE_ID_PTR && false) {
|
||||||
|
src2 = src - 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
dst = h->chip->v3_functions[src2];
|
||||||
|
|
||||||
|
if (dst) {
|
||||||
|
dst2 = dst;
|
||||||
|
} else {
|
||||||
|
dst2 = src;
|
||||||
|
}
|
||||||
|
|
||||||
|
dbg_printc("map fid: %02x -> %02x\n", src, dst2);
|
||||||
|
return map_ver(h, dst2);
|
||||||
}
|
}
|
||||||
|
|
||||||
void v3hil_init(struct v3hil *h, transport_t trans,
|
void v3hil_init(struct v3hil *h, transport_t trans,
|
||||||
|
@ -148,7 +215,8 @@ int v3hil_set_vcc(struct v3hil *h, int vcc_mv)
|
||||||
uint8_t data[2];
|
uint8_t data[2];
|
||||||
|
|
||||||
w16le(data, vcc_mv);
|
w16le(data, vcc_mv);
|
||||||
return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_VCC, data, 2);
|
dbg_printc("Setting VCC...\n");
|
||||||
|
return hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_SET_VCC), data, 2);
|
||||||
}
|
}
|
||||||
|
|
||||||
int v3hil_comm_init(struct v3hil *h)
|
int v3hil_comm_init(struct v3hil *h)
|
||||||
|
@ -163,6 +231,43 @@ int v3hil_comm_init(struct v3hil *h)
|
||||||
return -1;
|
return -1;
|
||||||
if (h->hal.length < 8) {
|
if (h->hal.length < 8) {
|
||||||
printc_err("warning: v3hil: short reply to version request\n");
|
printc_err("warning: v3hil: short reply to version request\n");
|
||||||
|
} else if (h->hal.length == 40) {
|
||||||
|
#ifdef DEBUG_V3HIL
|
||||||
|
printc_dbg("v3hil: Version:");
|
||||||
|
for (int i = 0; i < h->hal.length; i++)
|
||||||
|
printc_dbg(" %02x", h->hal.payload[i]);
|
||||||
|
printc_dbg("\n");
|
||||||
|
#endif
|
||||||
|
const uint16_t sw_version = r32le(h->hal.payload + 0);
|
||||||
|
const uint16_t sw_build = r32le(h->hal.payload + 2);
|
||||||
|
const uint32_t hw_thing = r32le(h->hal.payload + 4);
|
||||||
|
const uint32_t tool_id = r16le(h->hal.payload + 8);
|
||||||
|
const uint16_t core_version = r16le(h->hal.payload + 10);
|
||||||
|
const uint16_t hil_version = r16le(h->hal.payload + 12);
|
||||||
|
const uint16_t dcdc_layer_version = r16le(h->hal.payload + 14);
|
||||||
|
const uint16_t dcdc_mcu_version = r16le(h->hal.payload + 16);
|
||||||
|
const uint16_t com_version = r16le(h->hal.payload + 18);
|
||||||
|
|
||||||
|
const uint16_t hil_crc = r16le(h->hal.payload + 20);
|
||||||
|
const uint16_t hal_crc = r16le(h->hal.payload + 22);
|
||||||
|
const uint16_t dcdc_crc = r16le(h->hal.payload + 24);
|
||||||
|
const uint16_t core_crc = r16le(h->hal.payload + 26);
|
||||||
|
const uint16_t com_crc = r16le(h->hal.payload + 28);
|
||||||
|
|
||||||
|
const uint16_t fpga_version = r16le(h->hal.payload + 30);
|
||||||
|
const uint16_t n_rx_queues = r16le(h->hal.payload + 32);
|
||||||
|
const uint16_t rx_queue_size = r16le(h->hal.payload + 34);
|
||||||
|
|
||||||
|
const uint8_t major = (sw_version >> 14) + 1;
|
||||||
|
const uint8_t minor = (sw_version >> 8) & 0x3f;
|
||||||
|
const uint8_t patch = sw_version & 0xff;
|
||||||
|
const uint8_t build = sw_build;
|
||||||
|
|
||||||
|
printc_dbg("Version: %d.%d.%d.%d Core version: 0x%02x, HIL version: 0x%02x, HW: 0x%04x\n",
|
||||||
|
major, minor, patch, build,
|
||||||
|
core_version, hil_version, hw_thing);
|
||||||
|
|
||||||
|
h->proto_ver = (major << 8) | minor;
|
||||||
} else {
|
} else {
|
||||||
const uint8_t major = h->hal.payload[1] >> 6;
|
const uint8_t major = h->hal.payload[1] >> 6;
|
||||||
const uint8_t minor = h->hal.payload[1] & 0x3f;
|
const uint8_t minor = h->hal.payload[1] & 0x3f;
|
||||||
|
@ -172,11 +277,13 @@ int v3hil_comm_init(struct v3hil *h)
|
||||||
printc_dbg("Version: %d.%d.%d.%d, HW: 0x%04x\n",
|
printc_dbg("Version: %d.%d.%d.%d, HW: 0x%04x\n",
|
||||||
major, minor, patch, flavour,
|
major, minor, patch, flavour,
|
||||||
r32le(h->hal.payload + 4));
|
r32le(h->hal.payload + 4));
|
||||||
|
|
||||||
|
h->proto_ver = (major << 8) | minor;
|
||||||
}
|
}
|
||||||
|
|
||||||
printc_dbg("Reset firmware...\n");
|
printc_dbg("Reset firmware...\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS, NULL, 0) < 0)
|
map_ver(h, HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS), NULL, 0) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -187,7 +294,8 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
|
||||||
uint8_t data = type;
|
uint8_t data = type;
|
||||||
uint8_t chain_id[2] = {0, 0};
|
uint8_t chain_id[2] = {0, 0};
|
||||||
|
|
||||||
if (hal_proto_execute(&h->hal, HAL_PROTO_FID_START_JTAG,
|
dbg_printc("Start JTAG...\n");
|
||||||
|
if (hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_START_JTAG),
|
||||||
&data, 1) < 0)
|
&data, 1) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
|
||||||
|
@ -202,18 +310,30 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
|
||||||
}
|
}
|
||||||
|
|
||||||
printc_dbg("Device count: %d\n", h->hal.payload[0]);
|
printc_dbg("Device count: %d\n", h->hal.payload[0]);
|
||||||
return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO,
|
return hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO),
|
||||||
chain_id, 2);
|
chain_id, 2);
|
||||||
}
|
}
|
||||||
|
|
||||||
int v3hil_stop_jtag(struct v3hil *h)
|
int v3hil_stop_jtag(struct v3hil *h)
|
||||||
{
|
{
|
||||||
return hal_proto_execute(&h->hal, HAL_PROTO_FID_STOP_JTAG, NULL, 0);
|
dbg_printc("Stop JTAG...\n");
|
||||||
|
if (hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_STOP_JTAG), NULL, 0) < 0)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
dbg_printc("Reset communications...\n");
|
||||||
|
h->hal.ref_id = 0;
|
||||||
|
if (hal_proto_send(&h->hal, HAL_PROTO_TYPE_EXCEPTION, NULL, 0) < 0) {
|
||||||
|
h->hal.ref_id = 0;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
h->hal.ref_id = 0;
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int v3hil_sync(struct v3hil *h)
|
int v3hil_sync(struct v3hil *h)
|
||||||
{
|
{
|
||||||
uint8_t data[32];
|
uint8_t data[64], datalen = 21;
|
||||||
|
|
||||||
h->cal.is_cal = 0;
|
h->cal.is_cal = 0;
|
||||||
|
|
||||||
|
@ -228,8 +348,21 @@ int v3hil_sync(struct v3hil *h)
|
||||||
if (h->chip) {
|
if (h->chip) {
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < 16; i++)
|
for (i = 0; i < 16; i++) {
|
||||||
data[i + 20 - i] = h->chip->clock_map[i].value;
|
dbg_printc("clock map %d = %02x -> %d\n",
|
||||||
|
i, h->chip->clock_map[i].value, 20-i);
|
||||||
|
data[16 + 4 - i] = h->chip->clock_map[i].value;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (h->proto_ver >= 0x0308) {
|
||||||
|
datalen = 21+16;
|
||||||
|
|
||||||
|
for (i = 16; i < 32; i++) {
|
||||||
|
dbg_printc("clock map2 %d = %02x -> %d\n",
|
||||||
|
i, h->chip->clock_map[i].value, 16+4+16*2 - i);
|
||||||
|
data[16+4+16*2 - i] = h->chip->clock_map[i].value;
|
||||||
|
}
|
||||||
|
}
|
||||||
} else {
|
} else {
|
||||||
data[5] = 1;
|
data[5] = 1;
|
||||||
data[15] = 40;
|
data[15] = 40;
|
||||||
|
@ -238,12 +371,36 @@ int v3hil_sync(struct v3hil *h)
|
||||||
/* We can't use map_fid() because h->chip might be NULL -- this
|
/* We can't use map_fid() because h->chip might be NULL -- this
|
||||||
* function will be called before identification is complete.
|
* function will be called before identification is complete.
|
||||||
*/
|
*/
|
||||||
if (hal_proto_execute(&h->hal,
|
hal_proto_fid_t cmdid = (h->jtag_id == 0x90)
|
||||||
(h->jtag_id == 0x89)
|
|
||||||
? HAL_PROTO_FID_SJ_ASSERT_POR_SC
|
? HAL_PROTO_FID_SJ_ASSERT_POR_SC
|
||||||
: HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2,
|
: HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2;
|
||||||
data, 21) < 0)
|
|
||||||
|
dbg_printc("Sync: assert POR\n");
|
||||||
|
if (h->chip) {
|
||||||
|
if (hal_proto_execute(&h->hal, map_fid(h, cmdid), data, datalen) < 0) {
|
||||||
return -1;
|
return -1;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/* Need to do something for X/Xv2 devices, so try each in turn... */
|
||||||
|
cmdid = map_ver(h, cmdid);
|
||||||
|
if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
|
||||||
|
cmdid = map_ver(h, HAL_PROTO_FID_SJ_ASSERT_POR_SC_X);
|
||||||
|
if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
|
||||||
|
cmdid = map_ver(h, HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2);
|
||||||
|
if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef DEBUG_V3HIL
|
||||||
|
printc_dbg("v3hil: POR result: (len %d) ", h->hal.length);
|
||||||
|
for (int i = 0; i < h->hal.length; ++i) {
|
||||||
|
printc_dbg("%02x%s", h->hal.payload[i],
|
||||||
|
(i == h->hal.length - 1) ? "\n" : " ");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
if (h->hal.length < 8) {
|
if (h->hal.length < 8) {
|
||||||
printc_err("v3hil: short reply: %d\n", h->hal.length);
|
printc_err("v3hil: short reply: %d\n", h->hal.length);
|
||||||
|
@ -274,6 +431,7 @@ int v3hil_read(struct v3hil *h, address_t addr,
|
||||||
w32le(req + 4, (m->bits == 8) ? size : (size >> 1));
|
w32le(req + 4, (m->bits == 8) ? size : (size >> 1));
|
||||||
w32le(req + 8, h->regs[MSP430_REG_PC]);
|
w32le(req + 8, h->regs[MSP430_REG_PC]);
|
||||||
|
|
||||||
|
dbg_printc("do read\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_READ_MEM_BYTES :
|
map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_READ_MEM_BYTES :
|
||||||
HAL_PROTO_FID_READ_MEM_WORDS),
|
HAL_PROTO_FID_READ_MEM_WORDS),
|
||||||
|
@ -332,6 +490,7 @@ static int calibrate_dco(struct v3hil *h, uint8_t max_bcs)
|
||||||
w16le(data, ram->offset);
|
w16le(data, ram->offset);
|
||||||
w16le(data + 2, max_bcs);
|
w16le(data + 2, max_bcs);
|
||||||
|
|
||||||
|
dbg_printc("calibrate dco: get freq\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
|
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
|
||||||
data, 6) < 0)
|
data, 6) < 0)
|
||||||
|
@ -350,6 +509,7 @@ static int calibrate_dco(struct v3hil *h, uint8_t max_bcs)
|
||||||
mem_write[9] = data[2]; /* BCS1 */
|
mem_write[9] = data[2]; /* BCS1 */
|
||||||
mem_write[10] = data[4]; /* BCS2 */
|
mem_write[10] = data[4]; /* BCS2 */
|
||||||
mem_write[11] = 0; /* pad */
|
mem_write[11] = 0; /* pad */
|
||||||
|
dbg_printc("calibrate dco: write\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
|
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
|
||||||
mem_write, 12) < 0) {
|
mem_write, 12) < 0) {
|
||||||
|
@ -378,6 +538,7 @@ static int calibrate_fll(struct v3hil *h)
|
||||||
w16le(data, ram->offset);
|
w16le(data, ram->offset);
|
||||||
w16le(data + 2, 0);
|
w16le(data + 2, 0);
|
||||||
|
|
||||||
|
dbg_printc("calibrate fll: get dco freq\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
|
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
|
||||||
data, 10) < 0)
|
data, 10) < 0)
|
||||||
|
@ -399,6 +560,7 @@ static int calibrate_fll(struct v3hil *h)
|
||||||
mem_write[12] = data[8]; /* FLLCTL1 */
|
mem_write[12] = data[8]; /* FLLCTL1 */
|
||||||
mem_write[13] = 0; /* pad */
|
mem_write[13] = 0; /* pad */
|
||||||
|
|
||||||
|
dbg_printc("calibrate fll: write\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
|
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
|
||||||
mem_write, 14) < 0) {
|
mem_write, 14) < 0) {
|
||||||
|
@ -470,6 +632,7 @@ static int upload_funclet(struct v3hil *h,
|
||||||
for (i = 0; i < n; i++)
|
for (i = 0; i < n; i++)
|
||||||
w16le(data + 8 + i * 2, code[i]);
|
w16le(data + 8 + i * 2, code[i]);
|
||||||
|
|
||||||
|
dbg_printc("upload funclet: %d\n", n);
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_WRITE_MEM_WORDS),
|
map_fid(h, HAL_PROTO_FID_WRITE_MEM_WORDS),
|
||||||
data, n * 2 + 8) < 0) {
|
data, n * 2 + 8) < 0) {
|
||||||
|
@ -503,8 +666,10 @@ static int write_flash(struct v3hil *h, address_t addr,
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
dbg_printc("write flash: calibrate\n");
|
||||||
if (calibrate(h) < 0)
|
if (calibrate(h) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
dbg_printc("write flash: upload funclet\n");
|
||||||
if (upload_funclet(h, ram, f) < 0)
|
if (upload_funclet(h, ram, f) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
|
||||||
|
@ -529,6 +694,7 @@ static int write_flash(struct v3hil *h, address_t addr,
|
||||||
w16le(data + 20, h->cal.cal1);
|
w16le(data + 20, h->cal.cal1);
|
||||||
memcpy(data + 22, mem, size);
|
memcpy(data + 22, mem, size);
|
||||||
|
|
||||||
|
dbg_printc("exec write flash funclet\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
|
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
|
||||||
data, size + 22) < 0) {
|
data, size + 22) < 0) {
|
||||||
|
@ -544,16 +710,24 @@ static int write_ram(struct v3hil *h, const struct chipinfo_memory *m,
|
||||||
address_t addr, const uint8_t *mem, address_t size)
|
address_t addr, const uint8_t *mem, address_t size)
|
||||||
{
|
{
|
||||||
uint8_t data[256];
|
uint8_t data[256];
|
||||||
|
bool fram = false;
|
||||||
|
if (h->chip->features & CHIPINFO_FEATURE_FRAM) {
|
||||||
|
if (!strcmp(m->name, "Main") || !strcmp(m->name, "Info")) {
|
||||||
|
dbg_printc("write ram: to FRAM!\n");
|
||||||
|
fram = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
w32le(data, addr);
|
w32le(data, addr);
|
||||||
w32le(data + 4, (m->bits == 8) ? size : (size >> 1));
|
w32le(data + 4, (m->bits == 8 || fram) ? size : (size >> 1));
|
||||||
|
|
||||||
memcpy(data + 8, mem, size);
|
memcpy(data + 8, mem, size);
|
||||||
|
|
||||||
if (hal_proto_execute(&h->hal,
|
dbg_printc("write ram\n");
|
||||||
map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES
|
hal_proto_fid_t fid = (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES
|
||||||
: HAL_PROTO_FID_WRITE_MEM_WORDS),
|
: HAL_PROTO_FID_WRITE_MEM_WORDS;
|
||||||
data, size + 8) < 0) {
|
if (fram) fid = HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2;
|
||||||
|
if (hal_proto_execute(&h->hal, map_fid(h, fid), data, size + 8) < 0) {
|
||||||
printc_err("v3hil: failed writing %d bytes to 0x%05x\n",
|
printc_err("v3hil: failed writing %d bytes to 0x%05x\n",
|
||||||
size, addr);
|
size, addr);
|
||||||
return -1;
|
return -1;
|
||||||
|
@ -576,9 +750,12 @@ int v3hil_write(struct v3hil *h, address_t addr,
|
||||||
if (size > 128)
|
if (size > 128)
|
||||||
size = 128;
|
size = 128;
|
||||||
|
|
||||||
if (m->type == CHIPINFO_MEMTYPE_FLASH)
|
if (m->type == CHIPINFO_MEMTYPE_FLASH) {
|
||||||
|
dbg_printc("call write flash\n");
|
||||||
return write_flash(h, addr, mem, size);
|
return write_flash(h, addr, mem, size);
|
||||||
|
}
|
||||||
|
|
||||||
|
dbg_printc("call write ram\n");
|
||||||
return write_ram(h, m, addr, mem, size);
|
return write_ram(h, m, addr, mem, size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -603,6 +780,7 @@ static int call_erase(struct v3hil *h,
|
||||||
w16le(data + 20, h->cal.cal1);
|
w16le(data + 20, h->cal.cal1);
|
||||||
w32le(data + 22, 0xdeadbeef);
|
w32le(data + 22, 0xdeadbeef);
|
||||||
|
|
||||||
|
dbg_printc("call erase funclet\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
|
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
|
||||||
data, 26) < 0) {
|
data, 26) < 0) {
|
||||||
|
@ -636,8 +814,10 @@ int v3hil_erase(struct v3hil *h, address_t segment)
|
||||||
if (!flash)
|
if (!flash)
|
||||||
printc_err("v3hil: can't find appropriate flash region\n");
|
printc_err("v3hil: can't find appropriate flash region\n");
|
||||||
|
|
||||||
|
dbg_printc("calibrate\n");
|
||||||
if (calibrate(h) < 0)
|
if (calibrate(h) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
dbg_printc("upload erase funclet\n");
|
||||||
if (upload_funclet(h, ram, f) < 0)
|
if (upload_funclet(h, ram, f) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
|
||||||
|
@ -649,6 +829,7 @@ int v3hil_erase(struct v3hil *h, address_t segment)
|
||||||
bank_size /= flash->banks;
|
bank_size /= flash->banks;
|
||||||
|
|
||||||
for (i = flash->banks; i >= 0; i--)
|
for (i = flash->banks; i >= 0; i--)
|
||||||
|
dbg_printc("Erase bank %d\n", i);
|
||||||
if (call_erase(h, ram, f,
|
if (call_erase(h, ram, f,
|
||||||
flash->offset + i * bank_size - 2, 0xa502) < 0)
|
flash->offset + i * bank_size - 2, 0xa502) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
@ -667,10 +848,13 @@ int v3hil_update_regs(struct v3hil *h)
|
||||||
{
|
{
|
||||||
const hal_proto_fid_t fid =
|
const hal_proto_fid_t fid =
|
||||||
map_fid(h, HAL_PROTO_FID_READ_ALL_CPU_REGS);
|
map_fid(h, HAL_PROTO_FID_READ_ALL_CPU_REGS);
|
||||||
const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS) ? 2 : 3;
|
const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS
|
||||||
|
|| fid == HAL_PROTO_FID_READ_ALL_CPU_REGS - 1)
|
||||||
|
? 2 : 3;
|
||||||
int i;
|
int i;
|
||||||
int sptr = 0;
|
int sptr = 0;
|
||||||
|
|
||||||
|
dbg_printc("Read regs\n");
|
||||||
if (hal_proto_execute(&h->hal, fid, NULL, 0) < 0) {
|
if (hal_proto_execute(&h->hal, fid, NULL, 0) < 0) {
|
||||||
printc_err("v3hil: can't read CPU registers\n");
|
printc_err("v3hil: can't read CPU registers\n");
|
||||||
return -1;
|
return -1;
|
||||||
|
@ -704,7 +888,9 @@ int v3hil_flush_regs(struct v3hil *h)
|
||||||
{
|
{
|
||||||
const hal_proto_fid_t fid =
|
const hal_proto_fid_t fid =
|
||||||
map_fid(h, HAL_PROTO_FID_WRITE_ALL_CPU_REGS);
|
map_fid(h, HAL_PROTO_FID_WRITE_ALL_CPU_REGS);
|
||||||
const int reg_size = (fid == HAL_PROTO_FID_WRITE_ALL_CPU_REGS) ? 2 : 3;
|
const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS
|
||||||
|
|| fid == HAL_PROTO_FID_READ_ALL_CPU_REGS - 1)
|
||||||
|
? 2 : 3;
|
||||||
int i;
|
int i;
|
||||||
int dptr = 0;
|
int dptr = 0;
|
||||||
uint8_t data[64];
|
uint8_t data[64];
|
||||||
|
@ -724,6 +910,7 @@ int v3hil_flush_regs(struct v3hil *h)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
dbg_printc("Write regs\n");
|
||||||
if (hal_proto_execute(&h->hal, fid, data, reg_size * 13) < 0) {
|
if (hal_proto_execute(&h->hal, fid, data, reg_size * 13) < 0) {
|
||||||
printc_err("v3hil: can't write CPU registers\n");
|
printc_err("v3hil: can't write CPU registers\n");
|
||||||
return -1;
|
return -1;
|
||||||
|
@ -747,6 +934,7 @@ int v3hil_context_restore(struct v3hil *h, int free)
|
||||||
data[10] = free ? 7 : 6;
|
data[10] = free ? 7 : 6;
|
||||||
data[14] = free ? 1 : 0;
|
data[14] = free ? 1 : 0;
|
||||||
|
|
||||||
|
dbg_printc("Context restore\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_RC_RELEASE_JTAG),
|
map_fid(h, HAL_PROTO_FID_RC_RELEASE_JTAG),
|
||||||
data, 18) < 0) {
|
data, 18) < 0) {
|
||||||
|
@ -769,6 +957,7 @@ int v3hil_context_save(struct v3hil *h)
|
||||||
data[2] = h->wdtctl | 0x80;
|
data[2] = h->wdtctl | 0x80;
|
||||||
data[3] = 0x5a; /* WDTPW */
|
data[3] = 0x5a; /* WDTPW */
|
||||||
|
|
||||||
|
dbg_printc("Context save\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_SJ_CONDITIONAL_SC),
|
map_fid(h, HAL_PROTO_FID_SJ_CONDITIONAL_SC),
|
||||||
data, 8) < 0)
|
data, 8) < 0)
|
||||||
|
@ -800,6 +989,7 @@ int v3hil_single_step(struct v3hil *h)
|
||||||
data[9] = h->regs[MSP430_REG_SR] >> 8;
|
data[9] = h->regs[MSP430_REG_SR] >> 8;
|
||||||
data[10] = 7;
|
data[10] = 7;
|
||||||
|
|
||||||
|
dbg_printc("Single-stepping...\n");
|
||||||
if (hal_proto_execute(&h->hal,
|
if (hal_proto_execute(&h->hal,
|
||||||
map_fid(h, HAL_PROTO_FID_SINGLE_STEP),
|
map_fid(h, HAL_PROTO_FID_SINGLE_STEP),
|
||||||
data, 18) < 0) {
|
data, 18) < 0) {
|
||||||
|
@ -834,7 +1024,8 @@ static int set_param(struct v3hil *fet, hal_proto_config_t cfg,
|
||||||
}
|
}
|
||||||
|
|
||||||
data[0] = cfg;
|
data[0] = cfg;
|
||||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_CONFIGURE,
|
dbg_printc("Set param 0x%02x to 0x%08x\n", cfg, value);
|
||||||
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_CONFIGURE),
|
||||||
data, 8) < 0) {
|
data, 8) < 0) {
|
||||||
printc_err("v3hil: can't set param 0x%02x to 0x%08x\n",
|
printc_err("v3hil: can't set param 0x%02x to 0x%08x\n",
|
||||||
cfg, value);
|
cfg, value);
|
||||||
|
@ -854,7 +1045,7 @@ static int idproc_89(struct v3hil *fet, uint32_t id_data_addr,
|
||||||
memset(data, 0, 8);
|
memset(data, 0, 8);
|
||||||
w32le(data, id_data_addr);
|
w32le(data, id_data_addr);
|
||||||
data[4] = 8;
|
data[4] = 8;
|
||||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_WORDS,
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_WORDS),
|
||||||
data, 8) < 0)
|
data, 8) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
if (fet->hal.length < 16) {
|
if (fet->hal.length < 16) {
|
||||||
|
@ -870,7 +1061,7 @@ static int idproc_89(struct v3hil *fet, uint32_t id_data_addr,
|
||||||
id->config = fet->hal.payload[13] & 0x7f;
|
id->config = fet->hal.payload[13] & 0x7f;
|
||||||
|
|
||||||
printc_dbg("Read fuses...\n");
|
printc_dbg("Read fuses...\n");
|
||||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_FUSES, NULL, 0) < 0)
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_FUSES), NULL, 0) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
if (!fet->hal.length) {
|
if (!fet->hal.length) {
|
||||||
printc_err("v3hil: short reply: %d\n", fet->hal.length);
|
printc_err("v3hil: short reply: %d\n", fet->hal.length);
|
||||||
|
@ -894,7 +1085,7 @@ static int idproc_9x(struct v3hil *fet, uint32_t dev_id_ptr,
|
||||||
memset(data, 0, 8);
|
memset(data, 0, 8);
|
||||||
w32le(data, dev_id_ptr);
|
w32le(data, dev_id_ptr);
|
||||||
data[4] = 4;
|
data[4] = 4;
|
||||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2,
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_QUICK_XV2),
|
||||||
data, 8) < 0)
|
data, 8) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
if (fet->hal.length < 8) {
|
if (fet->hal.length < 8) {
|
||||||
|
@ -918,7 +1109,7 @@ static int idproc_9x(struct v3hil *fet, uint32_t dev_id_ptr,
|
||||||
w32le(data, dev_id_ptr);
|
w32le(data, dev_id_ptr);
|
||||||
w32le(data + 4, tlv_size >> 1);
|
w32le(data + 4, tlv_size >> 1);
|
||||||
w32le(data + 8, fet->regs[MSP430_REG_PC]);
|
w32le(data + 8, fet->regs[MSP430_REG_PC]);
|
||||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2,
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_QUICK_XV2),
|
||||||
data, 8) < 0)
|
data, 8) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
if (fet->hal.length < tlv_size) {
|
if (fet->hal.length < tlv_size) {
|
||||||
|
@ -952,26 +1143,57 @@ int v3hil_identify(struct v3hil *fet)
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
printc_dbg("Fetching JTAG ID...\n");
|
printc_dbg("Fetching JTAG ID...\n");
|
||||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_JTAG_ID,
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_JTAG_ID),
|
||||||
NULL, 0) < 0)
|
NULL, 0) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
|
||||||
if (fet->hal.length < 12) {
|
#ifdef DEBUG_V3HIL
|
||||||
printc_err("v3hil: short reply: %d\n", fet->hal.length);
|
printc_dbg("v3hil: ID:");
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
printc_dbg("ID:");
|
|
||||||
for (i = 0; i < fet->hal.length; i++)
|
for (i = 0; i < fet->hal.length; i++)
|
||||||
printc_dbg(" %02x", fet->hal.payload[i]);
|
printc_dbg(" %02x", fet->hal.payload[i]);
|
||||||
printc_dbg("\n");
|
printc_dbg("\n");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (fet->hal.length < 12) {
|
||||||
|
if (fet->hal.length == 2) {
|
||||||
|
fet->jtag_id = fet->hal.payload[0];
|
||||||
|
|
||||||
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_DEVICE_ID_PTR),
|
||||||
|
NULL, 0) < 0)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
#ifdef DEBUG_V3HIL
|
||||||
|
dbg_printc("len: %d\n", fet->hal.length);
|
||||||
|
printc_dbg("v3hil: IDPtr:");
|
||||||
|
for (i = 0; i < fet->hal.length; i++)
|
||||||
|
printc_dbg(" %02x", fet->hal.payload[i]);
|
||||||
|
printc_dbg("\n");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (fet->hal.length < 10) {
|
||||||
|
printc_err("v3hil: short reply: %d\n", fet->hal.length);
|
||||||
|
return -1;
|
||||||
|
} else {
|
||||||
|
dev_id_ptr = r32le(fet->hal.payload + 0);
|
||||||
|
|
||||||
|
if (dev_id_ptr == 0) { // welp sometimes it's this instead (JTAG ID == 0x89?)
|
||||||
|
dev_id_ptr = r32le(fet->hal.payload + 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
id_data_addr = dev_id_ptr; // idk
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printc_err("v3hil: short reply: %d\n", fet->hal.length);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
/* Byte at 0 is JTAG ID. 0x91, 0x95, 0x99 means CPUxV2. 0x89
|
/* Byte at 0 is JTAG ID. 0x91, 0x95, 0x99 means CPUxV2. 0x89
|
||||||
* means old CPU.
|
* means old CPU.
|
||||||
*/
|
*/
|
||||||
fet->jtag_id = fet->hal.payload[0];
|
fet->jtag_id = fet->hal.payload[0];
|
||||||
dev_id_ptr = r32le(fet->hal.payload + 4);
|
dev_id_ptr = r32le(fet->hal.payload + 4);
|
||||||
id_data_addr = r32le(fet->hal.payload + 8);
|
id_data_addr = r32le(fet->hal.payload + 8);
|
||||||
|
}
|
||||||
|
|
||||||
/* Pick fail-safe configuration */
|
/* Pick fail-safe configuration */
|
||||||
printc_dbg("Reset parameters...\n");
|
printc_dbg("Reset parameters...\n");
|
||||||
|
@ -982,14 +1204,15 @@ int v3hil_identify(struct v3hil *fet)
|
||||||
set_param(fet, HAL_PROTO_CONFIG_PSA_TCKL_HIGH, 0) < 0 ||
|
set_param(fet, HAL_PROTO_CONFIG_PSA_TCKL_HIGH, 0) < 0 ||
|
||||||
set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG_MASK, 0) < 0 ||
|
set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG_MASK, 0) < 0 ||
|
||||||
set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG3V_MASK, 0) < 0 ||
|
set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG3V_MASK, 0) < 0 ||
|
||||||
set_param(fet, HAL_PROTO_CONFIG_NO_BSL, 0) < 0 ||
|
|
||||||
set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ, 0) < 0)
|
set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ, 0) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
set_param(fet, HAL_PROTO_CONFIG_NO_BSL, 0); // is allowed to fail
|
||||||
|
|
||||||
printc_dbg("Check JTAG fuse...\n");
|
printc_dbg("Check JTAG fuse...\n");
|
||||||
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN,
|
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN),
|
||||||
NULL, 0) < 0)
|
NULL, 0) < 0) {
|
||||||
return -1;
|
return -1;
|
||||||
|
}
|
||||||
if ((fet->hal.length >= 2) &&
|
if ((fet->hal.length >= 2) &&
|
||||||
(fet->hal.payload[0] == 0x55) &&
|
(fet->hal.payload[0] == 0x55) &&
|
||||||
(fet->hal.payload[1] == 0x55)) {
|
(fet->hal.payload[1] == 0x55)) {
|
||||||
|
@ -1056,13 +1279,13 @@ int v3hil_configure(struct v3hil *fet)
|
||||||
fet->chip->power.enable_lpm5_3v) < 0 ||
|
fet->chip->power.enable_lpm5_3v) < 0 ||
|
||||||
set_param(fet, HAL_PROTO_CONFIG_TESTREG3V_DISABLE_LPMX5,
|
set_param(fet, HAL_PROTO_CONFIG_TESTREG3V_DISABLE_LPMX5,
|
||||||
fet->chip->power.disable_lpm5_3v) < 0 ||
|
fet->chip->power.disable_lpm5_3v) < 0 ||
|
||||||
set_param(fet, HAL_PROTO_CONFIG_NO_BSL,
|
|
||||||
(fet->chip->features &
|
|
||||||
CHIPINFO_FEATURE_NO_BSL) ? 1 : 0) < 0 ||
|
|
||||||
set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ,
|
set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ,
|
||||||
(fet->chip->features &
|
(fet->chip->features &
|
||||||
CHIPINFO_FEATURE_1337) ? 1 : 0) < 0)
|
CHIPINFO_FEATURE_1337) ? 1 : 0) < 0)
|
||||||
return -1;
|
return -1;
|
||||||
|
set_param(fet, HAL_PROTO_CONFIG_NO_BSL,
|
||||||
|
(fet->chip->features &
|
||||||
|
CHIPINFO_FEATURE_NO_BSL) ? 1 : 0); // is allowed to fail
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -44,6 +44,9 @@ struct v3hil {
|
||||||
/* Lower 8 bits of saved WDTCTL */
|
/* Lower 8 bits of saved WDTCTL */
|
||||||
uint8_t wdtctl;
|
uint8_t wdtctl;
|
||||||
|
|
||||||
|
/* Is this a v2 or v3 firmware running on the eZ-FET? */
|
||||||
|
uint16_t proto_ver;
|
||||||
|
|
||||||
/* Register cache: this must be flushed before restoring context
|
/* Register cache: this must be flushed before restoring context
|
||||||
* and updated after saving context.
|
* and updated after saving context.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -247,8 +247,10 @@ static int feed_section(struct elf32_info *info,
|
||||||
ch.data = buf;
|
ch.data = buf;
|
||||||
ch.len = len;
|
ch.len = len;
|
||||||
|
|
||||||
if (cb(user_data, &ch) < 0)
|
if (cb(user_data, &ch) < 0) {
|
||||||
|
pr_error("elf32: misc error");
|
||||||
return -1;
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
size -= len;
|
size -= len;
|
||||||
offset += len;
|
offset += len;
|
||||||
|
@ -331,7 +333,7 @@ int elf32_extract(FILE *in, binfile_imgcb_t cb, void *user_data)
|
||||||
Elf32_Shdr *s = &info.file_shdrs[i];
|
Elf32_Shdr *s = &info.file_shdrs[i];
|
||||||
|
|
||||||
if ((s->sh_type == SHT_PROGBITS || s->sh_type == SHT_INIT_ARRAY) &&
|
if ((s->sh_type == SHT_PROGBITS || s->sh_type == SHT_INIT_ARRAY) &&
|
||||||
s->sh_flags & SHF_ALLOC &&
|
(s->sh_flags & SHF_ALLOC) && s->sh_size > 0 &&
|
||||||
feed_section(&info, in, s, cb, user_data) < 0) {
|
feed_section(&info, in, s, cb, user_data) < 0) {
|
||||||
ret = -1;
|
ret = -1;
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -54,7 +54,7 @@ static int addr_exp_data(struct addr_exp_state *s, const char *text)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Hex value */
|
/* Hex value */
|
||||||
if (*text == '0' && text[1] == 'x') {
|
if (*text == '0' && (text[1] == 'x' || text[1] == 'X')) {
|
||||||
value = strtoul(text + 2, NULL, 16);
|
value = strtoul(text + 2, NULL, 16);
|
||||||
} else if (*text == '0' && text[1] == 'd') {
|
} else if (*text == '0' && text[1] == 'd') {
|
||||||
value = atoi(text + 2);
|
value = atoi(text + 2);
|
||||||
|
|
Loading…
Reference in New Issue