2012-06-08 09:56:42 +00:00
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/**
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* @brief NETINFO_ITEM class, to handle info on nets: netnames, net constraints
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*/
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2012 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
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* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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2007-06-05 12:10:51 +00:00
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2012-01-23 04:33:36 +00:00
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#include <fctsys.h>
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#include <gr_basic.h>
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#include <class_drawpanel.h>
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#include <wxBasePcbFrame.h>
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#include <common.h>
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#include <kicad_string.h>
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#include <pcbnew.h>
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#include <colors_selection.h>
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#include <richio.h>
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#include <macros.h>
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2013-01-12 17:32:24 +00:00
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#include <msgpanel.h>
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#include <base_units.h>
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2011-09-23 13:57:12 +00:00
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2012-01-23 04:33:36 +00:00
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#include <class_board.h>
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#include <class_module.h>
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#include <class_track.h>
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2011-09-23 13:57:12 +00:00
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2007-06-05 12:10:51 +00:00
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2007-08-08 03:50:44 +00:00
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/*********************************************************/
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2009-05-25 11:53:55 +00:00
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/* class NETINFO_ITEM: handle data relative to a given net */
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2007-08-08 03:50:44 +00:00
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/*********************************************************/
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2007-06-05 12:10:51 +00:00
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2016-01-29 10:21:13 +00:00
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NETINFO_ITEM::NETINFO_ITEM( BOARD* aParent, const wxString& aNetName, int aNetCode ) :
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BOARD_ITEM( aParent, PCB_NETINFO_T ),
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2014-01-09 14:51:47 +00:00
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m_NetCode( aNetCode ), m_Netname( aNetName ), m_ShortNetname( m_Netname.AfterLast( '/' ) )
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2007-06-05 12:10:51 +00:00
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{
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2013-01-12 17:32:24 +00:00
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m_parent = aParent;
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2009-11-12 15:43:38 +00:00
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m_RatsnestStartIdx = 0; // Starting point of ratsnests of this net in a
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// general buffer of ratsnest
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m_RatsnestEndIdx = 0; // Ending point of ratsnests of this net
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2007-06-05 12:10:51 +00:00
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2012-05-21 18:50:46 +00:00
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m_NetClassName = NETCLASS::Default;
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2009-08-17 02:59:38 +00:00
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}
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2007-06-05 12:10:51 +00:00
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2007-08-08 03:50:44 +00:00
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2009-05-24 18:28:36 +00:00
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NETINFO_ITEM::~NETINFO_ITEM()
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2007-06-05 12:10:51 +00:00
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{
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2009-08-17 02:59:38 +00:00
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// m_NetClass is not owned by me.
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2007-06-05 12:10:51 +00:00
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}
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2007-08-08 03:50:44 +00:00
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2010-11-12 16:36:43 +00:00
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/**
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* Function Draw (TODO)
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2008-12-14 19:45:05 +00:00
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*/
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2011-01-21 19:30:59 +00:00
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void NETINFO_ITEM::Draw( EDA_DRAW_PANEL* panel,
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wxDC* DC,
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2012-09-01 13:38:27 +00:00
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GR_DRAWMODE aDrawMode,
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2011-01-21 19:30:59 +00:00
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const wxPoint& aOffset )
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2008-12-14 19:45:05 +00:00
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{
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2007-10-30 21:30:58 +00:00
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}
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2007-08-09 01:41:30 +00:00
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2013-01-12 17:32:24 +00:00
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void NETINFO_ITEM::GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList )
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2009-05-21 14:59:54 +00:00
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{
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2010-12-08 20:12:46 +00:00
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wxString txt;
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2016-07-11 03:09:18 +00:00
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double lengthnet = 0.0; // This is the length of tracks on pcb
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double lengthPadToDie = 0.0; // this is the length of internal ICs connections
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2009-05-21 14:59:54 +00:00
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2013-01-12 17:32:24 +00:00
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aList.push_back( MSG_PANEL_ITEM( _( "Net Name" ), GetNetname(), RED ) );
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2009-05-21 14:59:54 +00:00
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txt.Printf( wxT( "%d" ), GetNet() );
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2013-01-12 17:32:24 +00:00
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aList.push_back( MSG_PANEL_ITEM( _( "Net Code" ), txt, RED ) );
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2009-05-21 14:59:54 +00:00
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2015-01-23 11:24:32 +00:00
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// Warning: for netcode == NETINFO_LIST::ORPHANED, the parent or the board
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// can be NULL
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BOARD * board = m_parent ? m_parent->GetBoard() : NULL;
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if( board == NULL )
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return;
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2013-01-12 17:32:24 +00:00
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2015-01-23 11:24:32 +00:00
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int count = 0;
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for( MODULE* module = board->m_Modules; module != NULL; module = module->Next() )
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2009-05-21 14:59:54 +00:00
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{
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2015-01-23 11:24:32 +00:00
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for( D_PAD* pad = module->Pads(); pad != 0; pad = pad->Next() )
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2009-05-21 14:59:54 +00:00
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{
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2014-02-25 10:40:34 +00:00
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if( pad->GetNetCode() == GetNet() )
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2011-06-30 06:02:07 +00:00
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{
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2009-05-21 14:59:54 +00:00
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count++;
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2012-12-12 11:57:17 +00:00
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lengthPadToDie += pad->GetPadToDieLength();
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2011-06-30 06:02:07 +00:00
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}
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2009-05-21 14:59:54 +00:00
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}
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}
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txt.Printf( wxT( "%d" ), count );
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2013-01-12 17:32:24 +00:00
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aList.push_back( MSG_PANEL_ITEM( _( "Pads" ), txt, DARKGREEN ) );
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2009-05-21 14:59:54 +00:00
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2009-06-05 15:57:41 +00:00
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count = 0;
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2011-10-01 19:24:27 +00:00
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2015-01-23 11:24:32 +00:00
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for( const TRACK *track = board->m_Track; track != NULL; track = track->Next() )
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2009-05-21 14:59:54 +00:00
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{
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2014-04-25 06:00:04 +00:00
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if( track->Type() == PCB_VIA_T )
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2011-10-01 19:24:27 +00:00
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{
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2014-04-25 06:00:04 +00:00
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if( track->GetNetCode() == GetNet() )
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2009-05-21 14:59:54 +00:00
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count++;
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2011-10-01 19:24:27 +00:00
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}
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2014-04-25 06:00:04 +00:00
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if( track->Type() == PCB_TRACE_T )
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2011-10-01 19:24:27 +00:00
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{
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2014-04-25 06:00:04 +00:00
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if( track->GetNetCode() == GetNet() )
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lengthnet += track->GetLength();
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2011-10-01 19:24:27 +00:00
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}
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2009-05-21 14:59:54 +00:00
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}
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txt.Printf( wxT( "%d" ), count );
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2013-01-12 17:32:24 +00:00
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aList.push_back( MSG_PANEL_ITEM( _( "Vias" ), txt, BLUE ) );
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2009-05-21 14:59:54 +00:00
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2013-01-12 17:32:24 +00:00
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// Displays the full net length (tracks on pcb + internal ICs connections ):
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2014-07-24 17:36:26 +00:00
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txt = ::LengthDoubleToString( lengthnet + lengthPadToDie );
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2014-11-15 19:06:05 +00:00
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aList.push_back( MSG_PANEL_ITEM( _( "Net Length" ), txt, RED ) );
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2011-06-30 06:02:07 +00:00
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2013-01-12 17:32:24 +00:00
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// Displays the net length of tracks only:
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2014-07-24 17:36:26 +00:00
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txt = ::LengthDoubleToString( lengthnet );
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2013-01-12 17:32:24 +00:00
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aList.push_back( MSG_PANEL_ITEM( _( "On Board" ), txt, RED ) );
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2011-06-30 06:02:07 +00:00
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2013-01-12 17:32:24 +00:00
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// Displays the net length of internal ICs connections (wires inside ICs):
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2014-07-24 17:36:26 +00:00
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txt = ::LengthDoubleToString( lengthPadToDie );
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2013-01-12 17:32:24 +00:00
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aList.push_back( MSG_PANEL_ITEM( _( "In Package" ), txt, RED ) );
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2009-05-21 14:59:54 +00:00
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}
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2009-05-25 11:53:55 +00:00
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/***********************/
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/* class RATSNEST_ITEM */
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/***********************/
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2009-06-05 15:57:41 +00:00
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RATSNEST_ITEM::RATSNEST_ITEM()
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{
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2009-11-12 15:43:38 +00:00
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m_NetCode = 0; // netcode ( = 1.. n , 0 is the value used for not
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// connected items)
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2009-06-05 15:57:41 +00:00
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m_Status = 0; // state
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m_PadStart = NULL; // pointer to the starting pad
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m_PadEnd = NULL; // pointer to ending pad
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2016-07-11 03:09:18 +00:00
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m_Length = 0; // length of the line (temporary used in some
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2009-11-12 15:43:38 +00:00
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// calculations)
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2009-06-05 15:57:41 +00:00
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}
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2010-11-12 16:36:43 +00:00
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/**
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* Function Draw
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2009-05-25 14:14:54 +00:00
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* Draws a line (a ratsnest) from the starting pad to the ending pad
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2009-05-25 11:53:55 +00:00
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*/
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2011-01-21 19:30:59 +00:00
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void RATSNEST_ITEM::Draw( EDA_DRAW_PANEL* panel,
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wxDC* DC,
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2012-09-01 13:38:27 +00:00
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GR_DRAWMODE aDrawMode,
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2011-01-21 19:30:59 +00:00
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const wxPoint& aOffset )
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2009-05-25 11:53:55 +00:00
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{
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2010-01-21 20:36:48 +00:00
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GRSetDrawMode( DC, aDrawMode );
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2011-12-10 05:33:24 +00:00
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2017-03-13 03:19:33 +00:00
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COLOR4D color = g_ColorsSettings.GetItemColor( LAYER_RATSNEST );
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2011-12-10 05:33:24 +00:00
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2012-02-19 04:02:19 +00:00
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GRLine( panel->GetClipBox(), DC,
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m_PadStart->GetPosition() - aOffset,
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m_PadEnd->GetPosition() - aOffset, 0, color );
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2009-05-25 11:53:55 +00:00
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}
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