kicad/pcbnew/netinfo_item.cpp

152 lines
4.7 KiB
C++
Raw Normal View History

/**
* @brief NETINFO_ITEM class, to handle info on nets: netnames, net constraints
*/
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2012 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <fctsys.h>
#include <gr_basic.h>
2018-01-29 15:39:40 +00:00
#include <pcb_base_frame.h>
#include <common.h>
#include <kicad_string.h>
#include <pcbnew.h>
#include <richio.h>
#include <macros.h>
#include <msgpanel.h>
#include <base_units.h>
#include <class_board.h>
#include <class_module.h>
#include <class_track.h>
2007-08-08 03:50:44 +00:00
/*********************************************************/
/* class NETINFO_ITEM: handle data relative to a given net */
2007-08-08 03:50:44 +00:00
/*********************************************************/
NETINFO_ITEM::NETINFO_ITEM( BOARD* aParent, const wxString& aNetName, int aNetCode ) :
BOARD_ITEM( aParent, PCB_NETINFO_T ),
m_NetCode( aNetCode ),
m_isCurrent( true ),
m_Netname( aNetName ),
m_ShortNetname( m_Netname.AfterLast( '/' ) )
{
m_parent = aParent;
if( aParent )
m_NetClass = aParent->GetDesignSettings().m_NetClasses.GetDefault();
else
m_NetClass = std::make_shared<NETCLASS>( "<invalid>" );
2009-08-17 02:59:38 +00:00
}
2007-08-08 03:50:44 +00:00
NETINFO_ITEM::~NETINFO_ITEM()
{
2009-08-17 02:59:38 +00:00
// m_NetClass is not owned by me.
}
2007-08-08 03:50:44 +00:00
/**
* Function Print (TODO)
*/
void NETINFO_ITEM::Print( PCB_BASE_FRAME* frame, wxDC* DC, const wxPoint& aOffset )
{
2007-10-30 21:30:58 +00:00
}
2007-08-09 01:41:30 +00:00
void NETINFO_ITEM::SetClass( const NETCLASSPTR& aNetClass )
{
wxCHECK( m_parent, /* void */ );
m_NetClass = aNetClass ? aNetClass : m_parent->GetDesignSettings().m_NetClasses.GetDefault();
}
void NETINFO_ITEM::GetMsgPanelInfo( EDA_UNITS_T aUnits, std::vector< MSG_PANEL_ITEM >& aList )
2009-05-21 14:59:54 +00:00
{
wxString txt;
2016-07-11 03:09:18 +00:00
double lengthnet = 0.0; // This is the length of tracks on pcb
double lengthPadToDie = 0.0; // this is the length of internal ICs connections
2009-05-21 14:59:54 +00:00
aList.push_back( MSG_PANEL_ITEM( _( "Net Name" ), GetNetname(), RED ) );
2009-05-21 14:59:54 +00:00
txt.Printf( wxT( "%d" ), GetNet() );
aList.push_back( MSG_PANEL_ITEM( _( "Net Code" ), txt, RED ) );
2009-05-21 14:59:54 +00:00
// Warning: for netcode == NETINFO_LIST::ORPHANED, the parent or the board
// can be NULL
BOARD * board = m_parent ? m_parent->GetBoard() : NULL;
if( board == NULL )
return;
int count = 0;
for( auto mod : board->Modules() )
2009-05-21 14:59:54 +00:00
{
for( auto pad : mod->Pads() )
2009-05-21 14:59:54 +00:00
{
if( pad->GetNetCode() == GetNet() )
{
2009-05-21 14:59:54 +00:00
count++;
lengthPadToDie += pad->GetPadToDieLength();
}
2009-05-21 14:59:54 +00:00
}
}
txt.Printf( wxT( "%d" ), count );
aList.push_back( MSG_PANEL_ITEM( _( "Pads" ), txt, DARKGREEN ) );
2009-05-21 14:59:54 +00:00
count = 0;
for( const TRACK *track = board->m_Track; track != NULL; track = track->Next() )
2009-05-21 14:59:54 +00:00
{
if( track->Type() == PCB_VIA_T )
{
if( track->GetNetCode() == GetNet() )
2009-05-21 14:59:54 +00:00
count++;
}
if( track->Type() == PCB_TRACE_T )
{
if( track->GetNetCode() == GetNet() )
lengthnet += track->GetLength();
}
2009-05-21 14:59:54 +00:00
}
txt.Printf( wxT( "%d" ), count );
aList.push_back( MSG_PANEL_ITEM( _( "Vias" ), txt, BLUE ) );
2009-05-21 14:59:54 +00:00
// Displays the full net length (tracks on pcb + internal ICs connections ):
txt = MessageTextFromValue( aUnits, lengthnet + lengthPadToDie );
aList.push_back( MSG_PANEL_ITEM( _( "Net Length" ), txt, RED ) );
// Displays the net length of tracks only:
txt = MessageTextFromValue( aUnits, lengthnet );
aList.push_back( MSG_PANEL_ITEM( _( "On Board" ), txt, RED ) );
// Displays the net length of internal ICs connections (wires inside ICs):
txt = MessageTextFromValue( aUnits, lengthPadToDie, true );
aList.push_back( MSG_PANEL_ITEM( _( "In Package" ), txt, RED ) );
}