f61d400d88
Allow non-identical schematic/pcb nets
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The schematic net names are fully unique but if we have multiple pads
that are mapped to a NC pin, they need to have unique net names so that
they do not get connected to each other in the ratsnest. This breaks
the schematic parity check as we have modified the netname for some
pads. To work around this, we first maintain the zero-th net without
suffix and then add an additional check in DRC to ensure that we allow
unconnected nets as long as the share a common prefix with the schematic
netname.
2024-04-15 17:54:44 -07:00
a9f35ba42e
Fix incremental connectivity
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The connectivity routine would consider symbols, overwriting unused
subgraphs for pins that were not in the change list. This is resolved
by updating the full connectivity to only use pins in the graph since
symbols are not connected independently.
In the process of adding QA tests for this change, additional issues
with the schematic QA were discovered. Specifically, we were not
properly setting the root sheet UUID. This was partially masked by a
const_cast setting of the RefDes in sch_symbol when called the RefDes
getter. This exposed the fact that our QA ERC numbers did not match the
schematic editor stand alone ERC numbers. So the test value for one
check needed to be updated
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17528
2024-04-10 17:25:58 -07:00
1dbe78c68b
Add QA tests and expand serialization for API
2024-04-02 19:51:18 -04:00
553e4a25bf
Tidy up some remaining triangulation cases
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Found and fixed a few corner cases where triangulation point removal
could reset expected points
2024-04-01 11:48:12 -07:00
c3f6a84d66
Update triangulation to handle poly-intersection
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Polygon intersections happen against the original outline, not against
the currently remaining polygon. This avoids pathalogical cases
Adds new simplification system to avoid duplicated points
Adds new edge-splitting algorithm to provide additional fall-back
Verifies that polygon cuts do not swap holes for outlines (negative
area)
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17559
2024-03-28 10:16:24 -07:00
6b915049d1
Check singular arcs connection
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Even if there are no other segments in the line chain, we still should
check for arc connections in cases of individual arcs on a line chain
2024-03-22 10:41:42 -07:00
543343b7d1
prettifier: add newlines to golden samples
2024-03-18 16:03:09 -04:00
2311eed08a
Add new ERC rule to check for global labels with only one entry in the schematic
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By default this rule is set to ignore to provide continuity for those using
single global labels to name nets (e.g. in simulation)
Fixes https://gitlab.com/kicad/code/kicad/-/issues/13212
2024-03-17 23:24:43 +00:00
96ea1f6f89
Revert change to prettifier QA data
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The file format should not be bumped in these test cases, they are not a test of the file format writer.
2024-02-25 12:50:44 -05:00
ee3be0802c
Move PCBNew overrides to nullable properties.
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/5562
2024-02-24 20:05:51 +00:00
27c253780d
Separate out Pad_Shape so auto-complete can work.
2024-01-10 19:22:05 +00:00
104aa1abe4
Change prettifier QA to not depend on file format changes
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Instead of writing out and reading back in using the plugin,
just test the formatter itself.
Also add support for testing full boards.
2024-01-01 13:38:16 -05:00
58b7eda47a
QA test( test_prettifier) update golden files and fix a warning message.
2024-01-01 10:57:32 +01:00
751c88ef20
Use 'uuid' (not 'id') in the s-expr PCB groups/generator format
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Add some regression tests to check loading of groups and generators
from various versions of the s-expr PCB format.
2023-12-31 23:09:26 +00:00
ea0673e7a0
Do not merge buses of distinct types
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Previously, this code would merge a vector bus
with a group bus containing the vector as a member.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/16439
2023-12-30 10:54:24 -05:00
2ecf1ac23f
Change regression test for #13162 to be less complex
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We are really only testing that `Rload1` works,
and the original testcase is unstable on some platforms.
2023-12-29 13:18:46 -05:00
d8b47d18d3
Initial rename of file plugin infrastructure components to IO
2023-12-24 01:22:21 +00:00
8e647c24b4
QA test, prettifier: Update golden files to the latest version.
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Add also a warning when a golden file is too old and creates comparison error.
2023-12-16 10:49:23 +01:00
e41f5efb03
Use modern bool style for footprint locking (locked yes)
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Add some simple tests for specific footprint load/save checks
(including round-trip stability)
2023-12-14 21:22:59 +00:00
481fa1f959
Allow PCB reference image locking and UUID to be saved
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Add some unit tests for reference image saving/loading.
Fixes: https://gitlab.com/kicad/code/kicad/-/issues/16334
2023-12-14 21:22:59 +00:00
343828c552
Fix invalid string compare in IBIS parser
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strcmp returns 0 if strings are the same but compareIbisWord returns
True (1).
Adds an IBIS simulation QA test case to catch this in the future
Fixes https://gitlab.com/kicad/code/kicad/-/issues/16223
(cherry picked from commit ef8b6bf9e1
2023-11-30 09:16:38 -08:00
ae66ce68b5
Update testcases for generator_version
2023-11-29 16:17:41 +00:00
f1f8981395
Automatic whitespace and indentation prettification for sexpr formats
2023-11-29 16:17:41 +00:00
9e48b388fe
Add additional QA sliver check
2023-11-28 16:02:39 -08:00
75c6b0ab28
Added IPC2581 support
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IPC2581 is a modern production file exchange system. It provides
single-file data output for an entire board including BOM and netlist
information.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/1954
2023-11-26 15:30:58 -08:00
9f0d409982
Missing files from last commit.
2023-11-12 14:33:47 +00:00
fe46fafa98
Add regression test for previous hier label issue
2023-11-09 06:20:52 -08:00
09f1df6c94
CADSTAR Parts: Add QA test for +N0 root with no parts
2023-11-08 22:53:14 +01:00
a6b517147e
QA: update Tracks.pretty
2023-11-06 17:16:16 +03:00
de0736863b
Allow multiple strong drivers with same name
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Multiple labels with the same name are allowed (and expected) so ensure
that we use a structure that allows duplicate names
2023-10-31 11:52:29 -07:00
1a7cc88b97
Add (failing) QA test for #16003
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Also remove old test_netlists.cpp that should have been removed long ago
2023-10-31 12:57:14 -04:00
6e4473855b
QA: update golden files for EAGLE SparkFun-GPS.lbr
2023-10-15 03:28:25 +03:00
6f9af10912
DbLib: support columns with numeric data
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/15662
2023-09-16 22:37:12 -04:00
cb1231382f
Fix connectivity regression
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We have a break somewhere in the connectivity that doesn't fully process
connections but the current code seems to catch these by forcing a
top-down & bottom-up calculation
Fixes https://gitlab.com/kicad/code/kicad/-/issues/14818
2023-09-14 14:39:51 -07:00
f49125da31
QA: Add kicad-cli pcb export gerber tests
2023-09-13 17:37:26 +00:00
e6f0a3d91b
QA: add test files for EasyEDA.
2023-09-07 11:02:40 +03:00
41e274684c
Make sure pads with no net get assigned Default netclass on board open.
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/15562
2023-09-02 10:11:38 +01:00
e118d2fca0
DbLib: Map multiple footprints to footprint filter list
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/13587
2023-08-23 19:16:49 -04:00
c2a91caacf
altium: verify that file contains "Compound File Binary Format" magic bytes, as we do not support the ASCII format
2023-08-18 14:47:08 +02:00
f2a8c25084
Update Eagle gold files for spoke angle fixes.
2023-08-16 23:21:18 +01:00
8d5ebf5e30
QA: Add dummy board files (should fail header checks)
2023-08-15 05:26:12 +03:00
fb3e8ef8f1
QA: Add example P-CAD file
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Supplied by evanshultz in gitlab issue 3993
2023-08-15 05:26:12 +03:00
0b0c50471a
QA: Add example KiCad legacy PCB files
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legacy_demos based on commit e4fdce4a47
2023-08-15 05:26:12 +03:00
1c95762534
QA: Add example EAGLE PCB file - Adafruit-AHT20-PCB
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Source: https://github.com/adafruit/Adafruit-AHT20-PCB
2023-08-15 05:26:12 +03:00
87959a4625
QA: Add simple CADSTAR PCB file
2023-08-15 05:26:12 +03:00
1cbef0157d
Avoid edge cases on very wide thermal spokes.
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/15280
2023-08-04 15:38:06 +01:00
44ff2f4858
Enable legacy .brd zone fill qa test + fix golden files
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Use 0.020mm pen thickness for SVG golden file (generated with build 2013-07-07 BZR 4022)
2023-08-03 15:36:19 +02:00
f00a68576e
Add qa test for legacy (< v5) zone fills
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Disable tests for .brd (legacy file format) fill for now.
2023-07-30 20:56:27 +02:00
d5fc2b757d
qa_cli: increase to 1200dpi + use 1 pixel erosion in comparisons to golden sample
2023-07-27 00:21:48 +02:00
96a34e5b57
Consolidate Maximum clearance calculation
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We were calculating the same thing in three locations and we missed
adding the clearance from the footprints in, resulting in bad fills and
missed drc errors (see QA addition)
2023-07-26 12:55:48 -07:00
Seth Hillbrand
Jon Evans
Mike Williams
JamesJ
Jeff Young
jean-pierre charras
John Beard
Ian McInerney
Roberto Fernandez Bautista
Alex Shvartzkop
Thomas Pointhuber