Commit Graph

220 Commits

Author SHA1 Message Date
jean-pierre charras a343cd0a24 Try to fix a QA issue (disable useless DRC tests for 2 boards) 2023-07-23 13:08:59 +02:00
Seth Hillbrand b827073b3f Update one more board to deal with changed default net clearance 2023-07-19 17:30:48 -07:00
Seth Hillbrand 45ed38a63b Update qa tests to use new zone fill algo 2023-07-19 16:13:49 -07:00
Marek Roszko c009328c07 Undo accidental commit from some time ago (woops) 2023-07-16 21:54:09 -04:00
Seth Hillbrand 998e749918 Move some DRC regression tests
The RegressionZoneFillTests handle issues that are resolved by the zone
filler, so Clipper2 problematic fill belongs there.  Otherwise, the
remaining tests should not refill the zones before running DRC because
we expect the DRC to catch errors without needing a refill
2023-07-07 11:52:25 -07:00
Seth Hillbrand 954b265839 Check for zone-zone overlap
Instead of just checking for the zone outline, we adjust to check the
full fill area of the zones for intersection and overlaps
2023-07-07 11:52:25 -07:00
Jeff Young dd83217062 Add DRC testing for copper graphic to zone fill collisions. 2023-06-30 14:04:20 +01:00
Seth Hillbrand cef4b72b89 Remove image-diff from QA
Re-enable tests for Ubuntu.

This implements a custom image diff function that checks for image
changes in plotted output.
2023-06-12 16:11:10 -07:00
Seth Hillbrand 4bc0822733 Connectivity: Correct alias-based bus resolution
Aliases in bus resolution were being resolved without a path, making
them effectively global nets.  This applies the corrected path to the
bus members and adds a QA to catch this error
2023-06-02 14:25:51 -07:00
jean-pierre charras 86abfd2cef Update a golden file in Eagle QA tests 2023-05-31 11:52:50 +02:00
Roberto Fernandez Bautista bb90aa24b7 Add basic QA test to CADSTAR PCB footprint import 2023-05-29 23:29:28 +02:00
Seth Hillbrand 6a0f64b5a4 Update golden QA images with fixed stroke font output
QA images were generated with v7 output location.  This needs to update
to use the v6 locations
2023-05-12 12:40:41 -07:00
Seth Hillbrand 6e4de18e15 Ensure _changed_ netlist is propagated
The propagation is currently (maybe not needed) limited to the global
name that is the source of the change.  We also need to propagate the
global name that is changed in case the global is set in a tree leaf and
not the root

Fixes https://gitlab.com/kicad/code/kicad/issues/14657
2023-05-09 12:13:06 -07:00
Jeff Young 8bd21edd8a Fix capitalization of text vars for Eagle importer.
Also fixes the test gold files to expect the correct variable
references.
2023-05-06 23:49:10 +01:00
Mark Roszko 112aa66be5 Changes to get cli testing in CI and other test fixes 2023-05-05 20:16:19 -04:00
Marek Roszko 2a222706df Start adding cli qa 2023-05-02 23:23:13 -04:00
Seth Hillbrand f7f52d77e4 Rework Copper Sliver check
Adds QA checks to copper sliver tests.  Adds the following checks:
- Dot product between two arms (quickly avoids checks for >90°)
- Checks the sliver is convex (area test)
- Eliminates minor slivers with angles that are approximately 0 and ones
  with the opposite side width beneath a configurable level
- Updates Clipper2 to fix a couple of jagged edges on inflate
- Adds simplify during zone fill inflation to limit jaggies

Fixes https://gitlab.com/kicad/code/kicad/issues/14549
2023-04-25 10:32:46 -07:00
Seth Hillbrand 012737593b Handle nested netclass assignments
Netclass directives should not be overriden, instead hold our error
checking for actually missing nets

Fixes https://gitlab.com/kicad/code/kicad/issues/14494
2023-04-06 17:38:13 -07:00
Seth Hillbrand 16b4ec3c7e Allow bus elements to connect
Previously, bus elements that were not instantiated as individual nets
could not connect to each other.  This caused issues for complex
schematics where busses needed to connect to other busses with elements
that resolved to the same net names.  Functionally, this means mixing
bus elements, which we will replace with first-class elements in version
8 but currently can only be accomplished either by using bus aliases and
  this patch or by individually instantiating each bus element as a
local label

Fixes https://gitlab.com/kicad/code/kicad/issues/14300
2023-04-04 15:23:29 -07:00
Jeff Young 30b3645e60 Add regression test for 14412. 2023-03-25 16:13:45 +00:00
Jeff Young 35ca3e7264 Add regression test for 13988. 2023-03-25 12:45:36 +00:00
Jeff Young e65a58b823 Add regression test for 14334. 2023-03-25 12:45:36 +00:00
Seth Hillbrand 8150deec32 Add QA test for Clipper2 fill 2023-03-22 15:24:46 -07:00
Seth Hillbrand 914b5a4d21 Simplify test for substantial nubs
Substantial elements following a divot should be at least as far in each
cardinal direction from the origin point in order to be considered
substantial.  This catches cases where the "substantial" element is
actually a straight segment away from the divot

Fixes https://gitlab.com/kicad/code/kicad/issues/14130
2023-03-22 13:01:50 -07:00
Roberto Fernandez Bautista f45ab30fa6 Add parsing for symbols and pins (Parser now complete) 2023-03-16 21:07:05 +01:00
Roberto Fernandez Bautista 379e3b2fbb Add CADSTAR Parts Library (.lib) parser and qa tests 2023-03-16 21:07:04 +01:00
Seth Hillbrand 7653a2bf99 Smarten connection width checker looking for splits
Fractured polygons are always fractured along the x-axis, so when
checking to see if a segment is a fracture point, we check if the y
coordinate is equal.  This avoids situations where there are multiple
fracture points between two inflection points

Additionally, we add a second check to ensure we don't hit spurious
blobs (all kinks should be symmetric and therefore be substantial in
each direction)

Fixes https://gitlab.com/kicad/code/kicad/issues/14130
2023-03-06 16:14:34 -08:00
Jeff Young d96598c87c Add 12505 to the regression test suite.
Fixes https://gitlab.com/kicad/code/kicad/issues/12505
2023-03-06 10:26:59 +00:00
JamesJCode 9dca70a773 Eeschema netlist output: Propagate NC across hierarchical schematics
Fixes #12580

Additionally does not export no_connect netlist annotation on pins
which are both connected to another pin and a NC item, unless all
connected pins are stacked at the symbol level.

Adds testing of pin types to netlist QA unit tests.
2023-02-25 00:02:46 +00:00
Mike Williams 959a19a461 Power Symbols: automatically fix mismatched legacy symbols, add tests
Has netlist generation test for legacy power symbols, and test for
fixing legacy mismatched power symbol text fields and invisible pin names.
2023-02-22 18:01:47 +00:00
jean-pierre charras 07f79208b9 Minor fixes: Coverity and compil minor warnings. 2023-02-18 13:04:43 +01:00
Jeff Young 5c45b53f88 Rollback testing changes that were accidentally checked in. 2023-02-11 21:11:07 +00:00
Jeff Young bc108023b3 ADDED operating point overlay for SCH_EDIT_FRAME.
Fixes https://gitlab.com/kicad/code/kicad/issues/11253
2023-02-11 21:11:07 +00:00
Jeff Young 2a5bb71fbd ADDED operating point text variables for labels and symbols.
ADDED formatting for cursors and operationg points

Also fixes a bunch of bugs to make the new cursors work with .ac sims.

Fixes https://gitlab.com/kicad/code/kicad/issues/11253

Fixes https://gitlab.com/kicad/code/kicad/issues/6965
2023-02-11 21:11:07 +00:00
Jon Evans e066454c61 Zones: use metric defaults and limits instead of mixed units
Update testcases to reflect new defaults
2023-02-11 07:39:29 -05:00
Jeff Young 9ca539b416 Remove TL072.031 from regression test. 2023-01-31 14:57:52 +00:00
Jon Evans 675b6b5d5c Fix logic error in ec4d377d
Also fixup goldens for importers for new default island mode
2023-01-27 10:16:56 -05:00
JamesJCode fef3274e8e Eeschema: ERC checks handle connections between a common sub-circuit
Fixes #10926

Contains the following changes:

    - Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
      comparison between items causing ERC violations (e.g. pins) when associated
      with a SCH_SHEET_PATH context.

    - Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
      which caused an ERC violation. This allows correct display of markers on the
      sheets of interest only, and allows correct naming resolution and cross-probing
      from the ERC dialog.

    - Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
      resolves component references across heirarchical sheets using the associated
      SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
      correctly in the ERC results tree.

    - Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
      an ERC violation.

    - Increments the schematic file version.

    - When loading a schematic with legacy ERC exclusions, discards those of type
      ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
      ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
      information which is now stored with these exclusions (sheet paths for error
      location and related items). Requiring users to (once) re-add exclusions is
      preferable to silently incorrectly matching new ERC issues to legacy exclusions.
2023-01-24 14:11:01 +00:00
jean-pierre charras f6d9a2574b Fix a QA simulation test on W1/msys2:
- Gives a bigger relative tolerance when comparing 2 values to pass some tests
- Fix error in test_sim_regressions.cpp for 3 TestNetlist() calls
2023-01-22 16:52:11 +01:00
Jeff Young 241dc0d96b Add SPICE regression test. 2023-01-21 19:32:25 +00:00
Jeff Young 259e382041 Add simulation regression test for legacy fixups. 2023-01-21 19:32:25 +00:00
Jeff Young e218c7109b Test case for immediate SBCKT models. 2023-01-21 19:32:25 +00:00
Jeff Young 6053b86a24 Add new spice regression test for windows path separators. 2023-01-21 19:32:25 +00:00
Seth Hillbrand fc86998bf6 Ensure duplicate pin names get unique nets
Same pin name != same net name unless the pins are explicitly connected

Also add pin number to all unconnected pads ensuring they have unique
nets

Fixes https://gitlab.com/kicad/code/kicad/issues/13236
2023-01-04 11:32:15 -08:00
Jeff Young a3a2e2e5b1 Update demos and legacy qa files SpiceMapping -> Spice_Node_Sequence.
Also removes migration in the code as it will no longer be needed.
2022-12-19 12:04:53 +00:00
Seth Hillbrand ba11de6e66 Update QA test schematics with valid and invalid variants 2022-12-09 02:14:05 +00:00
Barabas Raffai 63da407345 Add tests for no connect flag 2022-12-09 02:14:05 +00:00
Mikolaj Wielgus b025b103de Sim Model Editor: Make the VBIC model the first BJT model to select 2022-11-29 10:13:20 +01:00
Mikolaj Wielgus 484620eeb5 Sim QA: Add test for VDMOS 2022-11-29 09:48:01 +01:00
Mikolaj Wielgus 5fb191e4d6 Sim QA: Test all BJT parameters in each model 2022-11-28 09:49:48 +01:00
Mikolaj Wielgus 26644952a4 Sim QA: Test all diode parameters 2022-11-28 08:01:50 +01:00
Mikolaj Wielgus f2fb734e06 Sim QA: Add test for Numparam expressions inside .subckt 2022-11-27 06:32:17 +01:00
Mikolaj Wielgus 08d37d2795 Sim QA: Add Spice .subckt parsing tests 2022-11-26 10:24:11 +01:00
Mikolaj Wielgus 9766351ee6 Sim: Update QA to tests to match the new model upgrade scheme 2022-11-25 05:38:21 +01:00
Mikolaj Wielgus 833146cf50 Sim QA: Fix QA errors
Let's not allow units in fields for now. (is 1m one meter or one milli?)
2022-11-22 21:18:01 +01:00
Mikolaj Wielgus e9fe59a28c Sim: Rename the missed Sim_* fields to Sim.* 2022-11-21 03:33:11 +01:00
Mikolaj Wielgus 059ca8fc48 Sim: Rename Sim_* fields to Sim.* 2022-11-20 03:37:54 +01:00
Tomasz Wlostowski cab5f65685 qa/pns: added test case for via drag walkaround 2022-11-18 15:14:34 +01:00
Mikolaj Wielgus e7c43ca20a Sim: Remove inference from Reference and Value 2022-11-18 08:39:15 +01:00
Tomasz Wlostowski 33594e92fa router: qa test case for backspace (unfix) regression 2022-11-15 23:05:53 +01:00
Jon Evans c07477b94c Move to explicit symbol properties mapping
Fixes https://gitlab.com/kicad/code/kicad/-/issues/12845
2022-11-08 22:19:08 -05:00
Tomasz Wlostowski ab350cbfaa qa: some trivial test cases for the P&S regressions 2022-10-31 11:49:31 +01:00
Mikolaj Wielgus 5eca8dd8de Undo hardcoding swapping of diode pins
Revert commits d1e2acd3 70b4d1aa cff508fb
2022-10-30 11:01:59 +01:00
Mikolaj Wielgus cff508fb3b Sim: Reverse diode model pin order to match diode symbols 2022-10-28 14:01:09 +02:00
Mikolaj Wielgus f31feaac42 Sim: Commit forgotten files 2022-10-27 08:08:14 +02:00
Mikolaj Wielgus 00c04e74ed Sim QA: Test LTspice parameters and ako models of BJTs 2022-10-20 04:00:33 +02:00
Mikolaj Wielgus c4fc9c1b16 Sim QA: Add tests for AKO and LTspice diodes 2022-10-19 06:56:21 +02:00
Mikolaj Wielgus 42acabb5a9 Fix a mistake in uopamp.lib.spice 2022-10-18 22:38:49 +02:00
Mikolaj Wielgus ae671c07e1 Commit missing uopamp.lib.spice 2022-10-18 17:38:23 +02:00
Mikolaj Wielgus e5704d7058 Update uopamp.lib.spice to be the same in all QA tests 2022-10-18 06:15:54 +02:00
Mikolaj Wielgus c8e13813d9 Sim: Rename Sim_Disabled field to Sim_Enable 2022-10-16 00:49:44 +02:00
Mikolaj Wielgus c3d5b3b3e5 Sim: Only store device type in reference, not full model type
Instead of Reference="VSIN1", Value="dc=1 ampl=2 f=3", it's now
Reference="V1", Value="SIN dc=1 ampl=2 f=3".
2022-10-15 19:36:26 +02:00
Jeff Young 9424b166d0 Add regression test case for 12609. 2022-10-09 23:31:26 +01:00
Seth Hillbrand 0150655ed3 Fix missing DRC check with via
When the via is first and not second in our ordering, the hole-copper
clearance was not checked as the track did not have a hole.

We also calculated the NPTH-via clearance incorrectly in the inspector
2022-09-20 13:43:01 -07:00
Seth Hillbrand 60374daa49 Fix ERC global label unit tests
Need to test all units in the subgraph as there are chances that the
subgraph might have more than one label, which needs to be consistently
handled
2022-09-12 13:16:45 -07:00
Mikolaj Wielgus 0e0d1a34f5 Sim: Spice grammar fixes
- Fix parsing .model lines with model names containingnon-alphanumeric
  characters like - and _,
- Fix parsing libraries in which EOF is not preceded by a newline.

Fixes https://gitlab.com/kicad/code/kicad/issues/12394
2022-09-12 04:05:17 +02:00
Mikolaj Wielgus e56635a02b Sim: Add mutual inductor model 2022-09-11 19:23:01 +02:00
Seth Hillbrand f2e3329617 Add ERC QA tests 2022-09-09 17:21:57 -07:00
Jon Evans a5246a6df7 DbLib: Support showing field names 2022-09-04 13:01:32 -04:00
Mikolaj Wielgus b225e53135 Sim QA: Test raw model with fewer pins than its symbol 2022-09-02 16:42:15 +02:00
Mikolaj Wielgus 121fad63ab Sim QA: Add Directives test
This test checks whether Spice directives placed in schematics as text
objects are properly included in the generated Spice netlist.
2022-08-31 09:41:35 +02:00
Mikolaj Wielgus bd6c153ad9 Sim: Implement "enum" model parameters for switches
Displayed in Sim Model Dialog parameter grid as a dropdown
(wxEnumProperty).
2022-08-30 09:45:49 +02:00
Mikolaj Wielgus 385e5deaaa Add Switches sim QA test
Tests voltage switches. Current switches will be tested as well once
they're fixed to work with .probe alli command in Ngspice.
2022-08-29 04:30:21 +02:00
Jon Evans ae6a2a6443 ADDED: Database libraries MVP
Allows placing parts from an external database that reference symbols from another loaded library.

Includes:
- nanodbc wrapper
- database schematic library plugin
- basic tests

Fixes https://gitlab.com/kicad/code/kicad/-/issues/7436
2022-08-26 10:51:13 -04:00
Mikolaj Wielgus 103b8a0d2c Update the Opamp test to use a symbol with unordered pins 2022-08-26 04:36:48 +02:00
Mikolaj Wielgus c6defadb78 Add Fliege filter Spice netlist exporter test
Which we use to test multi-part symbols, as Fliege filter has two op
amps.
2022-08-25 08:47:31 +02:00
Mikolaj Wielgus 8a6a0ff7dc Allow inferred voltage/current sources to have a single float in Value
Update Opamp test to use this feature.
2022-08-24 06:19:38 +02:00
Seth Hillbrand b9461f2ba7 Re-enable tests for zones
Avoid invalid substantial checks triggered by signed floating point
zeros.  Adds a QA check to ensure zone-self checks are maintained
2022-08-18 17:06:29 -07:00
Mikolaj Wielgus b6f6d1ef81 Sim QA: Add legacy_opamp test to check legacy subckt fields
In particular, Spice_Node_Sequence needed some additional coverage.
2022-08-11 21:23:05 +02:00
Mikolaj Wielgus c669d55eb8 Sim QA: Use uopamp_lvl2 instead of uopamp_lvl1 in Opamp test 2022-08-11 18:32:20 +02:00
jean-pierre charras cc1e99ff5d QA test: annotate rlc.kicad_sch. only annotated schematic give reliable result. 2022-08-10 11:16:07 +02:00
Mikolaj Wielgus 128fedec1a Sim QA: Commit the missing rlc unit test project 2022-08-08 22:05:15 +02:00
Mikolaj Wielgus f6771ed789 Sim QA: Add rlc project to test RLC ideal model inference 2022-08-08 17:06:50 +02:00
Mikolaj Wielgus 9e7bc585ef Sim QA: Test only specific hardcoded points of the results
We don't want to assume Ngspice results to be very deterministic.
2022-08-04 21:07:43 +02:00
Mikolaj Wielgus 800b512fe8 Further cut off digits down to one after period in sim QA
We just want to make sure our netlist exporter works. Being
deterministic is the simulator's job, not ours, though perhaps we should
investigate that too eventually.
2022-08-03 16:25:00 +02:00
Mikolaj Wielgus 37209bb496 Try to fix Ngspice QA by resampling and cutting off value digits
`linearize` command resamples the data. Fourth and further digits from
decimal point are cut off by using `wrdata` command instead of `write`.
Oddly, "sources" unit test is not working (so it's still uncommented) --
some substantially different values are generated when generating the
reference with standalone Ngspice.
2022-08-03 14:28:01 +02:00
Jeff Young cc78997386 Add annular ring test and fix footprint/pad mismatch in other test. 2022-08-01 21:50:35 +01:00
Jeff Young 203d778c92 Fix test failure. 2022-08-01 21:42:02 +01:00
Jeff Young 0304ad4494 Move connection width testing to rule system.
Also copies connection width progress reporting architecture over to
the sliver checker.
2022-08-01 13:09:51 +01:00
Mikolaj Wielgus d7e5254c17 Comment out failing sim QA tests
The tests will probably have to test against manually specified bounds
and inexact points.

Added a previously mistakenly uncommitted cmos_not.csv.
2022-07-30 09:19:20 +02:00