8a9ee0f9e1
CADSTAR PCB: Load 2-point polygons as line segments
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Fixes asserts when loading design from https://gitlab.com/kicad/code/kicad/-/issues/12349
(cherry picked from commit c961624d43
2022-09-04 01:03:55 +02:00
9a823ca61b
CADSTAR PCB: Parse Teardrops
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Todo: We need to figure out how we will load teardrops. For now
just drop them on import.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/12349
(cherry picked from commit 21b3753e9b
2022-09-04 01:03:51 +02:00
9e9b38ef6a
Revert "cadstar: Report warning that imported text may be different"
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This reverts commit f637a820b6
2022-08-20 20:09:40 -07:00
1005f75cdb
CADSTAR PCB: Allow remapping all non-electrical layers
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/12196
(cherry picked from commit 6b349fdb0a
2022-08-14 21:26:37 +00:00
f637a820b6
cadstar: Report warning that imported text may be different
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/12195
(cherry picked from commit 69d696660b
2022-08-14 21:25:46 +00:00
861589d837
Use wxEmptyString instead of wxT( "" )
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Also fixes places where ternaries did autopromotion instead of returning
an empty wxString
2022-02-09 10:33:52 -08:00
3af606a020
Wide string decls for gerbview.
2022-02-05 19:59:29 +00:00
f412d8d461
CADSTAR: Fix potential nullptr dereferencing bug
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Don't assume the footprint will have the pad index that the file references.
2022-02-05 19:22:05 +00:00
9e5e46514d
More wide-string declarations.
2022-02-05 13:29:00 +00:00
13f081549c
CADSTAR PCB: Use all User layers when mapping documentation layers
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/9577
2021-11-10 21:47:22 +00:00
ad2e780a2c
CADSTAR PCB: Correctly load pads with holes
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If the THROUGH_HOLE attribute isn't set, it just means that the pads
are only present on one side of the board, but there can still be a
plated / non-plated hole.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/9579
2021-11-10 21:21:32 +00:00
6cc6f06a9a
Millimetres -> Millimeters
2021-11-08 15:56:51 -08:00
6569337d27
Haching -> Hatching
2021-11-08 15:56:51 -08:00
6aa7602c32
CADSTAR PCB: Reverse anticlockwise arcs before adding to the chain
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/9533
2021-11-05 17:13:02 +00:00
8314251fa1
CADSTAR PCB: Force white silkscreen and green soldermask
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We don't know the actual colour from the design, but this is the most
common used in the industry.
2021-11-05 17:13:02 +00:00
b2db24f275
CADSTAR PCB: Don't invert Text Angle for mirrored text
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It matches the original cadstar when we don't invert
2021-10-30 18:14:23 +01:00
99442350a4
CADSTAR PCB: Fix loading of arc tracks following recent PCB_ARC changes
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We no longer have any knowledge of the original start/end of the arc,
since SetArcAngleAndEnd swaps the start and end to ensure the arc is
always clockwise at the end.
Adds a method EDA_SHAPE::EndsSwapped() to notify whether the start/end
point of the shape were swapped.
2021-10-17 17:57:51 +01:00
e867a4fd27
CADSTAR PCB: Fix Zone fill priorities
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The algorithm now correctly determines fill priorities when the zone
outlines are close together and within the minimum clearance between
zones.
2021-10-16 21:50:56 +01:00
9b9e379aa0
Overhaul arc internal model to not over-specify information.
2021-10-15 12:45:43 +01:00
8b08c9e53f
Shorter names before things get out of hand.
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Also, remove comments indicating CURVE is a Bezier. Just call it a
BEZIER.
2021-10-15 12:45:43 +01:00
a41944020d
Push most of PCB_SHAPE impl down in to EDA_SHAPE.
2021-10-15 12:45:43 +01:00
43e59b0ea7
CADSTAR PCB: Correctly handle associated pad ids and PCB Only pads
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/9372
2021-10-11 18:30:20 +01:00
7a71ebf9ac
CADSTAR PCB: Load all three net properties into a single Netclass
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The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
2021-10-10 22:16:08 +01:00
ac3ade874e
CADSTAR PCB: Set Copper-to-Hole clearance as 0
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Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).
This removes a large amount of DRC violations on imported designs.
2021-10-10 00:20:13 +01:00
eb7d0fdf8a
CADSTAR PCB: Use board clearance + additional isolation as zone clearance
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Copper-to-copper clearance is too onerous and results in large amount
of DRC errors for the majority of imported designs.
2021-10-10 00:18:36 +01:00
f4ff01a5ab
CADSTAR PCB: Copy default netclass settings when creating new ones
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Ensures that the global clearance is preserved in the newly created
netclass.
2021-10-09 23:10:55 +01:00
8f74085ca4
CADSTAR PCB: Handle older boards without construction layers
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Use KiCad default stackup for older CADSTAR boards that do not
define any dielectric layers between the electrical layers.
Also fix default stackup calculation to ensure finished board thickness
is 1.6mm
2021-10-09 21:26:16 +01:00
33a3cfc87b
CADSTAR PCB: Update Board Design Settings to notify that a stackup exists
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Also update thickness of the PCB
Fixes https://gitlab.com/kicad/code/kicad/-/issues/9307
2021-10-09 20:33:14 +01:00
e80a1c2679
CADSTAR PCB: Don't load items on invalid layers
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This was happening in two cases:
- Loading documentation symbols (CADSTAR on purpose defines these in an
invalid layer)
- When an item was in a "layer set" such as ALLELEC or ALLLAYER - need to
make sure we remove the copper layers that are not active in the design
2021-10-09 20:07:23 +01:00
677166f0b8
CADSTAR PCB: Rule Areas have zero width
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Cadstar areas have a line width but this is only for display purposes.
Instead CADSTAR uses the center line when determining whether a DRC
violation occurred.
2021-10-08 21:27:32 +01:00
2dfbd42be6
CADSTAR PCB: Legacy netclass and design settings loading is required
2021-10-08 20:48:10 +01:00
ae0229b7c9
CADSTAR PCB: Add imported nets to the imported netclass.
2021-10-08 20:25:09 +01:00
58fc4f512d
CADSTAR PCB: Don't create zero width tracks
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Fixes a bug in the route offsetting part of the import
that was resulting in zero-width tracks being imported.
2021-10-08 20:25:09 +01:00
16b61e47cd
CADSTAR PCB: Clear arcs from polys before boolean ops (e.g. zone fills)
2021-10-08 20:25:09 +01:00
fb588da875
CADSTAR PCB: Fix loading of thermal relief gap in zones
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We were loading as solid fill when the relief gap was exactly the
same as the minimum width.
Also we can do better than just load as solid fill when it is smaller:
we can instead just use the minimum width and at least it still will
have thermal reliefs.
2021-10-08 17:39:08 +01:00
cb47bf25c0
CADSTAR PCB: Actually load the original route code as a KiCad NETCLASS
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We weren't actually loading it into the design settings even though
everything else was already being correctly loaded.
2021-10-07 22:13:06 +01:00
625e56676a
Add progress reporting to CADSTAR Schematic & PCB importers
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/8685
2021-09-11 17:50:19 +01:00
e6ca9837a2
Clear numbers from non-numberable pads and don't run DRC on them.
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This was also the last straw on the misnamed PAD::GetName() and
PAD::SetName(), which are now PAD::GetNumber() and PAD::SetNumber().
Fixes https://gitlab.com/kicad/code/kicad/issues/9017
2021-08-24 01:03:06 +01:00
f221220fe2
Rename layer ids file.
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It hasn't had anything to do with colors or visibility for some time
now.
2021-07-29 16:03:25 +01:00
37b200cb3e
Pass wxString objects by reference instead of on the stack.
2021-07-27 08:41:27 -04:00
8fd83cbb95
Pass wxPoint objects by reference instead of on the stack.
2021-07-26 15:35:33 -04:00
0fb864d596
Pull some name changes back from 7.0 to ease merging.
2021-07-21 20:58:59 +01:00
cf00319c85
More NULL expunging.
2021-07-20 07:27:18 -04:00
e61822c9e0
Naming conventions and a bug fix on arc points.
2021-07-19 13:17:12 +01:00
062c4fda62
More error message regularization (and translatability improvements).
2021-06-28 00:45:24 +01:00
0dfb5fcaf9
Error message cleanup.
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wxString::Format is redundant in a wxLogXXX call.
Error messages should generally be translatable.
Error messages should use generally consistent sentence forms.
2021-06-26 22:53:24 +01:00
81fc710a5d
Use consistent terminology.
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Fixes https://gitlab.com/kicad/code/kicad/issues/8681
2021-06-26 10:11:41 +01:00
5fa5a73c6d
File open/import progress dialogs.
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Fixes https://gitlab.com/kicad/code/kicad/issues/6864
Fixes https://gitlab.com/kicad/code/kicad/issues/2166
2021-06-23 23:55:54 +01:00
096e342386
Prefix TRACK, ARC and VIA.
2021-06-11 22:07:02 +01:00
16b0147af8
Prefix DIMENSION types.
2021-06-11 17:59:44 +01:00
Roberto Fernandez Bautista
Seth Hillbrand
Jeff Young
Wayne Stambaugh