Commit Graph

1407 Commits

Author SHA1 Message Date
Seth Hillbrand e3231e6996 Rework VECTOR2D promotion rules
VECTOR + scalar = vector type (KiROUND when VECTOR is integral and
scalar is float)
VECTOR + VECTOR = common type vector

Implemented with concepts in template rules - SWIG compatible
2024-06-15 13:41:07 -07:00
Seth Hillbrand 3e16359b4f Update golden master for Altium import
The altium footprint being imported has vias that were ignored before,
so now we need to have the correct golden master with vias
2024-06-14 17:41:44 -07:00
Seth Hillbrand 6df16d053e Add specialization for unsigned scalar add/sub
Adding/subtracting an unsigned scalar to a signed vector should maintain
the same signed vector

Fixes https://gitlab.com/kicad/code/kicad/-/issues/18212
2024-06-14 17:27:59 -07:00
Jeff Young 0f8d543172 Consistent capitalization. 2024-06-14 22:02:08 +01:00
Mike Williams a5e2615251 Revert "SCH/LIB SYMBOL: never allow null LIB_SYMBOLs in SCH_SYMBOL"
This reverts commit 0b187e7122.
2024-06-12 13:30:29 -04:00
Jon Evans 5fc0f1f51e ADDED: Independent control of front/back via tenting 2024-06-11 21:50:25 -04:00
Jon Evans 4aab9f59aa ADDED: Support tenting control of individual vias
REMOVED: Tenting option from plot dialog (tenting is now
         controlled from Board Setup and via properties)

See https://gitlab.com/kicad/code/kicad/-/issues/2402
2024-06-11 21:25:02 -04:00
Seth Hillbrand 8dd93501cf Add additional VECTOR2 tests
Check overflow, addition using alternate value representations and
clamping
2024-06-10 15:21:44 -07:00
Seth Hillbrand 37191720ca Add common VECTOR2 test cases 2024-06-10 15:12:57 -07:00
Mike Williams 0b187e7122 SCH/LIB SYMBOL: never allow null LIB_SYMBOLs in SCH_SYMBOL
Also always always flatten incoming lib symbols.
2024-06-10 08:36:42 -04:00
Jeff Young aa1fb0604a Fix KeepUpright settings in Eagle gold files. 2024-06-09 23:38:54 +01:00
Alex Shvartzkop ee8b74d688 QA: update golden data for Altium "Tracks" PcbLib.
(cherry picked from commit c6b483acb9)
2024-06-09 23:03:33 +03:00
Jon Evans f5e7c705db Move custom shapes to PADSTACK; support in API 2024-06-08 14:26:36 -04:00
Jeff Young edc7603d2a Make it clear that GetSheets() is heavy.
Also removes the side-effect that SCH_SHEET_LIST's
c'tor would sort the list (and write virtual page
numbers) anytime the starting sheet was the root.

Also, definitely don't build a SHEET_LIST (sorted or
otherwise) if you're not even going to use it.

Also don't build SCH_SHEET_LISTs on idle events.  Better
to just always have the Next Sheet button enabled (we
already beep if you click it and there's no next sheet).

Also, use a SCREEN_LIST when you can.  It's much cheaper
to create.
2024-06-06 18:00:59 +01:00
Jon Evans 0b0a37aaf7 Move padstack serialization to PADSTACK
Also move a few more things from pad/via
2024-06-04 09:28:24 -04:00
Jeff Young 855c972156 Add regression test and example rule.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18142
2024-06-04 10:58:52 +01:00
Seth Hillbrand 75ab3d9e8b Handle arcs dp coupling
Calculate coupled arcs and spacing

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17967
2024-05-30 16:11:12 -07:00
Marek Roszko 4c5b4cd99f Add BOOST_TEST_CONTEXT wrap in one function 2024-05-29 22:23:59 -04:00
Wayne Stambaugh 795a9eea60 Coding policy fixes.
This is primarily to change all instances of wxLogDebug with wxLogTrace
so developers do not have to sift through debugging output that is always
dumped.  The only exception is for code blocks built in debug builds and
called on demand for dumping object states.
2024-05-23 07:59:45 -04:00
Seth Hillbrand 819bdf4372 Fix qa failure 2024-05-21 16:26:00 -07:00
John Beard 6992afeb38 Consider a bus entry hitting a wire corner or tee to be dot-worthy
This doesn't change the connectivity, it just makes putting the
dot more closely match what the connectivity already does.

Fixes: https://gitlab.com/kicad/code/kicad/-/issues/18046
2024-05-20 12:40:29 +08:00
John Beard 6313b58ad6 Break out junction analysis so it can be tested in isolation
There are some corner cases with bus entries that could do with
care and it's a bit tricky to keep all the cases in mind at once!
2024-05-20 12:40:29 +08:00
Jon Evans e16130a02c Move pad and via properties into PADSTACK 2024-05-14 20:57:56 -04:00
Jon Evans c800fb790d Start unifying padstack properties 2024-05-14 20:57:56 -04:00
Jeff Young e73d2a32dc ADDED checkbox for saving SPICE digital event data.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17828
2024-05-12 18:24:53 +01:00
Thomas Pointhuber a44c106f62 Migrate Altium pcblib test to BOOST_DATA_TEST_CASE and use FootprintNeedsUpdate for equality checking 2024-05-12 18:41:31 +02:00
Thomas Pointhuber 3ade85bc8d Fix compilation error caused by trying to include boost/test/data/test_case.hpp by default 2024-05-12 17:29:40 +02:00
Thomas Pointhuber 0890594f75 Altium: migrate test_altium_parser_utils.cpp to use BOOST_DATA_TEST_CASE 2024-05-12 17:10:45 +02:00
Thomas Pointhuber 01892ab98f Altium: extend tests to handle new cases introduced with commit b7460f29b4 2024-05-12 17:01:30 +02:00
Thomas Pointhuber 4aca6ba294 Change test_altium_parser.cpp to use BOOST_DATA_TEST_CASE for parameterized tests 2024-05-12 16:58:25 +02:00
Jeff Young 29360b1aef Raw spice models don't have pin names. 2024-05-10 20:58:13 +01:00
Jeff Young a0a368f47b Fix bogus value field in spice test source. 2024-05-10 15:58:48 +01:00
Jon Evans e1f6d82a34 Fix lifetime of markers in DRCFalseNegativeRegressions 2024-05-07 12:21:06 -04:00
Wayne Stambaugh a508f2e716 Fix false annular ring width DRC test failure.
The DRC annular ring width test failed to take into account that a pad
could be contained inside another pad having the same number (thermal
vias for example) which changes the effective annular width of the pad
contained within another pad.  A test was added to calculate the effective
annular ring width in this case.

Added some PNS log viewer helper and test code to the PNS playground QA
utility for testing the effective pad annular width code.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17485
2024-05-07 08:04:17 -04:00
John Beard fa7e842c8c Rework item distribution
This splits the tool into two separate tools: by center and
by even gaps. Previously, this was automatically decided, based on
if the items could have any gaps between them. This was unintuitive
as it would appear to arrange by centre point sometimes but not others.
When items aren't all the same width, the results can then be very
different, based only on the starting positions.

The new behaviour is to have a dedicated tool for each, which echos
how graphical programs like Inkscape manage this.

The by-gaps method is then extended to work for overlapping items
(when items overlap, the overlaps are made equal). The logic is
centralised in kimath/geometry, and some QA is added. This should
make it easier to extend to eeschema, for example.

This also (attempts to) address some rounding issues which could
cause minor, but compounding, errors to build up along the list
of items.

Also, fix bugs in the collection filtering - previously items
like markers were filtered out only after the selection size
was used to compute the gaps between items.
2024-05-05 03:35:09 +08:00
Thomas Pointhuber e82b8f6fda Fix small memleak in test_lib_part.cpp 2024-05-04 13:12:25 +02:00
Seth Hillbrand 8463bd59b7 ADDED: Optional check for four way junctions
Defaults to off because this is likely contentious

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17870
2024-05-03 12:06:24 -07:00
Seth Hillbrand 2139789c4c Move ERC items to their own directory 2024-05-03 12:06:24 -07:00
Seth Hillbrand b0c9df3ff4 Update QA mock for new PCB_SELECTION 2024-05-02 12:49:56 -07:00
Seth Hillbrand 5bede7bddb Update QA to reflect current correct output
Previously, (v7), the NPTH had a too-large clearance.  This affected the
fill so that there was no island.  In v8, at some point, NPTH had zero
clearance, which was definitely incorrect but also did not create an
island.

Correcting this to have the appropriate clearance between copper and
NPTH results in one almost island that has a neck and is appropriately
caught by the copper connection check.
2024-05-02 12:16:05 -07:00
Seth Hillbrand 339cf3f2e2 Fix simplify routine for last segment
The last segment of a track could be removed when the iterator does not
correctly loop.  Keeping the ll within bounds and checking for
equivalency instead of comparison works for last point
2024-04-30 16:11:20 -07:00
Alex Shvartzkop 16e3692e71 Build time optimizations. 2024-04-27 23:49:13 +03:00
dsa-t 16f3237983 QA: update Altium footprint library golden file.
(cherry picked from commit dd2f15c96d)

Co-authored-by: Alex Shvartzkop <dudesuchamazing@gmail.com>
2024-04-27 20:35:00 +00:00
Jeff Young c59ed0bbb7 Flip symbol editor's Y axis to match other editors. 2024-04-27 13:47:56 +01:00
James J be8744176c Add SCH_RULE_AREA shapes to eeschema
Includes:
 - Fix GAL to draw closed polygons in eeschema
 - Add functionality to eeschema to draw arbitary polygons
 - Update polygon item previews to have customisable edge colour
 - Add new SCH_RULE_AREA class, derived from a poly SCH_SHAPE
 - Add SCH_RULE_AREA to paint and plot methods
 - Add new rule area color preference to themes
2024-04-25 14:24:46 +00:00
Jeff Young 95136494b3 RIP LIB_PIN. 2024-04-20 12:10:31 +01:00
Jeff Young d761b4f22f RIP LIB_TEXTBOX and LIB_SHAPE. 2024-04-16 16:31:16 +01:00
Jeff Young 3efe504dcc Collapse LIB_TEXT into SCH_TEXT. 2024-04-16 16:31:16 +01:00
Seth Hillbrand f61d400d88 Allow non-identical schematic/pcb nets
The schematic net names are fully unique but if we have multiple pads
that are mapped to a NC pin, they need to have unique net names so that
they do not get connected to each other in the ratsnest.  This breaks
the schematic parity check as we have modified the netname for some
pads.  To work around this, we first maintain the zero-th net without
suffix and then add an additional check in DRC to ensure that we allow
unconnected nets as long as the share a common prefix with the schematic
netname.
2024-04-15 17:54:44 -07:00
Jeff Young d77eae3e7e Collapse LIB_FIELD into SCH_FIELD. 2024-04-13 15:42:13 +01:00