Also removes the side-effect that SCH_SHEET_LIST's
c'tor would sort the list (and write virtual page
numbers) anytime the starting sheet was the root.
Also, definitely don't build a SHEET_LIST (sorted or
otherwise) if you're not even going to use it.
Also don't build SCH_SHEET_LISTs on idle events. Better
to just always have the Next Sheet button enabled (we
already beep if you click it and there's no next sheet).
Also, use a SCREEN_LIST when you can. It's much cheaper
to create.
This is primarily to change all instances of wxLogDebug with wxLogTrace
so developers do not have to sift through debugging output that is always
dumped. The only exception is for code blocks built in debug builds and
called on demand for dumping object states.
The DRC annular ring width test failed to take into account that a pad
could be contained inside another pad having the same number (thermal
vias for example) which changes the effective annular width of the pad
contained within another pad. A test was added to calculate the effective
annular ring width in this case.
Added some PNS log viewer helper and test code to the PNS playground QA
utility for testing the effective pad annular width code.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17485
This splits the tool into two separate tools: by center and
by even gaps. Previously, this was automatically decided, based on
if the items could have any gaps between them. This was unintuitive
as it would appear to arrange by centre point sometimes but not others.
When items aren't all the same width, the results can then be very
different, based only on the starting positions.
The new behaviour is to have a dedicated tool for each, which echos
how graphical programs like Inkscape manage this.
The by-gaps method is then extended to work for overlapping items
(when items overlap, the overlaps are made equal). The logic is
centralised in kimath/geometry, and some QA is added. This should
make it easier to extend to eeschema, for example.
This also (attempts to) address some rounding issues which could
cause minor, but compounding, errors to build up along the list
of items.
Also, fix bugs in the collection filtering - previously items
like markers were filtered out only after the selection size
was used to compute the gaps between items.
Previously, (v7), the NPTH had a too-large clearance. This affected the
fill so that there was no island. In v8, at some point, NPTH had zero
clearance, which was definitely incorrect but also did not create an
island.
Correcting this to have the appropriate clearance between copper and
NPTH results in one almost island that has a neck and is appropriately
caught by the copper connection check.
The last segment of a track could be removed when the iterator does not
correctly loop. Keeping the ll within bounds and checking for
equivalency instead of comparison works for last point
Includes:
- Fix GAL to draw closed polygons in eeschema
- Add functionality to eeschema to draw arbitary polygons
- Update polygon item previews to have customisable edge colour
- Add new SCH_RULE_AREA class, derived from a poly SCH_SHAPE
- Add SCH_RULE_AREA to paint and plot methods
- Add new rule area color preference to themes
The schematic net names are fully unique but if we have multiple pads
that are mapped to a NC pin, they need to have unique net names so that
they do not get connected to each other in the ratsnest. This breaks
the schematic parity check as we have modified the netname for some
pads. To work around this, we first maintain the zero-th net without
suffix and then add an additional check in DRC to ensure that we allow
unconnected nets as long as the share a common prefix with the schematic
netname.
The connectivity routine would consider symbols, overwriting unused
subgraphs for pins that were not in the change list. This is resolved
by updating the full connectivity to only use pins in the graph since
symbols are not connected independently.
In the process of adding QA tests for this change, additional issues
with the schematic QA were discovered. Specifically, we were not
properly setting the root sheet UUID. This was partially masked by a
const_cast setting of the RefDes in sch_symbol when called the RefDes
getter. This exposed the fact that our QA ERC numbers did not match the
schematic editor stand alone ERC numbers. So the test value for one
check needed to be updated
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17528
When we add vertices to the tesselation routines, we cannot reuse these
without the original vertex points.
It may be possible to copy and modify the vertices from the hint data so
that they are properly positioned but naive attempts (moving based on
first point) did not work, so for now, we disable the hint cache when
the vertex sizes do not match as this prevents OOB access
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17621
Jon Evans
Jeff Young
Seth Hillbrand
Marek Roszko
Wayne Stambaugh
John Beard
Thomas Pointhuber
Alex Shvartzkop
James J
Roberto Fernandez Bautista