We don't want to allow the full track width to change after placing a
segment when we are in follow-segment mode. This would require either
ripping up and re-solving the existing track or allowing potential DRC
errors.
Fixes https://gitlab.com/kicad/code/kicad/issues/9395
__WXDEBUG__ is only for internal WX debugging and is always enabled even
on release builds because it is defined to be 0, 1 or 2. Use DEBUG to
limit to debug builds
Fixes https://gitlab.com/kicad/code/kicad/issues/9392
This should not run if the action is "Cut". Additionally, we need to
transfer the expanded selection to selectionCopy in order for it to
proceed with the deletion. There is also no need for this to be limited
to the Hover action, so this section was removed.
Fixes https://gitlab.com/kicad/code/kicad/issues/9385
The rebuildLayerStackPanel() reads from the current board to setup the
panel. We maintain the board swap until after the setup is completed
Fixes https://gitlab.com/kicad/code/kicad/issues/9370
We were already checking for zone-zone overlap but missing checks when
running against (possibly) buried vias as well as the general check
Fixes https://gitlab.com/kicad/code/kicad/issues/9366
The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).
This removes a large amount of DRC violations on imported designs.
Rather than detaching and re-attaching the layer panels with the
attendant overhead, we keep each panel intact and only update its
contents. Since the bindings are the same, this saves substantial time
on pcb loading as well as when closing the board setup dialog
Use KiCad default stackup for older CADSTAR boards that do not
define any dielectric layers between the electrical layers.
Also fix default stackup calculation to ensure finished board thickness
is 1.6mm
This was happening in two cases:
- Loading documentation symbols (CADSTAR on purpose defines these in an
invalid layer)
- When an item was in a "layer set" such as ALLELEC or ALLLAYER - need to
make sure we remove the copper layers that are not active in the design
Cadstar areas have a line width but this is only for display purposes.
Instead CADSTAR uses the center line when determining whether a DRC
violation occurred.
We were loading as solid fill when the relief gap was exactly the
same as the minimum width.
Also we can do better than just load as solid fill when it is smaller:
we can instead just use the minimum width and at least it still will
have thermal reliefs.
Makes usage cleaner. If the user specifies that they are creating an
SMD, they should get SMD pads by default so that they don't have to
change them later.
Fixes https://gitlab.com/kicad/code/kicad/issues/9333
Jeff Young
jean-pierre charras
Seth Hillbrand
Mikolaj Wielgus
Roberto Fernandez Bautista
Ian McInerney