kicad/pcbnew/specctra_import_export/specctra_export.cpp

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
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*
* Copyright (C) 2007-2015 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
* Copyright (C) 2015-2017 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
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/* This source is a complement to specctra.cpp and implements the export to
specctra dsn file format. The specification for the grammar of the specctra
dsn file used to develop this code is given here:
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http://tech.groups.yahoo.com/group/kicad-users/files/ then file "specctra.pdf"
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Also see the comments at the top of the specctra.cpp file itself.
*/
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#include <pcb_edit_frame.h>
#include <confirm.h> // DisplayError()
#include <gestfich.h> // EDA_FileSelector()
#include <trigo.h> // RotatePoint()
#include <macros.h>
#include <math/util.h> // for KiROUND
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#include <set> // std::set
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#include <map> // std::map
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#include <class_board.h>
#include <class_module.h>
#include <class_edge_mod.h>
#include <class_track.h>
#include <class_zone.h>
#include <base_units.h>
#include <wildcards_and_files_ext.h>
#include <collectors.h>
#include <geometry/shape_poly_set.h>
#include <geometry/convex_hull.h>
#include <convert_basic_shapes_to_polygon.h>
#include <geometry/geometry_utils.h>
#include <pcbnew_settings.h>
#include "specctra.h"
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using namespace DSN;
// comment the line #define EXPORT_CUSTOM_PADS_CONVEX_HULL to export CUSTOM pads exact shapes.
// Keep in mind shapes can be non convex polygons with holes (linked to outline)
// that can create issues.
// Especially Freerouter does not handle them very well:
// - too complex shapes are not accepted, especially shapes with holes (dsn files are not loaded).
// - and Freerouter actually uses something like a convex hull of the shape (that works not very well).
// I am guessing non convex polygons with holes linked could create issues with any Router.
#define EXPORT_CUSTOM_PADS_CONVEX_HULL
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// Add .1 mil to the requested clearances as a safety margin.
// There has been disagreement about interpretation of clearance in the past
// between KiCad and Freerouter, so keep this safetyMargin until the
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// disagreement is resolved and stable. Freerouter seems to be moving
// (protected) traces upon loading the DSN file, and even though it seems to sometimes
// add its own 0.1 to the clearances, I believe this is happening after
// the load process (and moving traces) so I am of the opinion this is
// still needed.
static const double safetyMargin = 0.1;
bool PCB_EDIT_FRAME::ExportSpecctraFile( const wxString& aFullFilename )
{
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SPECCTRA_DB db;
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bool ok = true;
wxString errorText;
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BASE_SCREEN* screen = GetScreen();
bool wasModified = screen->IsModify();
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db.SetPCB( SPECCTRA_DB::MakePCB() );
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LOCALE_IO toggle; // Switch the locale to standard C
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// DSN Images (=KiCad MODULES and pads) must be presented from the
// top view. So we temporarily flip any modules which are on the back
// side of the board to the front, and record this in the MODULE's flag field.
db.FlipMODULEs( GetBoard() );
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try
{
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GetBoard()->SynchronizeNetsAndNetClasses();
db.FromBOARD( GetBoard() );
db.ExportPCB( aFullFilename, true );
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// if an exception is thrown by FromBOARD or ExportPCB(), then
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// ~SPECCTRA_DB() will close the file.
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}
catch( const IO_ERROR& ioe )
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{
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ok = false;
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// copy the error string to safe place, ioe is in this scope only.
errorText = ioe.What();
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}
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// done assuredly, even if an exception was thrown and caught.
db.RevertMODULEs( GetBoard() );
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// The two calls below to MODULE::Flip(), both set the
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// modified flag, yet their actions cancel each other out, so it should
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// be ok to clear the modify flag.
if( !wasModified )
screen->ClrModify();
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if( ok )
{
SetStatusText( wxString( _( "BOARD exported OK." ) ) );
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}
else
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{
DisplayErrorMessage( this,
_( "Unable to export, please fix and try again" ),
errorText );
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}
return ok;
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}
namespace DSN {
const KICAD_T SPECCTRA_DB::scanPADs[] = { PCB_PAD_T, EOT };
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// "specctra reported units" are what we tell the external router that our
// exported lengths are in.
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/**
* Function scale
* converts a distance from PCBNEW internal units to the reported specctra dsn units
* in floating point format.
*/
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static inline double scale( int kicadDist )
{
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// nanometers to um
return kicadDist / ( IU_PER_MM / 1000.0 );
}
// / Convert integer internal units to float um
static inline double IU2um( int kicadDist )
{
return kicadDist * (1000.0 / IU_PER_MM);
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}
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static inline double mapX( int x )
{
return scale( x );
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}
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static inline double mapY( int y )
{
return -scale( y ); // make y negative, since it is increasing going down.
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}
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/**
* Function mapPt
* converts a KiCad point into a DSN file point. Kicad's BOARD coordinates
* are in nanometers (called Internal Units or IU)and we are exporting in units
* of mils, so we have to scale them.
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*/
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static POINT mapPt( const wxPoint& pt )
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{
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POINT ret;
ret.x = mapX( pt.x );
ret.y = mapY( pt.y );
ret.FixNegativeZero();
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return ret;
}
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/**
* Function isRoundKeepout
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* decides if the pad is a copper-less through hole which needs to be made into
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* a round keepout.
*/
static bool isRoundKeepout( D_PAD* aPad )
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{
if( aPad->GetShape()==PAD_SHAPE_CIRCLE )
{
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if( aPad->GetDrillSize().x >= aPad->GetSize().x )
return true;
if( !( aPad->GetLayerSet() & LSET::AllCuMask() ).any() )
return true;
}
return false;
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}
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/**
* Function makePath
* creates a PATH element with a single straight line, a pair of vertices.
*/
static PATH* makePath( const POINT& aStart, const POINT& aEnd, const std::string& aLayerName )
{
PATH* path = new PATH( 0, T_path );
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path->AppendPoint( aStart );
path->AppendPoint( aEnd );
path->SetLayerId( aLayerName.c_str() );
return path;
}
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PADSTACK* SPECCTRA_DB::makePADSTACK( BOARD* aBoard, D_PAD* aPad )
{
char name[256]; // padstack name builder
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std::string uniqifier;
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// caller must do these checks before calling here.
wxASSERT( !isRoundKeepout( aPad ) );
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PADSTACK* padstack = new PADSTACK();
int reportedLayers = 0; // how many in reported padstack
const char* layerName[MAX_CU_LAYERS];
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uniqifier = '[';
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static const LSET all_cu = LSET::AllCuMask();
bool onAllCopperLayers = ( (aPad->GetLayerSet() & all_cu) == all_cu );
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if( onAllCopperLayers )
uniqifier += 'A'; // A for all layers
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const int copperCount = aBoard->GetCopperLayerCount();
for( int layer=0; layer<copperCount; ++layer )
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{
PCB_LAYER_ID kilayer = pcbLayer2kicad[layer];
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if( onAllCopperLayers || aPad->IsOnLayer( kilayer ) )
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{
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layerName[reportedLayers++] = layerIds[layer].c_str();
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if( !onAllCopperLayers )
{
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if( layer == 0 )
uniqifier += 'T';
else if( layer == copperCount - 1 )
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uniqifier += 'B';
else
uniqifier += char('0' + layer); // layer index char
}
}
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}
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uniqifier += ']';
POINT dsnOffset;
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if( aPad->GetOffset().x || aPad->GetOffset().y )
{
char offsetTxt[64];
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wxPoint offset( aPad->GetOffset().x, aPad->GetOffset().y );
dsnOffset = mapPt( offset );
// using '(' or ')' would cause padstack name to be quote wrapped,
// so use other brackets, and {} locks freerouter.
sprintf( offsetTxt, "[%.6g,%.6g]", dsnOffset.x, dsnOffset.y );
uniqifier += offsetTxt;
}
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switch( aPad->GetShape() )
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{
case PAD_SHAPE_CIRCLE:
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{
double diameter = scale( aPad->GetSize().x );
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for( int ndx=0; ndx<reportedLayers; ++ndx )
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{
SHAPE* shape = new SHAPE( padstack );
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padstack->Append( shape );
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CIRCLE* circle = new CIRCLE( shape );
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shape->SetShape( circle );
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circle->SetLayerId( layerName[ndx] );
circle->SetDiameter( diameter );
circle->SetVertex( dsnOffset );
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}
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snprintf( name, sizeof(name), "Round%sPad_%.6g_um",
uniqifier.c_str(), IU2um( aPad->GetSize().x ) );
name[ sizeof(name) - 1 ] = 0;
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padstack->SetPadstackId( name );
}
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break;
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case PAD_SHAPE_RECT:
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{
double dx = scale( aPad->GetSize().x ) / 2.0;
double dy = scale( aPad->GetSize().y ) / 2.0;
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POINT lowerLeft( -dx, -dy );
POINT upperRight( dx, dy );
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lowerLeft += dsnOffset;
upperRight += dsnOffset;
for( int ndx=0; ndx<reportedLayers; ++ndx )
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{
SHAPE* shape = new SHAPE( padstack );
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padstack->Append( shape );
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RECTANGLE* rect = new RECTANGLE( shape );
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shape->SetShape( rect );
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rect->SetLayerId( layerName[ndx] );
rect->SetCorners( lowerLeft, upperRight );
}
snprintf( name, sizeof(name), "Rect%sPad_%.6gx%.6g_um",
uniqifier.c_str(),
IU2um( aPad->GetSize().x ),
IU2um( aPad->GetSize().y ) );
name[ sizeof(name) - 1 ] = 0;
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padstack->SetPadstackId( name );
}
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break;
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case PAD_SHAPE_OVAL:
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{
double dx = scale( aPad->GetSize().x ) / 2.0;
double dy = scale( aPad->GetSize().y ) / 2.0;
double dr = dx - dy;
double radius;
POINT pstart;
POINT pstop;
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if( dr >= 0 ) // oval is horizontal
{
radius = dy;
pstart = POINT( -dr, 0.0 );
pstop = POINT( dr, 0.0 );
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}
else // oval is vertical
{
radius = dx;
dr = -dr;
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pstart = POINT( 0.0, -dr );
pstop = POINT( 0.0, dr );
}
pstart += dsnOffset;
pstop += dsnOffset;
for( int ndx=0; ndx<reportedLayers; ++ndx )
{
SHAPE* shape;
PATH* path;
// see http://www.freerouting.net/usren/viewtopic.php?f=3&t=317#p408
shape = new SHAPE( padstack );
padstack->Append( shape );
path = makePath( pstart, pstop, layerName[ndx] );
shape->SetShape( path );
path->aperture_width = 2.0 * radius;
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}
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snprintf( name, sizeof(name), "Oval%sPad_%.6gx%.6g_um",
uniqifier.c_str(),
IU2um( aPad->GetSize().x ),
IU2um( aPad->GetSize().y ) );
name[ sizeof(name) - 1 ] = 0;
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padstack->SetPadstackId( name );
}
break;
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case PAD_SHAPE_TRAPEZOID:
{
double dx = scale( aPad->GetSize().x ) / 2.0;
double dy = scale( aPad->GetSize().y ) / 2.0;
double ddx = scale( aPad->GetDelta().x ) / 2.0;
double ddy = scale( aPad->GetDelta().y ) / 2.0;
// see class_pad_draw_functions.cpp which draws the trapezoid pad
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POINT lowerLeft( -dx - ddy, -dy - ddx );
POINT upperLeft( -dx + ddy, +dy + ddx );
POINT upperRight( +dx - ddy, +dy - ddx );
POINT lowerRight( +dx + ddy, -dy + ddx );
lowerLeft += dsnOffset;
upperLeft += dsnOffset;
upperRight += dsnOffset;
lowerRight += dsnOffset;
for( int ndx=0; ndx<reportedLayers; ++ndx )
{
SHAPE* shape = new SHAPE( padstack );
padstack->Append( shape );
// a T_polygon exists as a PATH
PATH* polygon = new PATH( shape, T_polygon );
shape->SetShape( polygon );
polygon->SetLayerId( layerName[ndx] );
polygon->AppendPoint( lowerLeft );
polygon->AppendPoint( upperLeft );
polygon->AppendPoint( upperRight );
polygon->AppendPoint( lowerRight );
}
// this string _must_ be unique for a given physical shape
snprintf( name, sizeof(name), "Trapz%sPad_%.6gx%.6g_%c%.6gx%c%.6g_um",
uniqifier.c_str(), IU2um( aPad->GetSize().x ), IU2um( aPad->GetSize().y ),
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aPad->GetDelta().x < 0 ? 'n' : 'p',
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std::abs( IU2um( aPad->GetDelta().x )),
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aPad->GetDelta().y < 0 ? 'n' : 'p',
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std::abs( IU2um( aPad->GetDelta().y ) )
);
name[ sizeof(name)-1 ] = 0;
padstack->SetPadstackId( name );
}
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break;
case PAD_SHAPE_CHAMFERED_RECT:
case PAD_SHAPE_ROUNDRECT:
{
// Export the shape as as polygon, round rect does not exist as primitive
const int circleToSegmentsCount = 36;
int rradius = aPad->GetRoundRectCornerRadius();
SHAPE_POLY_SET cornerBuffer;
// Use a slightly bigger shape because the round corners are approximated by
// segments, giving to the polygon a slightly smaller shape than the actual shape
/* calculates the coeff to compensate radius reduction of holes clearance
* due to the segment approx.
* For a circle the min radius is radius * cos( 2PI / s_CircleToSegmentsCount / 2)
* correctionFactor is cos( PI/s_CircleToSegmentsCount )
*/
double correctionFactor = cos( M_PI / (double) circleToSegmentsCount );
int extra_clearance = KiROUND( rradius * (1.0 - correctionFactor ) );
wxSize psize = aPad->GetSize();
psize.x += extra_clearance*2;
psize.y += extra_clearance*2;
rradius += extra_clearance;
bool doChamfer = aPad->GetShape() == PAD_SHAPE_CHAMFERED_RECT;
TransformRoundChamferedRectToPolygon( cornerBuffer, wxPoint(0,0), psize,
0, rradius,
aPad->GetChamferRectRatio(),
doChamfer ? aPad->GetChamferPositions() : 0,
aBoard->GetDesignSettings().m_MaxError );
SHAPE_LINE_CHAIN& polygonal_shape = cornerBuffer.Outline( 0 );
for( int ndx=0; ndx < reportedLayers; ++ndx )
{
SHAPE* shape = new SHAPE( padstack );
padstack->Append( shape );
// a T_polygon exists as a PATH
PATH* polygon = new PATH( shape, T_polygon );
shape->SetShape( polygon );
polygon->SetLayerId( layerName[ndx] );
// append a closed polygon
POINT first_corner;
for( int idx = 0; idx < polygonal_shape.PointCount(); idx++ )
{
POINT corner( scale( polygonal_shape.CPoint( idx ).x ),
scale( -polygonal_shape.CPoint( idx ).y ) );
corner += dsnOffset;
polygon->AppendPoint( corner );
if( idx == 0 )
first_corner = corner;
}
polygon->AppendPoint( first_corner ); // Close polygon
}
// this string _must_ be unique for a given physical shape
snprintf( name, sizeof(name), "RoundRect%sPad_%.6gx%.6g_%.6g_um",
uniqifier.c_str(),
IU2um( aPad->GetSize().x ),
IU2um( aPad->GetSize().y ), IU2um( rradius ) );
name[ sizeof(name) - 1 ] = 0;
padstack->SetPadstackId( name );
}
break;
case PAD_SHAPE_CUSTOM:
{
std::vector<wxPoint> polygonal_shape;
const SHAPE_POLY_SET& pad_shape = aPad->GetCustomShapeAsPolygon();
#ifdef EXPORT_CUSTOM_PADS_CONVEX_HULL
BuildConvexHull( polygonal_shape, pad_shape );
#else
const SHAPE_LINE_CHAIN& p_outline = pad_shape.COutline( 0 );
for( int ii = 0; ii < p_outline.PointCount(); ++ii )
polygonal_shape.push_back( wxPoint( p_outline.CPoint( ii ) ) );
#endif
// The polygon must be closed
if( polygonal_shape.front() != polygonal_shape.back() )
polygonal_shape.push_back( polygonal_shape.front() );
for( int ndx=0; ndx < reportedLayers; ++ndx )
{
SHAPE* shape = new SHAPE( padstack );
padstack->Append( shape );
// a T_polygon exists as a PATH
PATH* polygon = new PATH( shape, T_polygon );
shape->SetShape( polygon );
polygon->SetLayerId( layerName[ndx] );
for( unsigned idx = 0; idx < polygonal_shape.size(); idx++ )
{
POINT corner( scale( polygonal_shape[idx].x ), scale( -polygonal_shape[idx].y ) );
corner += dsnOffset;
polygon->AppendPoint( corner );
}
}
// this string _must_ be unique for a given physical shape, so try to make it unique
EDA_RECT rect = aPad->GetBoundingBox();
snprintf( name, sizeof(name), "Cust%sPad_%.6gx%.6g_%.6gx_%.6g_%d_um",
uniqifier.c_str(), IU2um( aPad->GetSize().x ), IU2um( aPad->GetSize().y ),
IU2um( rect.GetWidth() ), IU2um( rect.GetHeight() ),
(int)polygonal_shape.size() );
name[ sizeof(name)-1 ] = 0;
padstack->SetPadstackId( name );
}
break;
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}
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return padstack;
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}
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/// data type used to ensure unique-ness of pin names, holding (wxString and int)
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typedef std::map<wxString, int> PINMAP;
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IMAGE* SPECCTRA_DB::makeIMAGE( BOARD* aBoard, MODULE* aModule )
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{
PINMAP pinmap;
wxString padName;
PCB_TYPE_COLLECTOR moduleItems;
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// get all the MODULE's pads.
moduleItems.Collect( aModule, scanPADs );
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IMAGE* image = new IMAGE(0);
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image->image_id = aModule->GetFPID().Format().c_str();
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// from the pads, and make an IMAGE using collated padstacks.
for( int p=0; p < moduleItems.GetCount(); ++p )
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{
D_PAD* pad = (D_PAD*) moduleItems[p];
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// see if this pad is a through hole with no copper on its perimeter
if( isRoundKeepout( pad ) )
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{
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double diameter = scale( pad->GetDrillSize().x );
POINT vertex = mapPt( pad->GetPos0() );
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int layerCount = aBoard->GetCopperLayerCount();
for( int layer=0; layer<layerCount; ++layer )
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{
KEEPOUT* keepout = new KEEPOUT( image, T_keepout );
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image->keepouts.push_back( keepout );
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CIRCLE* circle = new CIRCLE( keepout );
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keepout->SetShape( circle );
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circle->SetDiameter( diameter );
circle->SetVertex( vertex );
circle->SetLayerId( layerIds[layer].c_str() );
}
}
// else if() could there be a square keepout here?
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else
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{
// Pads not on copper layers (i.e. only on tech layers) are ignored
// because they create invalid pads in .dsn file for freeroute
LSET mask_copper_layers = pad->GetLayerSet() & LSET::AllCuMask();
if( !mask_copper_layers.any() )
continue;
PADSTACK* padstack = makePADSTACK( aBoard, pad );
PADSTACKSET::iterator iter = padstackset.find( *padstack );
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if( iter != padstackset.end() )
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{
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// padstack is a duplicate, delete it and use the original
delete padstack;
padstack = (PADSTACK*) *iter.base(); // folklore, be careful here
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}
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else
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{
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padstackset.insert( padstack );
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}
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PIN* pin = new PIN( image );
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padName = pad->GetName();
pin->pin_id = TO_UTF8( padName );
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if( padName!=wxEmptyString && pinmap.find( padName )==pinmap.end() )
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{
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pinmap[ padName ] = 0;
}
else // pad name is a duplicate within this module
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{
char buf[32];
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int duplicates = ++pinmap[ padName ];
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sprintf( buf, "@%d", duplicates );
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pin->pin_id += buf; // append "@1" or "@2", etc. to pin name
}
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pin->kiNetCode = pad->GetNetCode();
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image->pins.push_back( pin );
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pin->padstack_id = padstack->padstack_id;
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double angle = pad->GetOrientationDegrees() - aModule->GetOrientationDegrees();
NORMALIZE_ANGLE_DEGREES_POS( angle );
pin->SetRotation( angle );
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wxPoint pos( pad->GetPos0() );
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pin->SetVertex( mapPt( pos ) );
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}
}
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#if 1 // enable image (outline) scopes.
static const KICAD_T scanEDGEs[] = { PCB_MODULE_EDGE_T, EOT };
// get all the MODULE's EDGE_MODULEs and convert those to DSN outlines.
moduleItems.Collect( aModule, scanEDGEs );
for( int i = 0; i<moduleItems.GetCount(); ++i )
{
EDGE_MODULE* graphic = (EDGE_MODULE*) moduleItems[i];
SHAPE* outline;
PATH* path;
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switch( graphic->GetShape() )
{
case S_SEGMENT:
outline = new SHAPE( image, T_outline );
image->Append( outline );
path = new PATH( outline );
outline->SetShape( path );
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path->SetAperture( scale( graphic->GetWidth() ) );
path->SetLayerId( "signal" );
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path->AppendPoint( mapPt( graphic->GetStart0() ) );
path->AppendPoint( mapPt( graphic->GetEnd0() ) );
break;
case S_CIRCLE:
{
// this is best done by 4 QARC's but freerouter does not yet support QARCs.
// for now, support by using line segments.
outline = new SHAPE( image, T_outline );
image->Append( outline );
path = new PATH( outline );
outline->SetShape( path );
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path->SetAperture( scale( graphic->GetWidth() ) );
path->SetLayerId( "signal" );
// Do the math using KiCad units, that way we stay out of the
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// scientific notation range of floating point numbers in the
// DSN file. We do not parse scientific notation in our own
// lexer/beautifier, and the spec is not clear that this is
// required. Fixed point floats are all that should be needed.
double radius = GetLineLength( graphic->GetStart(), graphic->GetEnd() );
// seg count to approximate circle by line segments
int seg_per_circle = GetArcToSegmentCount( radius, ARC_LOW_DEF, 360.0 );
for( int ii = 0; ii < seg_per_circle; ++ii )
{
double radians = 2*M_PI / seg_per_circle * ii;
wxPoint point( KiROUND( radius * cos( radians ) ),
KiROUND( radius * sin( radians ) ) );
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point += graphic->m_Start0; // an offset
path->AppendPoint( mapPt( point ) );
}
// The shape must be closed
wxPoint point( radius , 0 );
point += graphic->m_Start0;
path->AppendPoint( mapPt( point ) );
}
break;
case S_RECT:
case S_ARC:
default:
DBG( printf( "makeIMAGE(): unsupported shape %s\n",
TO_UTF8( BOARD_ITEM::ShowShape( graphic->GetShape() ) ) ); )
continue;
}
}
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#endif
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return image;
}
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PADSTACK* SPECCTRA_DB::makeVia( int aCopperDiameter, int aDrillDiameter,
int aTopLayer, int aBotLayer )
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{
char name[48];
PADSTACK* padstack = new PADSTACK();
double dsnDiameter = scale( aCopperDiameter );
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for( int layer=aTopLayer; layer<=aBotLayer; ++layer )
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{
SHAPE* shape = new SHAPE( padstack );
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padstack->Append( shape );
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CIRCLE* circle = new CIRCLE( shape );
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shape->SetShape( circle );
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circle->SetDiameter( dsnDiameter );
circle->SetLayerId( layerIds[layer].c_str() );
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}
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snprintf( name, sizeof(name), "Via[%d-%d]_%.6g:%.6g_um",
aTopLayer, aBotLayer, dsnDiameter,
// encode the drill value into the name for later import
IU2um( aDrillDiameter )
);
name[ sizeof(name) - 1 ] = 0;
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padstack->SetPadstackId( name );
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return padstack;
}
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PADSTACK* SPECCTRA_DB::makeVia( const ::VIA* aVia )
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{
PCB_LAYER_ID topLayerNum;
PCB_LAYER_ID botLayerNum;
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* KIWAY Milestone A): Make major modules into DLL/DSOs. ! The initial testing of this commit should be done using a Debug build so that all the wxASSERT()s are enabled. Also, be sure and keep enabled the USE_KIWAY_DLLs option. The tree won't likely build without it. Turning it off is senseless anyways. If you want stable code, go back to a prior version, the one tagged with "stable". * Relocate all functionality out of the wxApp derivative into more finely targeted purposes: a) DLL/DSO specific b) PROJECT specific c) EXE or process specific d) configuration file specific data e) configuration file manipulations functions. All of this functionality was blended into an extremely large wxApp derivative and that was incompatible with the desire to support multiple concurrently loaded DLL/DSO's ("KIFACE")s and multiple concurrently open projects. An amazing amount of organization come from simply sorting each bit of functionality into the proper box. * Switch to wxConfigBase from wxConfig everywhere except instantiation. * Add classes KIWAY, KIFACE, KIFACE_I, SEARCH_STACK, PGM_BASE, PGM_KICAD, PGM_SINGLE_TOP, * Remove "Return" prefix on many function names. * Remove obvious comments from CMakeLists.txt files, and from else() and endif()s. * Fix building boost for use in a DSO on linux. * Remove some of the assumptions in the CMakeLists.txt files that windows had to be the host platform when building windows binaries. * Reduce the number of wxStrings being constructed at program load time via static construction. * Pass wxConfigBase* to all SaveSettings() and LoadSettings() functions so that these functions are useful even when the wxConfigBase comes from another source, as is the case in the KICAD_MANAGER_FRAME. * Move the setting of the KIPRJMOD environment variable into class PROJECT, so that it can be moved into a project variable soon, and out of FP_LIB_TABLE. * Add the KIWAY_PLAYER which is associated with a particular PROJECT, and all its child wxFrames and wxDialogs now have a Kiway() member function which returns a KIWAY& that that window tree branch is in support of. This is like wxWindows DNA in that child windows get this member with proper value at time of construction. * Anticipate some of the needs for milestones B) and C) and make code adjustments now in an effort to reduce work in those milestones. * No testing has been done for python scripting, since milestone C) has that being largely reworked and re-thought-out.
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aVia->LayerPair( &topLayerNum, &botLayerNum );
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int topLayer = kicadLayer2pcb[topLayerNum];
int botLayer = kicadLayer2pcb[botLayerNum];
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if( topLayer > botLayer )
std::swap( topLayer, botLayer );
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return makeVia( aVia->GetWidth(), aVia->GetDrillValue(), topLayer, botLayer );
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}
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void SPECCTRA_DB::fillBOUNDARY( BOARD* aBoard, BOUNDARY* boundary )
{
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wxString errMessage;
SHAPE_POLY_SET outlines;
aBoard->GetBoardPolygonOutlines( outlines, &errMessage );
for( int cnt = 0; cnt < outlines.OutlineCount(); cnt++ ) // Should be one outline
{
PATH* path = new PATH( boundary );
boundary->paths.push_back( path );
path->layer_id = "pcb";
SHAPE_LINE_CHAIN& outline = outlines.Outline( cnt );
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for( int ii = 0; ii < outline.PointCount(); ii++ )
{
wxPoint pos( outline.CPoint( ii ).x, outline.CPoint( ii ).y );
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path->AppendPoint( mapPt( pos ) );
}
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// Close polygon:
wxPoint pos0( outline.CPoint( 0 ).x, outline.CPoint( 0 ).y );
path->AppendPoint( mapPt( pos0 ) );
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// Generate holes as keepout:
for( int ii = 0; ii < outlines.HoleCount( cnt ); ii++ )
{
// emit a signal layers keepout for every interior polygon left...
KEEPOUT* keepout = new KEEPOUT( NULL, T_keepout );
PATH* poly_ko = new PATH( NULL, T_polygon );
keepout->SetShape( poly_ko );
poly_ko->SetLayerId( "signal" );
pcb->structure->keepouts.push_back( keepout );
SHAPE_LINE_CHAIN& hole = outlines.Hole( cnt, ii );
for( int jj = 0; jj < hole.PointCount(); jj++ )
{
wxPoint pos( hole.CPoint( jj ).x, hole.CPoint( jj ).y );
poly_ko->AppendPoint( mapPt( pos ) );
}
// Close polygon:
wxPoint pos( hole.CPoint( 0 ).x, hole.CPoint( 0 ).y );
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poly_ko->AppendPoint( mapPt( pos ) );
}
}
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if( !errMessage.IsEmpty() )
wxLogMessage( errMessage );
}
typedef std::set<std::string> STRINGSET;
typedef std::pair<STRINGSET::iterator, bool> STRINGSET_PAIR;
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void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
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{
PCB_TYPE_COLLECTOR items;
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static const KICAD_T scanMODULEs[] = { PCB_MODULE_T, EOT };
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// Not all boards are exportable. Check that all reference Ids are unique.
// Unless they are unique, we cannot import the session file which comes
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// back to us later from the router.
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{
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items.Collect( aBoard, scanMODULEs );
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STRINGSET refs; // holds module reference designators
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for( int i=0; i<items.GetCount(); ++i )
{
MODULE* module = (MODULE*) items[i];
if( module->GetReference() == wxEmptyString )
{
THROW_IO_ERROR( wxString::Format( _( "Symbol with value of \"%s\" has empty reference id." ),
GetChars( module->GetValue() ) ) );
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}
// if we cannot insert OK, that means the reference has been seen before.
STRINGSET_PAIR refpair = refs.insert( TO_UTF8( module->GetReference() ) );
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if( !refpair.second ) // insert failed
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{
THROW_IO_ERROR( wxString::Format( _( "Multiple symbols have identical reference IDs of \"%s\"." ),
GetChars( module->GetReference() ) ) );
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}
}
}
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if( !pcb )
pcb = SPECCTRA_DB::MakePCB();
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//-----<layer_descriptor>-----------------------------------------------
{
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// specctra wants top physical layer first, then going down to the
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// bottom most physical layer in physical sequence.
// @question : why does KiCad not display layers in that order?
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buildLayerMaps( aBoard );
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int layerCount = aBoard->GetCopperLayerCount();
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for( int pcbNdx=0; pcbNdx<layerCount; ++pcbNdx )
{
LAYER* layer = new LAYER( pcb->structure );
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pcb->structure->layers.push_back( layer );
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layer->name = layerIds[pcbNdx];
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DSN_T layerType;
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switch( aBoard->GetLayerType( pcbLayer2kicad[pcbNdx] ) )
{
default:
case LT_SIGNAL: layerType = T_signal; break;
case LT_POWER: layerType = T_power; break;
#if 1 // Freerouter does not support type "mixed", only signal and power.
// Remap "mixed" to "signal".
case LT_MIXED: layerType = T_signal; break;
#else
case LT_MIXED: layerType = T_mixed; break;
#endif
case LT_JUMPER: layerType = T_jumper; break;
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}
layer->layer_type = layerType;
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layer->properties.push_back( PROPERTY() );
PROPERTY* property = &layer->properties.back();
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property->name = "index";
char temp[32];
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sprintf( temp, "%d", pcbNdx );
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property->value = temp;
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}
}
// a space in a quoted token is NOT a terminator, true establishes this.
pcb->parser->space_in_quoted_tokens = true;
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//-----<unit_descriptor> & <resolution_descriptor>--------------------
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{
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// tell freerouter to use "tenths of micrometers",
// which is 100 nm resolution. Possibly more resolution is possible
// in freerouter, but it would need testing.
pcb->unit->units = T_um;
pcb->resolution->units = T_um;
pcb->resolution->value = 10; // tenths of a um
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// pcb->resolution->value = 1000; // "thousandths of a um" (i.e. "nm")
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}
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//-----<boundary_descriptor>------------------------------------------
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{
// Because fillBOUNDARY() can throw an exception, we link in an
// empty boundary so the BOUNDARY does not get lost in the event of
// of an exception.
BOUNDARY* boundary = new BOUNDARY( 0 );
pcb->structure->SetBOUNDARY( boundary );
fillBOUNDARY( aBoard, boundary );
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}
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//-----<rules>--------------------------------------------------------
{
char rule[80];
NETCLASSPTR defaultClass = aBoard->GetDesignSettings().GetDefault();
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int defaultTrackWidth = defaultClass->GetTrackWidth();
int defaultClearance = defaultClass->GetClearance();
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double clearance = scale( defaultClearance );
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STRINGS& rules = pcb->structure->rules->rules;
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sprintf( rule, "(width %.6g)", scale( defaultTrackWidth ) );
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rules.push_back( rule );
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sprintf( rule, "(clearance %.6g)", clearance + safetyMargin );
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rules.push_back( rule );
// On a high density board (a board with 4 mil tracks, 4 mil spacing)
// a typical solder mask clearance will be 2-3 mils.
// This exposes 2 to 3 mils of bare board around each pad, and would
// leave only 1 to 2 mils of solder mask between the solder mask's boundary
// to the edge of any trace within "clearance" of the pad. So we need at least
// 2 mils *extra* clearance for traces which would come near a pad on
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// a different net. So if the baseline trace to trace clearance was say 4 mils, then
// the SMD to trace clearance should be at least 6 mils.
double default_smd = clearance + safetyMargin;
if( default_smd <= 6.0 )
default_smd = 6.0;
sprintf( rule, "(clearance %.6g (type default_smd))", default_smd );
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rules.push_back( rule );
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/* see: http://www.freerouting.net/usren/viewtopic.php?f=5&t=339#p474
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sprintf( rule, "(clearance %.6g (type pad_to_turn_gap))", clearance + safetyMargin );
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rules.push_back( rule );
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sprintf( rule, "(clearance %.6g (type smd_to_turn_gap))", clearance + safetyMargin );
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rules.push_back( rule );
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sprintf( rule, "(clearance %.6g (type via_via))", clearance + safetyMargin );
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rules.push_back( rule );
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sprintf( rule, "(clearance %.6g (type via_smd))", clearance + safetyMargin );
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rules.push_back( rule );
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sprintf( rule, "(clearance %.6g (type via_pin))", clearance + safetyMargin );
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rules.push_back( rule );
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sprintf( rule, "(clearance %.6g (type pin_pin))", clearance + safetyMargin );
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rules.push_back( rule );
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sprintf( rule, "(clearance %.6g (type smd_pin))", clearance + safetyMargin );
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rules.push_back( rule );
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*/
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// Pad to pad spacing on a single SMT part can be closer than our
// clearance, we don't want freerouter complaining about that, so
// output a significantly smaller pad to pad clearance to freerouter.
clearance = scale( defaultClearance ) / 4;
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sprintf( rule, "(clearance %.6g (type smd_smd))", clearance );
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rules.push_back( rule );
}
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//-----<zone containers (not keepout areas) become planes>--------------------------------
// Note: only zones are output here, keepout areas be be created later
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{
int netlessZones = 0;
static const KICAD_T scanZONEs[] = { PCB_ZONE_AREA_T, EOT };
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items.Collect( aBoard, scanZONEs );
for( int i = 0; i<items.GetCount(); ++i )
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{
ZONE_CONTAINER* item = (ZONE_CONTAINER*) items[i];
if( item->GetIsKeepout() )
continue;
// Currently, we export only copper layers
if( ! IsCopperLayer( item->GetLayer() ) )
continue;
2008-01-23 22:36:37 +00:00
COPPER_PLANE* plane = new COPPER_PLANE( pcb->structure );
2008-05-22 15:55:24 +00:00
pcb->structure->planes.push_back( plane );
PATH* mainPolygon = new PATH( plane, T_polygon );
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plane->SetShape( mainPolygon );
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plane->name = TO_UTF8( item->GetNetname() );
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if( plane->name.size() == 0 )
{
char name[32];
// This is one of those no connection zones, netcode=0, and it has no name.
// Create a unique, bogus netname.
NET* no_net = new NET( pcb->network );
sprintf( name, "@:no_net_%d", netlessZones++ );
no_net->net_id = name;
// add the bogus net name to network->nets.
pcb->network->nets.push_back( no_net );
// use the bogus net name in the netless zone.
plane->name = no_net->net_id;
}
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mainPolygon->layer_id = layerIds[ kicadLayer2pcb[ item->GetLayer() ] ];
2008-02-07 20:23:58 +00:00
// Handle the main outlines
SHAPE_POLY_SET::ITERATOR iterator;
wxPoint startpoint;
bool is_first_point = true;
for( iterator = item->IterateWithHoles(); iterator; iterator++ )
2008-01-23 22:36:37 +00:00
{
wxPoint point( iterator->x, iterator->y );
if( is_first_point )
{
startpoint = point;
is_first_point = false;
}
mainPolygon->AppendPoint( mapPt( point ) );
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// this was the end of the main polygon
if( iterator.IsEndContour() )
{
// Close polygon
mainPolygon->AppendPoint( mapPt( startpoint ) );
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break;
}
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}
WINDOW* window = 0;
PATH* cutout = 0;
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bool isStartContour = true;
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// handle the cutouts
for( iterator++; iterator; iterator++ )
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{
if( isStartContour )
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{
is_first_point = true;
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window = new WINDOW( plane );
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plane->AddWindow( window );
cutout = new PATH( window, T_polygon );
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window->SetShape( cutout );
cutout->layer_id = layerIds[ kicadLayer2pcb[ item->GetLayer() ] ];
}
// If the point in this iteration is the last of the contour, the next iteration
// will start with a new contour.
isStartContour = iterator.IsEndContour();
2009-02-06 14:23:56 +00:00
wxASSERT( window );
wxASSERT( cutout );
wxPoint point(iterator->x, iterator->y );
if( is_first_point )
{
startpoint = point;
is_first_point = false;
}
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cutout->AppendPoint( mapPt(point) );
// Close the polygon
if( iterator.IsEndContour() )
cutout->AppendPoint( mapPt( startpoint ) );
2008-01-23 22:36:37 +00:00
}
}
}
2008-01-24 21:47:54 +00:00
//-----<zone containers flagged keepout areas become keepout>--------------------------------
{
static const KICAD_T scanZONEs[] = { PCB_ZONE_AREA_T, EOT };
items.Collect( aBoard, scanZONEs );
for( int i=0; i<items.GetCount(); ++i )
{
ZONE_CONTAINER* item = (ZONE_CONTAINER*) items[i];
if( ! item->GetIsKeepout() )
continue;
// keepout areas have a type. types are
// T_place_keepout, T_via_keepout, T_wire_keepout,
// T_bend_keepout, T_elongate_keepout, T_keepout.
// Pcbnew knows only T_keepout, T_via_keepout and T_wire_keepout
DSN_T keepout_type;
if( item->GetDoNotAllowVias() && item->GetDoNotAllowTracks() )
keepout_type = T_keepout;
else if( item->GetDoNotAllowVias() )
keepout_type = T_via_keepout;
else if( item->GetDoNotAllowTracks() )
keepout_type = T_wire_keepout;
else
keepout_type = T_keepout;
// Now, build keepout polygon on each copper layer where the item
// keepout is living (keepout zones can live on many copper layers)
const int copperCount = aBoard->GetCopperLayerCount();
for( int layer = 0; layer < copperCount; layer++ )
{
if( layer == copperCount-1)
layer = B_Cu;
if( !item->IsOnLayer( PCB_LAYER_ID( layer ) ) )
continue;
KEEPOUT* keepout = new KEEPOUT( pcb->structure, keepout_type );
pcb->structure->keepouts.push_back( keepout );
PATH* mainPolygon = new PATH( keepout, T_polygon );
keepout->SetShape( mainPolygon );
mainPolygon->layer_id = layerIds[ kicadLayer2pcb[ layer ] ];
// Handle the main outlines
SHAPE_POLY_SET::ITERATOR iterator;
bool is_first_point = true;
wxPoint startpoint;
for( iterator = item->IterateWithHoles(); iterator; iterator++ )
{
wxPoint point( iterator->x, iterator->y );
if( is_first_point )
{
startpoint = point;
is_first_point = false;
}
mainPolygon->AppendPoint( mapPt(point) );
// this was the end of the main polygon
if( iterator.IsEndContour() )
{
mainPolygon->AppendPoint( mapPt( startpoint ) );
break;
}
}
WINDOW* window = nullptr;
PATH* cutout = nullptr;
bool isStartContour = true;
// handle the cutouts
for( iterator++; iterator; iterator++ )
{
if( isStartContour )
{
is_first_point = true;
window = new WINDOW( keepout );
keepout->AddWindow( window );
cutout = new PATH( window, T_polygon );
window->SetShape( cutout );
cutout->layer_id = layerIds[ kicadLayer2pcb[ item->GetLayer() ] ];
}
isStartContour = iterator.IsEndContour();
wxASSERT( window );
wxASSERT( cutout );
wxPoint point(iterator->x, iterator->y );
if( is_first_point )
{
startpoint = point;
is_first_point = false;
}
cutout->AppendPoint( mapPt(point) );
// Close the polygon
if( iterator.IsEndContour() )
cutout->AppendPoint( mapPt( startpoint ) );
}
}
}
}
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2008-02-14 01:07:52 +00:00
//-----<build the images, components, and netlist>-----------------------
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{
PIN_REF empty( pcb->network );
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std::string componentId;
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// find the highest numbered netCode within the board.
int highestNetCode = aBoard->GetNetCount() - 1;
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deleteNETs();
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2008-02-14 01:07:52 +00:00
// expand the net vector to highestNetCode+1, setting empty to NULL
nets.resize( highestNetCode + 1, NULL );
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for( unsigned i = 1 /* skip "No Net" at [0] */; i < nets.size(); ++i )
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nets[i] = new NET( pcb->network );
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for( unsigned ii = 0; ii < aBoard->GetNetCount(); ii++ )
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{
NETINFO_ITEM* net = aBoard->FindNet( ii );
int netcode = net->GetNet();
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if( netcode > 0 )
nets[ netcode ]->net_id = TO_UTF8( net->GetNetname() );
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}
2008-02-07 20:23:58 +00:00
2008-01-24 21:47:54 +00:00
items.Collect( aBoard, scanMODULEs );
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padstackset.clear();
for( int m = 0; m<items.GetCount(); ++m )
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{
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MODULE* module = (MODULE*) items[m];
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IMAGE* image = makeIMAGE( aBoard, module );
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componentId = TO_UTF8( module->GetReference() );
2008-02-29 06:49:34 +00:00
2008-02-14 01:07:52 +00:00
// create a net list entry for all the actual pins in the image
// for the current module. location of this code is critical
// because we fabricated some pin names to ensure unique-ness
2008-02-29 06:49:34 +00:00
// of pin names within a module, do not move this code because
// the life of this 'IMAGE* image' is not necessarily long. The
2008-02-14 01:07:52 +00:00
// exported netlist will have some fabricated pin names in it.
// If you don't like fabricated pin names, then make sure all pads
// within your MODULEs are uniquely named!
for( unsigned p = 0; p<image->pins.size(); ++p )
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{
PIN* pin = &image->pins[p];
int netcode = pin->kiNetCode;
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if( netcode > 0 )
{
NET* net = nets[netcode];
net->pins.push_back( empty );
PIN_REF& pin_ref = net->pins.back();
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pin_ref.component_id = componentId;
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pin_ref.pin_id = pin->pin_id;
}
}
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IMAGE* registered = pcb->library->LookupIMAGE( image );
if( registered != image )
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{
// If our new 'image' is not a unique IMAGE, delete it.
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// and use the registered one, known as 'image' after this.
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delete image;
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image = registered;
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}
COMPONENT* comp = pcb->placement->LookupCOMPONENT( image->GetImageId() );
PLACE* place = new PLACE( comp );
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comp->places.push_back( place );
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place->SetRotation( module->GetOrientationDegrees() );
place->SetVertex( mapPt( module->GetPosition() ) );
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place->component_id = componentId;
place->part_number = TO_UTF8( module->GetValue() );
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// module is flipped from bottom side, set side to T_back
if( module->GetFlag() )
2008-02-05 02:13:16 +00:00
{
double angle = 180.0 - module->GetOrientationDegrees();
NORMALIZE_ANGLE_DEGREES_POS( angle );
place->SetRotation( angle );
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place->side = T_back;
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}
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}
2008-02-07 20:23:58 +00:00
2008-02-14 01:07:52 +00:00
// copy the SPECCTRA_DB::padstackset to the LIBRARY. Since we are
// removing, do not increment the iterator
for( PADSTACKSET::iterator i = padstackset.begin(); i!=padstackset.end();
i = padstackset.begin() )
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{
PADSTACKSET::auto_type ps = padstackset.release( i );
PADSTACK* padstack = ps.release();
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2008-02-14 01:07:52 +00:00
pcb->library->AddPadstack( padstack );
}
2008-02-07 20:23:58 +00:00
2008-02-14 01:07:52 +00:00
// copy our SPECCTRA_DB::nets to the pcb->network
for( unsigned n = 1; n<nets.size(); ++n )
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{
NET* net = nets[n];
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if( net->pins.size() )
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{
// give ownership to pcb->network
pcb->network->nets.push_back( net );
nets[n] = 0;
}
}
}
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//-----< output vias used in netclasses >-----------------------------------
2008-02-14 01:07:52 +00:00
{
NETCLASSES& nclasses = aBoard->GetDesignSettings().m_NetClasses;
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// Assume the netclass vias are all the same kind of thru, blind, or buried vias.
// This is in lieu of either having each netclass via have its own layer pair in
// the netclass dialog, or such control in the specctra export dialog.
// if( aBoard->GetDesignSettings().m_CurrentViaType == VIA_THROUGH )
{
m_top_via_layer = 0; // first specctra cu layer is number zero.
m_bot_via_layer = aBoard->GetCopperLayerCount()-1;
}
/*
else
{
// again, should be in the BOARD:
topLayer = kicadLayer2pcb[ GetScreen()->m_Route_Layer_TOP ];
botLayer = kicadLayer2pcb[ GetScreen()->m_Route_Layer_BOTTOM ];
}
*/
// Add the via from the Default netclass first. The via container
// in pcb->library preserves the sequence of addition.
2008-02-14 01:07:52 +00:00
NETCLASSPTR netclass = nclasses.GetDefault();
PADSTACK* via = makeVia( netclass->GetViaDiameter(), netclass->GetViaDrill(),
m_top_via_layer, m_bot_via_layer );
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// we AppendVia() this first one, there is no way it can be a duplicate,
// the pcb->library via container is empty at this point. After this,
// we'll have to use LookupVia().
wxASSERT( pcb->library->vias.size() == 0 );
pcb->library->AppendVia( via );
#if 0
// I've seen no way to make stock vias useable by freerouter. Also the
// zero based diameter was leading to duplicates in the LookupVia() function.
// User should use netclass based vias when going to freerouter.
// Output the stock vias, but preserve uniqueness in the via container by
// using LookupVia().
for( unsigned i = 0; i < aBoard->m_ViasDimensionsList.size(); ++i )
{
int viaSize = aBoard->m_ViasDimensionsList[i].m_Diameter;
int viaDrill = aBoard->m_ViasDimensionsList[i].m_Drill;
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via = makeVia( viaSize, viaDrill,
m_top_via_layer, m_bot_via_layer );
// maybe add 'via' to the library, but only if unique.
PADSTACK* registered = pcb->library->LookupVia( via );
if( registered != via )
delete via;
}
#endif
// set the "spare via" index at the start of the
// pcb->library->spareViaIndex = pcb->library->vias.size();
// output the non-Default netclass vias
for( NETCLASSES::iterator nc = nclasses.begin(); nc != nclasses.end(); ++nc )
{
netclass = nc->second;
via = makeVia( netclass->GetViaDiameter(), netclass->GetViaDrill(),
m_top_via_layer, m_bot_via_layer );
// maybe add 'via' to the library, but only if unique.
PADSTACK* registered = pcb->library->LookupVia( via );
if( registered != via )
delete via;
}
}
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2008-02-14 01:07:52 +00:00
#if 1 // do existing wires and vias
2008-01-30 19:16:46 +00:00
//-----<create the wires from tracks>-----------------------------------
{
// export all of them for now, later we'll decide what controls we need
// on this.
static const KICAD_T scanTRACKs[] = { PCB_TRACE_T, EOT };
2008-02-07 20:23:58 +00:00
2008-01-30 19:16:46 +00:00
items.Collect( aBoard, scanTRACKs );
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2008-02-07 20:23:58 +00:00
std::string netname;
2008-01-31 06:46:31 +00:00
WIRING* wiring = pcb->wiring;
PATH* path = 0;
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2008-02-07 20:23:58 +00:00
int old_netcode = -1;
int old_width = -1;
LAYER_NUM old_layer = UNDEFINED_LAYER;
2008-01-31 01:30:52 +00:00
2008-01-30 19:16:46 +00:00
for( int i=0; i<items.GetCount(); ++i )
{
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TRACK* track = (TRACK*) items[i];
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int netcode = track->GetNetCode();
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if( netcode == 0 )
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continue;
2015-11-11 18:47:51 +00:00
if( old_netcode != netcode ||
old_width != track->GetWidth() ||
old_layer != track->GetLayer() ||
(path && path->points.back() != mapPt(track->GetStart()) )
2008-02-07 20:23:58 +00:00
)
2008-01-31 01:30:52 +00:00
{
old_width = track->GetWidth();
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old_layer = track->GetLayer();
2008-01-31 01:30:52 +00:00
2008-02-29 06:49:34 +00:00
if( old_netcode != netcode )
2008-01-31 01:30:52 +00:00
{
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old_netcode = netcode;
NETINFO_ITEM* net = aBoard->FindNet( netcode );
wxASSERT( net );
netname = TO_UTF8( net->GetNetname() );
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}
2008-01-31 06:46:31 +00:00
WIRE* wire = new WIRE( wiring );
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wiring->wires.push_back( wire );
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wire->net_id = netname;
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wire->wire_type = T_protect; // @todo, this should be configurable
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LAYER_NUM kiLayer = track->GetLayer();
int pcbLayer = kicadLayer2pcb[kiLayer];
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2008-01-31 06:46:31 +00:00
path = new PATH( wire );
2008-01-31 06:46:31 +00:00
wire->SetShape( path );
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2008-01-31 06:46:31 +00:00
path->layer_id = layerIds[pcbLayer];
path->aperture_width = scale( old_width );
path->AppendPoint( mapPt( track->GetStart() ) );
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}
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2015-11-11 18:47:51 +00:00
if( path ) // Should not occur
path->AppendPoint( mapPt( track->GetEnd() ) );
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}
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}
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2008-02-09 08:34:45 +00:00
//-----<export the existing real BOARD instantiated vias>-----------------
2008-02-01 01:09:39 +00:00
{
// Export all vias, once per unique size and drill diameter combo.
static const KICAD_T scanVIAs[] = { PCB_VIA_T, EOT };
2008-02-07 20:23:58 +00:00
2008-02-01 01:09:39 +00:00
items.Collect( aBoard, scanVIAs );
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for( int i = 0; i<items.GetCount(); ++i )
2008-02-01 01:09:39 +00:00
{
::VIA* via = (::VIA*) items[i];
wxASSERT( via->Type() == PCB_VIA_T );
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int netcode = via->GetNetCode();
2008-02-21 06:04:32 +00:00
if( netcode == 0 )
continue;
PADSTACK* padstack = makeVia( via );
PADSTACK* registered = pcb->library->LookupVia( padstack );
// if the one looked up is not our padstack, then delete our padstack
// since it was a duplicate of one already registered.
2008-02-01 01:09:39 +00:00
if( padstack != registered )
{
delete padstack;
}
WIRE_VIA* dsnVia = new WIRE_VIA( pcb->wiring );
2008-02-01 01:09:39 +00:00
pcb->wiring->wire_vias.push_back( dsnVia );
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2008-02-01 01:09:39 +00:00
dsnVia->padstack_id = registered->padstack_id;
dsnVia->vertexes.push_back( mapPt( via->GetPosition() ) );
2008-02-07 20:23:58 +00:00
NETINFO_ITEM* net = aBoard->FindNet( netcode );
wxASSERT( net );
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dsnVia->net_id = TO_UTF8( net->GetNetname() );
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2008-02-21 06:04:32 +00:00
dsnVia->via_type = T_protect; // @todo, this should be configurable
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}
}
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#endif // do existing wires and vias
2008-02-07 20:23:58 +00:00
2008-02-01 01:09:39 +00:00
//-----<via_descriptor>-------------------------------------------------
{
// The pcb->library will output <padstack_descriptors> which is a combined
// list of part padstacks and via padstacks. specctra dsn uses the
// <via_descriptors> to say which of those padstacks are vias.
// Output the vias in the padstack list here, by name only. This must
2008-02-01 01:09:39 +00:00
// be done after exporting existing vias as WIRE_VIAs.
VIA* vias = pcb->structure->via;
2008-02-01 01:09:39 +00:00
for( unsigned viaNdx = 0; viaNdx < pcb->library->vias.size(); ++viaNdx )
2008-02-01 01:09:39 +00:00
{
vias->AppendVia( pcb->library->vias[viaNdx].padstack_id.c_str() );
2008-02-01 01:09:39 +00:00
}
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}
2008-02-01 01:09:39 +00:00
2008-02-07 20:23:58 +00:00
2009-09-10 15:22:26 +00:00
//-----<output NETCLASSs>----------------------------------------------------
NETCLASSES& nclasses = aBoard->GetDesignSettings().m_NetClasses;
2009-09-10 15:22:26 +00:00
exportNETCLASS( nclasses.GetDefault(), aBoard );
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for( NETCLASSES::iterator nc = nclasses.begin(); nc != nclasses.end(); ++nc )
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{
NETCLASSPTR netclass = nc->second;
exportNETCLASS( netclass, aBoard );
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}
}
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void SPECCTRA_DB::exportNETCLASS( const NETCLASSPTR& aNetClass, BOARD* aBoard )
2009-09-10 15:22:26 +00:00
{
/* From page 11 of specctra spec:
*
* Routing and Placement Rule Hierarchies
*
* Routing and placement rules can be defined at multiple levels of design
* specification. When a routing or placement rule is defined for an object at
* multiple levels, a predefined routing or placement precedence order
* automatically determines which rule to apply to the object. The routing rule
* precedence order is
*
* pcb < layer < class < class layer < group_set < group_set layer < net <
* net layer < group < group layer < fromto < fromto layer < class_class <
* class_class layer < padstack < region < class region < net region <
* class_class region
*
* A pcb rule (global rule for the PCB design) has the lowest precedence in the
* hierarchy. A class-to-class region rule has the highest precedence. Rules
* set at one level of the hierarchy override conflicting rules set at lower
* levels. The placement rule precedence order is
*
* pcb < image_set < image < component < super cluster < room <
* room_image_set < family_family < image_image
*
* A pcb rule (global rule for the PCB design) has the lowest precedence in the
* hierarchy. An image-to-image rule has the highest precedence. Rules set at
* one level of the hierarchy override conflicting rules set at lower levels.
*/
char text[256];
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2009-09-10 15:22:26 +00:00
CLASS* clazz = new CLASS( pcb->network );
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pcb->network->classes.push_back( clazz );
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// freerouter creates a class named 'default' anyway, and if we
// try and use that, we end up with two 'default' via rules so use
// something else as the name of our default class.
clazz->class_id = TO_UTF8( aNetClass->GetName() );
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for( NETCLASS::iterator net = aNetClass->begin(); net != aNetClass->end(); ++net )
clazz->net_ids.push_back( TO_UTF8( *net ) );
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clazz->rules = new RULE( clazz, T_rule );
// output the track width.
int trackWidth = aNetClass->GetTrackWidth();
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sprintf( text, "(width %.6g)", scale( trackWidth ) );
clazz->rules->rules.push_back( text );
// output the clearance.
int clearance = aNetClass->GetClearance();
sprintf( text, "(clearance %.6g)", scale( clearance ) + safetyMargin );
clazz->rules->rules.push_back( text );
if( aNetClass->GetName() == NETCLASS::Default )
{
clazz->class_id = "kicad_default";
}
// the easiest way to get the via name is to create a via (which generates
// the name internal to the PADSTACK), and then grab the name and then
// delete the via. There are not that many netclasses so
// this should never become a performance issue.
PADSTACK* via = makeVia( aNetClass->GetViaDiameter(), aNetClass->GetViaDrill(),
m_top_via_layer, m_bot_via_layer );
snprintf( text, sizeof(text), "(use_via %s)", via->GetPadstackId().c_str() );
clazz->circuit.push_back( text );
delete via;
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}
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void SPECCTRA_DB::FlipMODULEs( BOARD* aBoard )
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{
for( auto module : aBoard->Modules() )
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{
module->SetFlag( 0 );
if( module->GetLayer() == B_Cu )
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{
module->Flip( module->GetPosition(), aBoard->GeneralSettings().m_FlipLeftRight );
module->SetFlag( 1 );
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}
}
modulesAreFlipped = true;
}
void SPECCTRA_DB::RevertMODULEs( BOARD* aBoard )
{
if( !modulesAreFlipped )
return;
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// DSN Images (=KiCad MODULES and pads) must be presented from the
// top view. Restore those that were flipped.
for( auto module : aBoard->Modules() )
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{
if( module->GetFlag() )
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{
module->Flip( module->GetPosition(), aBoard->GeneralSettings().m_FlipLeftRight );
module->SetFlag( 0 );
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}
}
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modulesAreFlipped = false;
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}
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} // namespace DSN