kicad/pcbnew/pcb_track.cpp

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2012 Jean-Pierre Charras, jp.charras at wanadoo.fr
* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
* Copyright (C) 2012 Wayne Stambaugh <stambaughw@gmail.com>
* Copyright (C) 1992-2021 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
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#include <pcb_base_frame.h>
#include <connectivity/connectivity_data.h>
#include <board.h>
#include <board_design_settings.h>
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#include <pcb_track.h>
#include <base_units.h>
#include <bitmaps.h>
#include <kicad_string.h>
#include <view/view.h>
#include <settings/color_settings.h>
#include <settings/settings_manager.h>
#include <i18n_utility.h>
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#include <geometry/seg.h>
#include <geometry/shape_segment.h>
#include <geometry/shape_circle.h>
#include <geometry/shape_arc.h>
#include <drc/drc_engine.h>
#include <pcb_painter.h>
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#include <trigo.h>
using KIGFX::PCB_PAINTER;
using KIGFX::PCB_RENDER_SETTINGS;
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PCB_TRACK::PCB_TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) :
BOARD_CONNECTED_ITEM( aParent, idtype )
{
m_Width = Millimeter2iu( 0.2 ); // Gives a reasonable default width
}
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EDA_ITEM* PCB_TRACK::Clone() const
{
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return new PCB_TRACK( *this );
}
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PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
PCB_TRACK( aParent, PCB_ARC_T )
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{
m_Start = wxPoint( aArc->GetP0() );
m_End = wxPoint( aArc->GetP1() );
m_Mid = wxPoint( aArc->GetArcMid() );
}
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EDA_ITEM* PCB_ARC::Clone() const
{
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return new PCB_ARC( *this );
}
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PCB_VIA::PCB_VIA( BOARD_ITEM* aParent ) :
PCB_TRACK( aParent, PCB_VIA_T )
{
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SetViaType( VIATYPE::THROUGH );
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m_bottomLayer = B_Cu;
SetDrillDefault();
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m_removeUnconnectedLayer = false;
m_keepTopBottomLayer = true;
m_isFree = false;
}
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EDA_ITEM* PCB_VIA::Clone() const
{
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return new PCB_VIA( *this );
}
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wxString PCB_VIA::GetSelectMenuText( EDA_UNITS aUnits ) const
{
wxString formatStr;
switch( GetViaType() )
{
case VIATYPE::BLIND_BURIED: formatStr = _( "Blind/Buried Via %s on %s" ); break;
case VIATYPE::MICROVIA: formatStr = _( "Micro Via %s on %s" ); break;
default: formatStr = _( "Via %s on %s" ); break;
}
return wxString::Format( formatStr,
GetNetnameMsg(),
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layerMaskDescribe() );
}
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BITMAPS PCB_VIA::GetMenuImage() const
{
return BITMAPS::via;
}
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bool PCB_TRACK::ApproxCollinear( const PCB_TRACK& aTrack )
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{
SEG a( m_Start, m_End );
SEG b( aTrack.GetStart(), aTrack.GetEnd() );
return a.ApproxCollinear( b );
}
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int PCB_TRACK::GetLocalClearance( wxString* aSource ) const
{
// Not currently implemented
return 0;
}
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void PCB_TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const
{
*aMin = 0;
*aMax = INT_MAX;
DRC_CONSTRAINT constraint;
if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
{
BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, GetLayer() );
}
if( constraint.Value().HasMin() || constraint.Value().HasMax() )
{
if( constraint.Value().HasMin() )
*aMin = constraint.Value().Min();
if( constraint.Value().HasMax() )
*aMax = constraint.Value().Max();
if( aSource )
*aSource = constraint.GetName();
}
}
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int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
{
if( !FlashLayer( aLayer ) )
{
if( aSource )
*aSource = _( "removed annular ring" );
return 0;
}
DRC_CONSTRAINT constraint;
if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
{
BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer );
}
if( constraint.Value().HasMin() )
{
if( aSource )
*aSource = constraint.GetName();
return constraint.Value().Min();
}
return 0;
}
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int PCB_VIA::GetDrillValue() const
{
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if( m_drill > 0 ) // Use the specific value.
return m_drill;
// Use the default value from the Netclass
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NETCLASS* netclass = GetNetClass();
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if( GetViaType() == VIATYPE::MICROVIA )
return netclass->GetuViaDrill();
return netclass->GetViaDrill();
}
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EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) const
{
EDA_ITEM_FLAGS result = 0;
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if( min_dist < 0 )
min_dist = m_Width / 2;
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if( min_dist == 0 )
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{
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if( m_Start == point )
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result |= STARTPOINT;
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if( m_End == point )
result |= ENDPOINT;
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}
else
{
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double dist = GetLineLength( m_Start, point );
if( min_dist >= KiROUND( dist ) )
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result |= STARTPOINT;
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dist = GetLineLength( m_End, point );
if( min_dist >= KiROUND( dist ) )
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result |= ENDPOINT;
}
return result;
}
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const EDA_RECT PCB_TRACK::GetBoundingBox() const
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{
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// end of track is round, this is its radius, rounded up
int radius = ( m_Width + 1 ) / 2;
int ymax, xmax, ymin, xmin;
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if( Type() == PCB_VIA_T )
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{
ymax = m_Start.y;
xmax = m_Start.x;
ymin = m_Start.y;
xmin = m_Start.x;
}
else if( Type() == PCB_ARC_T )
{
std::shared_ptr<SHAPE> arc = GetEffectiveShape();
auto bbox = arc->BBox();
xmin = bbox.GetLeft();
xmax = bbox.GetRight();
ymin = bbox.GetTop();
ymax = bbox.GetBottom();
}
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else
{
ymax = std::max( m_Start.y, m_End.y );
xmax = std::max( m_Start.x, m_End.x );
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ymin = std::min( m_Start.y, m_End.y );
xmin = std::min( m_Start.x, m_End.x );
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}
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ymax += radius;
xmax += radius;
ymin -= radius;
xmin -= radius;
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// return a rectangle which is [pos,dim) in nature. therefore the +1
EDA_RECT ret( wxPoint( xmin, ymin ), wxSize( xmax - xmin + 1, ymax - ymin + 1 ) );
return ret;
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}
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double PCB_TRACK::GetLength() const
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{
return GetLineLength( m_Start, m_End );
}
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void PCB_TRACK::Rotate( const wxPoint& aRotCentre, double aAngle )
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{
RotatePoint( &m_Start, aRotCentre, aAngle );
RotatePoint( &m_End, aRotCentre, aAngle );
}
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void PCB_ARC::Rotate( const wxPoint& aRotCentre, double aAngle )
{
RotatePoint( &m_Start, aRotCentre, aAngle );
RotatePoint( &m_End, aRotCentre, aAngle );
RotatePoint( &m_Mid, aRotCentre, aAngle );
}
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void PCB_TRACK::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
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{
if( aFlipLeftRight )
{
m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
m_End.x = aCentre.x - ( m_End.x - aCentre.x );
}
else
{
m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
m_End.y = aCentre.y - ( m_End.y - aCentre.y );
}
int copperLayerCount = GetBoard()->GetCopperLayerCount();
SetLayer( FlipLayer( GetLayer(), copperLayerCount ) );
}
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void PCB_ARC::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
{
if( aFlipLeftRight )
{
m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
m_End.x = aCentre.x - ( m_End.x - aCentre.x );
m_Mid.x = aCentre.x - ( m_Mid.x - aCentre.x );
}
else
{
m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
m_End.y = aCentre.y - ( m_End.y - aCentre.y );
m_Mid.y = aCentre.y - ( m_Mid.y - aCentre.y );
}
int copperLayerCount = GetBoard()->GetCopperLayerCount();
SetLayer( FlipLayer( GetLayer(), copperLayerCount ) );
}
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void PCB_VIA::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
{
if( aFlipLeftRight )
{
m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
m_End.x = aCentre.x - ( m_End.x - aCentre.x );
}
else
{
m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
m_End.y = aCentre.y - ( m_End.y - aCentre.y );
}
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if( GetViaType() != VIATYPE::THROUGH )
{
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int copperLayerCount = GetBoard()->GetCopperLayerCount();
PCB_LAYER_ID top_layer;
PCB_LAYER_ID bottom_layer;
LayerPair( &top_layer, &bottom_layer );
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top_layer = FlipLayer( top_layer, copperLayerCount );
bottom_layer = FlipLayer( bottom_layer, copperLayerCount );
SetLayerPair( top_layer, bottom_layer );
}
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}
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// see class_track.h
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SEARCH_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData, const KICAD_T scanTypes[] )
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{
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KICAD_T stype = *scanTypes;
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// If caller wants to inspect my type
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if( stype == Type() )
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{
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if( SEARCH_RESULT::QUIT == inspector( this, testData ) )
return SEARCH_RESULT::QUIT;
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}
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return SEARCH_RESULT::CONTINUE;
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}
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bool PCB_VIA::IsOnLayer( PCB_LAYER_ID layer_number ) const
{
PCB_LAYER_ID bottom_layer, top_layer;
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* KIWAY Milestone A): Make major modules into DLL/DSOs. ! The initial testing of this commit should be done using a Debug build so that all the wxASSERT()s are enabled. Also, be sure and keep enabled the USE_KIWAY_DLLs option. The tree won't likely build without it. Turning it off is senseless anyways. If you want stable code, go back to a prior version, the one tagged with "stable". * Relocate all functionality out of the wxApp derivative into more finely targeted purposes: a) DLL/DSO specific b) PROJECT specific c) EXE or process specific d) configuration file specific data e) configuration file manipulations functions. All of this functionality was blended into an extremely large wxApp derivative and that was incompatible with the desire to support multiple concurrently loaded DLL/DSO's ("KIFACE")s and multiple concurrently open projects. An amazing amount of organization come from simply sorting each bit of functionality into the proper box. * Switch to wxConfigBase from wxConfig everywhere except instantiation. * Add classes KIWAY, KIFACE, KIFACE_I, SEARCH_STACK, PGM_BASE, PGM_KICAD, PGM_SINGLE_TOP, * Remove "Return" prefix on many function names. * Remove obvious comments from CMakeLists.txt files, and from else() and endif()s. * Fix building boost for use in a DSO on linux. * Remove some of the assumptions in the CMakeLists.txt files that windows had to be the host platform when building windows binaries. * Reduce the number of wxStrings being constructed at program load time via static construction. * Pass wxConfigBase* to all SaveSettings() and LoadSettings() functions so that these functions are useful even when the wxConfigBase comes from another source, as is the case in the KICAD_MANAGER_FRAME. * Move the setting of the KIPRJMOD environment variable into class PROJECT, so that it can be moved into a project variable soon, and out of FP_LIB_TABLE. * Add the KIWAY_PLAYER which is associated with a particular PROJECT, and all its child wxFrames and wxDialogs now have a Kiway() member function which returns a KIWAY& that that window tree branch is in support of. This is like wxWindows DNA in that child windows get this member with proper value at time of construction. * Anticipate some of the needs for milestones B) and C) and make code adjustments now in an effort to reduce work in those milestones. * No testing has been done for python scripting, since milestone C) has that being largely reworked and re-thought-out.
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LayerPair( &top_layer, &bottom_layer );
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wxASSERT( top_layer <= bottom_layer );
if( top_layer <= layer_number && layer_number <= bottom_layer )
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return true;
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else
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return false;
}
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LSET PCB_VIA::GetLayerSet() const
{
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if( GetViaType() == VIATYPE::THROUGH )
return LSET::AllCuMask();
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// VIA_BLIND_BURIED or VIA_MICRVIA:
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LSET layermask;
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wxASSERT( m_layer <= m_bottomLayer );
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// PCB_LAYER_IDs are numbered from front to back, this is top to bottom.
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for( LAYER_NUM id = m_layer; id <= m_bottomLayer; ++id )
{
layermask.set( id );
}
return layermask;
}
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void PCB_VIA::SetLayerSet( LSET aLayerSet )
{
bool first = true;
for( PCB_LAYER_ID layer : aLayerSet.Seq() )
{
if( first )
{
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m_layer = layer;
first = false;
}
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m_bottomLayer = layer;
}
}
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void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
{
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m_layer = aTopLayer;
m_bottomLayer = aBottomLayer;
SanitizeLayers();
}
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void PCB_VIA::SetTopLayer( PCB_LAYER_ID aLayer )
{
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m_layer = aLayer;
}
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void PCB_VIA::SetBottomLayer( PCB_LAYER_ID aLayer )
{
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m_bottomLayer = aLayer;
}
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void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
{
PCB_LAYER_ID t_layer = F_Cu;
PCB_LAYER_ID b_layer = B_Cu;
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if( GetViaType() != VIATYPE::THROUGH )
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{
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b_layer = m_bottomLayer;
t_layer = m_layer;
if( b_layer < t_layer )
std::swap( b_layer, t_layer );
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}
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if( top_layer )
*top_layer = t_layer;
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if( bottom_layer )
*bottom_layer = b_layer;
}
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PCB_LAYER_ID PCB_VIA::TopLayer() const
{
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return m_layer;
}
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PCB_LAYER_ID PCB_VIA::BottomLayer() const
{
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return m_bottomLayer;
}
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void PCB_VIA::SanitizeLayers()
{
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if( GetViaType() == VIATYPE::THROUGH )
{
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m_layer = F_Cu;
m_bottomLayer = B_Cu;
}
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if( m_bottomLayer < m_layer )
std::swap( m_bottomLayer, m_layer );
}
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bool PCB_VIA::FlashLayer( LSET aLayers ) const
{
for( auto layer : aLayers.Seq() )
{
if( FlashLayer( layer ) )
return true;
}
return false;
}
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bool PCB_VIA::FlashLayer( int aLayer ) const
{
std::vector<KICAD_T> types
{ PCB_TRACE_T, PCB_ARC_T, PCB_PAD_T, PCB_ZONE_T, PCB_FP_ZONE_T };
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// Return the "normal" shape if the caller doesn't specify a particular layer
if( aLayer == UNDEFINED_LAYER )
return true;
BOARD* board = GetBoard();
if( !board )
return false;
if( !IsOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) ) )
return false;
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if( !m_removeUnconnectedLayer )
return true;
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if( m_keepTopBottomLayer && ( aLayer == m_layer || aLayer == m_bottomLayer ) )
return true;
return board->GetConnectivity()->IsConnectedOnLayer( this, static_cast<int>( aLayer ),
types );
}
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void PCB_TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
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{
// Show the track and its netname on different layers
aLayers[0] = GetLayer();
aLayers[1] = GetNetnameLayer( aLayers[0] );
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aCount = 2;
}
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double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
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{
constexpr double HIDE = std::numeric_limits<double>::max();
PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
if( !aView->IsLayerVisible( LAYER_TRACKS ) )
return HIDE;
if( IsNetnameLayer( aLayer ) )
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{
// Hide netnames on dimmed tracks
if( renderSettings->GetHighContrast() )
{
if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
return HIDE;
}
// Netnames will be shown only if zoom is appropriate
return ( double ) Millimeter2iu( 4 ) / ( m_Width + 1 );
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}
// Other layers are shown without any conditions
return 0.0;
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}
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const BOX2I PCB_TRACK::ViewBBox() const
{
BOX2I bbox = GetBoundingBox();
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BOARD* board = GetBoard();
if( board )
bbox.Inflate( 2 * board->GetDesignSettings().GetBiggestClearanceValue() );
return bbox;
}
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void PCB_VIA::ViewGetLayers( int aLayers[], int& aCount ) const
Introduction of Graphics Abstraction Layer based rendering for pcbnew. New classes: - VIEW - represents view that is seen by user, takes care of layer ordering & visibility and how it is displayed (which location, how much zoomed, etc.) - VIEW_ITEM - Base class for every item that can be displayed on VIEW (the biggest change is that now it may be necessary to override ViewBBox & ViewGetLayers method for derived classes). - EDA_DRAW_PANEL_GAL - Inherits after EDA_DRAW_PANEL, displays VIEW output, right now it is not editable (in opposite to usual EDA_DRAW_PANEL). - GAL/OPENGL_GAL/CAIRO_GAL - Base Graphics Abstraction Layer class + two different flavours (Cairo is not fully supported yet), that offers methods to draw primitives using different libraries. - WX_VIEW_CONTROLS - Controller for VIEW, handles user events, allows zooming, panning, etc. - PAINTER/PCB_PAINTER - Classes that uses GAL interface to draw items (as you may have already guessed - PCB_PAINTER is a class for drawing PCB specific object, PAINTER is an abstract class). Its methods are invoked by VIEW, when an item has to be drawn. To display a new type of item - you need to implement draw(ITEM_TYPE*) method that draws it using GAL methods. - STROKE_FONT - Implements stroke font drawing using GAL methods. Most important changes to Kicad original code: * EDA_ITEM now inherits from VIEW_ITEM, which is a base class for all drawable objects. * EDA_DRAW_FRAME contains both usual EDA_DRAW_PANEL and new EDA_DRAW_PANEL_GAL, that can be switched anytime. * There are some new layers for displaying multilayer pads, vias & pads holes (these are not shown yet on the right sidebar in pcbnew) * Display order of layers is different than in previous versions (if you are curious - you may check m_galLayerOrder@pcbnew/basepcbframe.cpp). Preserving usual order would result in not very natural display, such as showing silkscreen texts on the bottom. * Introduced new hotkey (Alt+F12) and new menu option (View->Switch canvas) for switching canvas during runtime. * Some of classes (mostly derived from BOARD_ITEM) now includes ViewBBox & ViewGetLayers methods. * Removed tools/class_painter.h, as now it is extended and included in source code. Build changes: * GAL-based rendering option is turned on by a new compilation CMake option KICAD_GAL. * When compiling with CMake option KICAD_GAL=ON, GLEW and Cairo libraries are required. * GAL-related code is compiled into a static library (common/libgal). * Build with KICAD_GAL=OFF should not need any new libraries and should come out as a standard version of Kicad Currently most of items in pcbnew can be displayed using OpenGL (to be done are DIMENSIONS and MARKERS). More details about GAL can be found in: http://www.ohwr.org/attachments/1884/view-spec.pdf
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{
aLayers[0] = LAYER_VIA_HOLES;
aLayers[1] = LAYER_VIA_HOLEWALLS;
aLayers[2] = LAYER_VIA_NETNAMES;
// Just show it on common via & via holes layers
switch( GetViaType() )
{
case VIATYPE::THROUGH: aLayers[3] = LAYER_VIA_THROUGH; break;
case VIATYPE::BLIND_BURIED: aLayers[3] = LAYER_VIA_BBLIND; break;
case VIATYPE::MICROVIA: aLayers[3] = LAYER_VIA_MICROVIA; break;
default: aLayers[3] = LAYER_GP_OVERLAY; break;
}
aCount = 4;
Introduction of Graphics Abstraction Layer based rendering for pcbnew. New classes: - VIEW - represents view that is seen by user, takes care of layer ordering & visibility and how it is displayed (which location, how much zoomed, etc.) - VIEW_ITEM - Base class for every item that can be displayed on VIEW (the biggest change is that now it may be necessary to override ViewBBox & ViewGetLayers method for derived classes). - EDA_DRAW_PANEL_GAL - Inherits after EDA_DRAW_PANEL, displays VIEW output, right now it is not editable (in opposite to usual EDA_DRAW_PANEL). - GAL/OPENGL_GAL/CAIRO_GAL - Base Graphics Abstraction Layer class + two different flavours (Cairo is not fully supported yet), that offers methods to draw primitives using different libraries. - WX_VIEW_CONTROLS - Controller for VIEW, handles user events, allows zooming, panning, etc. - PAINTER/PCB_PAINTER - Classes that uses GAL interface to draw items (as you may have already guessed - PCB_PAINTER is a class for drawing PCB specific object, PAINTER is an abstract class). Its methods are invoked by VIEW, when an item has to be drawn. To display a new type of item - you need to implement draw(ITEM_TYPE*) method that draws it using GAL methods. - STROKE_FONT - Implements stroke font drawing using GAL methods. Most important changes to Kicad original code: * EDA_ITEM now inherits from VIEW_ITEM, which is a base class for all drawable objects. * EDA_DRAW_FRAME contains both usual EDA_DRAW_PANEL and new EDA_DRAW_PANEL_GAL, that can be switched anytime. * There are some new layers for displaying multilayer pads, vias & pads holes (these are not shown yet on the right sidebar in pcbnew) * Display order of layers is different than in previous versions (if you are curious - you may check m_galLayerOrder@pcbnew/basepcbframe.cpp). Preserving usual order would result in not very natural display, such as showing silkscreen texts on the bottom. * Introduced new hotkey (Alt+F12) and new menu option (View->Switch canvas) for switching canvas during runtime. * Some of classes (mostly derived from BOARD_ITEM) now includes ViewBBox & ViewGetLayers methods. * Removed tools/class_painter.h, as now it is extended and included in source code. Build changes: * GAL-based rendering option is turned on by a new compilation CMake option KICAD_GAL. * When compiling with CMake option KICAD_GAL=ON, GLEW and Cairo libraries are required. * GAL-related code is compiled into a static library (common/libgal). * Build with KICAD_GAL=OFF should not need any new libraries and should come out as a standard version of Kicad Currently most of items in pcbnew can be displayed using OpenGL (to be done are DIMENSIONS and MARKERS). More details about GAL can be found in: http://www.ohwr.org/attachments/1884/view-spec.pdf
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}
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double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
{
constexpr double HIDE = (double)std::numeric_limits<double>::max();
PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
BOARD* board = GetBoard();
LSET visible = LSET::AllLayersMask();
// Meta control for hiding all vias
if( !aView->IsLayerVisible( LAYER_VIAS ) )
return HIDE;
// Handle board visibility
if( board )
visible = board->GetVisibleLayers() & board->GetEnabledLayers();
if( IsViaPadLayer( aLayer ) )
{
if( !FlashLayer( visible ) )
return HIDE;
}
else if( IsHoleLayer( aLayer ) )
{
if( m_viaType == VIATYPE::BLIND_BURIED || m_viaType == VIATYPE::MICROVIA )
{
// Show a blind or micro via's hole if it crosses a visible layer
if( !( visible & GetLayerSet() ).any() )
return HIDE;
}
else
{
// Show a through via's hole if any physical layer is shown
if( !( visible & LSET::PhysicalLayersMask() ).any() )
return HIDE;
}
}
else if( IsNetnameLayer( aLayer ) )
{
if( renderSettings->GetHighContrast() )
{
// Hide netnames unless via is flashed to a high-contrast layer
if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
return HIDE;
}
else
{
// Hide netnames unless pad is flashed to a visible layer
if( !FlashLayer( visible ) )
return HIDE;
}
// Netnames will be shown only if zoom is appropriate
return m_Width == 0 ? HIDE : ( (double)Millimeter2iu( 10 ) / m_Width );
}
// Passed all tests; show.
return 0.0;
}
// see class_track.h
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void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
{
EDA_UNITS units = aFrame->GetUserUnits();
wxString msg;
BOARD* board = GetBoard();
aList.emplace_back( _( "Type" ),
Type() == PCB_ARC_T ? ( "Track (arc)" ) : _( "Track" ) );
GetMsgPanelInfoBase_Common( aFrame, aList );
aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
aList.emplace_back( _( "Width" ), MessageTextFromValue( units, m_Width ) );
if( Type() == PCB_ARC_T )
{
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double radius = static_cast<PCB_ARC*>( this )->GetRadius();
aList.emplace_back( _( "Radius" ), MessageTextFromValue( units, radius ) );
}
aList.emplace_back( _( "Segment Length" ), MessageTextFromValue( units, GetLength() ) );
// Display full track length (in Pcbnew)
if( board && GetNetCode() > 0 )
{
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int count;
double trackLen;
double lenPadToDie;
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std::tie( count, trackLen, lenPadToDie ) = board->GetTrackLength( *this );
aList.emplace_back( _( "Routed Length" ), MessageTextFromValue( units, trackLen ) );
if( lenPadToDie != 0 )
{
msg = MessageTextFromValue( units, lenPadToDie );
aList.emplace_back( _( "Pad To Die Length" ), msg );
msg = MessageTextFromValue( units, trackLen + lenPadToDie );
aList.emplace_back( _( "Full Length" ), msg );
}
}
wxString source;
int clearance = GetOwnClearance( GetLayer(), &source );
aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
MessageTextFromValue( units, clearance ) ),
wxString::Format( _( "(from %s)" ), source ) );
int minWidth, maxWidth;
GetWidthConstraints( &minWidth, &maxWidth, &source );
aList.emplace_back( wxString::Format( _( "Min Width: %s" ),
MessageTextFromValue( units, minWidth ) ),
wxString::Format( _( "(from %s)" ), source ) );
}
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void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
{
EDA_UNITS units = aFrame->GetUserUnits();
wxString msg;
switch( GetViaType() )
{
case VIATYPE::MICROVIA: msg = _( "Micro Via" ); break;
case VIATYPE::BLIND_BURIED: msg = _( "Blind/Buried Via" ); break;
case VIATYPE::THROUGH: msg = _( "Through Via" ); break;
default: msg = _( "Via" ); break;
}
aList.emplace_back( _( "Type" ), msg );
GetMsgPanelInfoBase_Common( aFrame, aList );
aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
msg = MessageTextFromValue( aFrame->GetUserUnits(), m_Width );
aList.emplace_back( _( "Diameter" ), msg );
msg = MessageTextFromValue( aFrame->GetUserUnits(), GetDrillValue() );
aList.emplace_back( _( "Drill" ), msg );
wxString source;
int clearance = GetOwnClearance( GetLayer(), &source );
aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
MessageTextFromValue( units, clearance ) ),
wxString::Format( _( "(from %s)" ), source ) );
int minAnnulus = GetMinAnnulus( GetLayer(), &source );
aList.emplace_back( wxString::Format( _( "Min Annular Width: %s" ),
MessageTextFromValue( units, minAnnulus ) ),
wxString::Format( _( "(from %s)" ), source ) );
}
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void PCB_TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame,
std::vector<MSG_PANEL_ITEM>& aList ) const
{
wxString msg;
aList.emplace_back( _( "Net" ), UnescapeString( GetNetname() ) );
aList.emplace_back( _( "NetClass" ), UnescapeString( GetNetClass()->GetName() ) );
#if 0 // Enable for debugging
if( GetBoard() )
{
// Display net code:
msg.Printf( wxT( "%d" ), GetNetCode() );
aList.emplace_back( _( "NetCode" ), msg );
}
// Display the flags:
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msg.Printf( wxT( "0x%08X" ), m_flags );
aList.emplace_back( wxT( "Flags" ), msg );
// Display start and end positions:
msg.Printf( wxT( "%d %d" ), m_Start.x, m_Start.y );
aList.push_back( MSG_PANEL_ITEM( wxT( "Start pos" ), msg ) );
msg.Printf( wxT( "%d %d" ), m_End.x, m_End.y );
aList.push_back( MSG_PANEL_ITEM( wxT( "End pos" ), msg ) );
#endif
// Display the State member
aList.emplace_back( _( "Status" ), IsLocked() ? _( "Locked" ) : wxT( "" ) );
}
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wxString PCB_VIA::layerMaskDescribe() const
{
BOARD* board = GetBoard();
PCB_LAYER_ID top_layer;
PCB_LAYER_ID bottom_layer;
LayerPair( &top_layer, &bottom_layer );
return board->GetLayerName( top_layer ) + wxT( " - " ) + board->GetLayerName( bottom_layer );
}
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bool PCB_TRACK::HitTest( const wxPoint& aPosition, int aAccuracy ) const
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{
return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_Width / 2 ) );
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}
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bool PCB_ARC::HitTest( const wxPoint& aPosition, int aAccuracy ) const
{
int max_dist = aAccuracy + ( m_Width / 2 );
// Short-circuit common cases where the arc is connected to a track or via at an endpoint
if( EuclideanNorm( GetStart() - aPosition ) <= max_dist ||
EuclideanNorm( GetEnd() - aPosition ) <= max_dist )
{
return true;
}
wxPoint center = GetPosition();
wxPoint relpos = aPosition - center;
double dist = EuclideanNorm( relpos );
double radius = GetRadius();
if( std::abs( dist - radius ) > max_dist )
return false;
double arc_angle_start = GetArcAngleStart(); // Always 0.0 ... 360 deg, in 0.1 deg
double arc_hittest = ArcTangente( relpos.y, relpos.x );
// Calculate relative angle between the starting point of the arc, and the test point
arc_hittest -= arc_angle_start;
// Normalise arc_hittest between 0 ... 360 deg
NORMALIZE_ANGLE_POS( arc_hittest );
double arc_angle = GetAngle();
if( arc_angle < 0 )
return arc_hittest >= 3600 + arc_angle;
return arc_hittest <= arc_angle;
}
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bool PCB_VIA::HitTest( const wxPoint& aPosition, int aAccuracy ) const
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{
int max_dist = aAccuracy + ( m_Width / 2 );
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// rel_pos is aPosition relative to m_Start (or the center of the via)
wxPoint rel_pos = aPosition - m_Start;
double dist = (double) rel_pos.x * rel_pos.x + (double) rel_pos.y * rel_pos.y;
return dist <= (double) max_dist * max_dist;
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}
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bool PCB_TRACK::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
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{
EDA_RECT arect = aRect;
arect.Inflate( aAccuracy );
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if( aContained )
return arect.Contains( GetStart() ) && arect.Contains( GetEnd() );
else
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return arect.Intersects( GetStart(), GetEnd() );
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}
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bool PCB_ARC::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
{
EDA_RECT box;
EDA_RECT arect = aRect;
arect.Inflate( aAccuracy );
box.SetOrigin( GetStart() );
box.Merge( GetMid() );
box.Merge( GetEnd() );
box.Inflate( GetWidth() / 2 );
if( aContained )
return arect.Contains( box );
else
return arect.Intersects( box );
}
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bool PCB_VIA::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
{
EDA_RECT box;
EDA_RECT arect = aRect;
arect.Inflate( aAccuracy );
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box.SetOrigin( GetStart() );
box.Inflate( GetWidth() / 2 );
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if( aContained )
return arect.Contains( box );
else
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return arect.IntersectsCircle( GetStart(), GetWidth() / 2 );
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}
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wxString PCB_TRACK::GetSelectMenuText( EDA_UNITS aUnits ) const
{
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return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
: _("Track %s on %s, length %s" ),
GetNetnameMsg(),
GetLayerName(),
MessageTextFromValue( aUnits, GetLength() ) );
}
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BITMAPS PCB_TRACK::GetMenuImage() const
{
return BITMAPS::add_tracks;
}
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void PCB_TRACK::SwapData( BOARD_ITEM* aImage )
{
assert( aImage->Type() == PCB_TRACE_T );
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std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
}
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void PCB_ARC::SwapData( BOARD_ITEM* aImage )
{
assert( aImage->Type() == PCB_ARC_T );
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std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
}
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void PCB_VIA::SwapData( BOARD_ITEM* aImage )
{
assert( aImage->Type() == PCB_VIA_T );
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std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
}
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wxPoint PCB_ARC::GetPosition() const
{
auto center = GetArcCenter( VECTOR2I( m_Start ), VECTOR2I( m_Mid ), VECTOR2I( m_End ) );
return wxPoint( center.x, center.y );
}
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double PCB_ARC::GetRadius() const
{
auto center = GetArcCenter( VECTOR2I( m_Start ), VECTOR2I( m_Mid ), VECTOR2I( m_End ) );
return GetLineLength( wxPoint( center ), m_Start );
}
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double PCB_ARC::GetAngle() const
{
wxPoint center = GetPosition();
wxPoint p0 = m_Start - center;
wxPoint p1 = m_Mid - center;
wxPoint p2 = m_End - center;
double angle1 = ArcTangente( p1.y, p1.x ) - ArcTangente( p0.y, p0.x );
double angle2 = ArcTangente( p2.y, p2.x ) - ArcTangente( p1.y, p1.x );
return NormalizeAngle180( angle1 ) + NormalizeAngle180( angle2 );
}
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double PCB_ARC::GetArcAngleStart() const
{
wxPoint center = GetPosition();
double angleStart = ArcTangente( m_Start.y - center.y,
m_Start.x - center.x );
return NormalizeAnglePos( angleStart );
}
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double PCB_ARC::GetArcAngleEnd() const
{
wxPoint center = GetPosition();
double angleEnd = ArcTangente( m_End.y - center.y,
m_End.x - center.x );
return NormalizeAnglePos( angleEnd );
}
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bool PCB_TRACK::cmp_tracks::operator() ( const PCB_TRACK* a, const PCB_TRACK* b ) const
{
if( a->GetNetCode() != b->GetNetCode() )
return a->GetNetCode() < b->GetNetCode();
if( a->GetLayer() != b->GetLayer() )
return a->GetLayer() < b->GetLayer();
if( a->Type() != b->Type() )
return a->Type() < b->Type();
if( a->m_Uuid != b->m_Uuid )
return a->m_Uuid < b->m_Uuid;
return a < b;
}
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std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
{
return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, m_Width );
}
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std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
{
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if( FlashLayer( aLayer ) )
return std::make_shared<SHAPE_CIRCLE>( m_Start, m_Width / 2 );
else
return std::make_shared<SHAPE_CIRCLE>( m_Start, GetDrillValue() / 2 );
}
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std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
{
return std::make_shared<SHAPE_ARC>( GetStart(), GetMid(), GetEnd(), GetWidth() );
}
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#if defined(DEBUG)
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wxString PCB_TRACK::ShowState( int stateBits )
{
wxString ret;
if( stateBits & IS_LINKED )
ret << wxT( " | IS_LINKED" );
if( stateBits & LOCKED )
ret << wxT( " | LOCKED" );
if( stateBits & IN_EDIT )
ret << wxT( " | IN_EDIT" );
if( stateBits & IS_DRAGGING )
ret << wxT( " | IS_DRAGGING" );
if( stateBits & DO_NOT_DRAW )
ret << wxT( " | DO_NOT_DRAW" );
if( stateBits & IS_DELETED )
ret << wxT( " | IS_DELETED" );
if( stateBits & END_ONPAD )
ret << wxT( " | END_ONPAD" );
if( stateBits & BEGIN_ONPAD )
ret << wxT( " | BEGIN_ONPAD" );
return ret;
}
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#endif
static struct TRACK_VIA_DESC
{
TRACK_VIA_DESC()
{
ENUM_MAP<VIATYPE>::Instance()
.Undefined( VIATYPE::NOT_DEFINED )
.Map( VIATYPE::THROUGH, _HKI( "Through" ) )
.Map( VIATYPE::BLIND_BURIED, _HKI( "Blind/buried" ) )
.Map( VIATYPE::MICROVIA, _HKI( "Micro" ) );
ENUM_MAP<PCB_LAYER_ID>& layerEnum = ENUM_MAP<PCB_LAYER_ID>::Instance();
if( layerEnum.Choices().GetCount() == 0 )
{
layerEnum.Undefined( UNDEFINED_LAYER );
for( LSEQ seq = LSET::AllLayersMask().Seq(); seq; ++seq )
layerEnum.Map( *seq, LSET::Name( *seq ) );
}
PROPERTY_MANAGER& propMgr = PROPERTY_MANAGER::Instance();
// Track
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REGISTER_TYPE( PCB_TRACK );
propMgr.InheritsAfter( TYPE_HASH( PCB_TRACK ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
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propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
&PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
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new PROPERTY<PCB_TRACK, int, BOARD_ITEM>( _HKI( "Origin X" ),
&PCB_TRACK::SetX, &PCB_TRACK::GetX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
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new PROPERTY<PCB_TRACK, int, BOARD_ITEM>( _HKI( "Origin Y" ),
&PCB_TRACK::SetY, &PCB_TRACK::GetY, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
&PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
&PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::DISTANCE ) );
// Arc
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REGISTER_TYPE( PCB_ARC );
propMgr.InheritsAfter( TYPE_HASH( PCB_ARC ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
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propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
&PCB_ARC::SetWidth, &PCB_ARC::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
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new PROPERTY<PCB_ARC, int, BOARD_ITEM>( _HKI( "Origin X" ),
&PCB_TRACK::SetX, &PCB_ARC::GetX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
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new PROPERTY<PCB_ARC, int, BOARD_ITEM>( _HKI( "Origin Y" ),
&PCB_TRACK::SetY, &PCB_ARC::GetY, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
&PCB_TRACK::SetEndX, &PCB_ARC::GetEndX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
&PCB_TRACK::SetEndY, &PCB_ARC::GetEndY, PROPERTY_DISPLAY::DISTANCE ) );
// Via
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REGISTER_TYPE( PCB_VIA );
propMgr.InheritsAfter( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
// TODO layerset for vias?
// TODO test drill, use getdrillvalue?
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propMgr.ReplaceProperty( TYPE_HASH( PCB_TRACK ), _HKI( "Width" ),
new PROPERTY<PCB_VIA, int, PCB_TRACK>( _HKI( "Diameter" ),
&PCB_VIA::SetWidth, &PCB_VIA::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Drill" ),
&PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Layer" ),
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new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID, BOARD_ITEM>( _HKI( "Layer Top" ),
&PCB_VIA::SetLayer, &PCB_VIA::GetLayer ) );
propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
&PCB_VIA::SetBottomLayer, &PCB_VIA::BottomLayer ) );
propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
&PCB_VIA::SetViaType, &PCB_VIA::GetViaType ) );
}
} _TRACK_VIA_DESC;
ENUM_TO_WXANY( VIATYPE );