We no longer have any knowledge of the original start/end of the arc,
since SetArcAngleAndEnd swaps the start and end to ensure the arc is
always clockwise at the end.
Adds a method EDA_SHAPE::EndsSwapped() to notify whether the start/end
point of the shape were swapped.
The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).
This removes a large amount of DRC violations on imported designs.
Use KiCad default stackup for older CADSTAR boards that do not
define any dielectric layers between the electrical layers.
Also fix default stackup calculation to ensure finished board thickness
is 1.6mm
This was happening in two cases:
- Loading documentation symbols (CADSTAR on purpose defines these in an
invalid layer)
- When an item was in a "layer set" such as ALLELEC or ALLLAYER - need to
make sure we remove the copper layers that are not active in the design
Cadstar areas have a line width but this is only for display purposes.
Instead CADSTAR uses the center line when determining whether a DRC
violation occurred.
We were loading as solid fill when the relief gap was exactly the
same as the minimum width.
Also we can do better than just load as solid fill when it is smaller:
we can instead just use the minimum width and at least it still will
have thermal reliefs.
wxString::Format is redundant in a wxLogXXX call.
Error messages should generally be translatable.
Error messages should use generally consistent sentence forms.
- Create a pad if a component copper is associated with any other pads
in the footprint.
- Rename/renumber 'PCB Only' pads that are associated with a component
copper and make them all use the same pad name/number.
KiCad doesn't yet support full padstacks, but at least we can use the
solder mask / solder paste expansion to import a better result. Also
we can disable the specific layer if the shape has a size of zero.
The CADSTAR post processor has a peculiar feature called "route offset"
which effectively shortens tracks when the pad, track or via that it
connects to has a smaller width. This operation is not saved in the
design itself, but applied as a post processing operation meaning that
the importer has to apply it when loading on the board.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/6648
Roberto Fernandez Bautista
Jeff Young
Wayne Stambaugh
luz paz
Marek Roszko
Ian McInerney
jean-pierre charras