bbef4fee17
Added documentation about pcbnew plugin development
2017-06-28 10:48:41 -04:00
d6aad9c6e7
Corrected Typo in documentation of GetClearance function
2017-06-27 16:50:47 -04:00
85a0a371b1
Add support to resolve schematic symbol links using symbol library table.
...
Add Resolve() and ResolveAll() methods the SCH_COMPONENT object to use the
symbol library table to obtain links to the library symbols.
Add LoadAlias() method to SYMBOL_LIB_TABLE to find an alias by it's LIB_ID.
Clean up Doxygen comments to match coding policy changes.
2017-06-27 11:22:58 -04:00
1e87ae6c50
Fixed a memleak in raytracer
2017-06-27 10:58:43 +02:00
37f8c83c5b
Fix the BOARD & MODULE classes SWIG interface
2017-06-26 18:28:23 +02:00
3c3ee9b8c3
Fix a few doxygen warnings
2017-06-26 18:12:57 +02:00
5774fd284e
pcbnew: Do not sove 'no_connects' and 'area' in .kicad_pcb
...
These data are redundant as they are calculated by pcbnew.
2017-06-26 08:59:20 +02:00
544e944647
pcbnew: Do not save 'links' information
...
It is not parsed anyway and the new connectivity algorithm
does not calculate it.
2017-06-26 08:40:50 +02:00
ac688e688a
Fixed selecting components with Enter (DIALOG_CHOOSE_COMPONENT)
...
Added dedicated event types: COMPONENT_SELECTED, COMPONENT_PRESELECTED.
2017-06-25 23:13:39 +02:00
6a3c1720b2
Fix a few doxygen warnings
2017-06-25 11:26:04 +02:00
1e770f56a6
Fix a non ASCII7 string in a message. Only ASCII7 chars can be used in sources.
...
Non ASCII7 symbols are not allowed because the encoding is OS dependent.
2017-06-24 20:05:11 +02:00
0719b99ad8
Minor enhancement in color selection on Windows
2017-06-24 10:45:26 +02:00
5d8dd7c20f
Loading python plugins: make subdir import more tolerant to broken python scripts,
...
and compatible to subdirs that contains other scripts (like .xsl scripts)
2017-06-24 10:15:51 +02:00
e40de096bc
Fix broken directory names building for python plugins
2017-06-24 07:55:27 +02:00
72eff0941e
Code formatting and warning fixes
2017-06-23 19:22:44 +02:00
3aaf26da2e
Fixes for pcbnew_scripting_helpers.cpp
2017-06-23 19:22:27 +02:00
f1d650d5be
Use node & unconnected count from CONNECTIVITY object
2017-06-23 18:51:00 +02:00
7b9330129c
Update ratsnest lines on zone fill removal
2017-06-23 18:51:00 +02:00
79b2d60666
Reenabled pad number increment on placement (module editor)
2017-06-23 18:51:00 +02:00
7330a85554
Moved INTRUSIVE_LIST to a separate header
2017-06-23 18:51:00 +02:00
450ad5eab9
CONNECTIVITY_DATA::GetNodeCount() implementation
2017-06-23 18:51:00 +02:00
74ef3ecb1d
Moved one-liners to header files
2017-06-23 18:51:00 +02:00
3dd4429ef6
Dead code removal
2017-06-23 18:50:31 +02:00
f3fbce9560
Code formatting and clean-up
2017-06-23 15:43:13 +02:00
113163257d
Fixed compilation warnings
2017-06-23 11:36:05 +02:00
5c0edbabab
Fixes for the connectivity & board cleanup algorithms
2017-06-23 11:12:38 +02:00
f324c7b16d
Switch another loop to D_PAD iterator
2017-06-23 11:12:38 +02:00
a7759efc59
Multiple fixes:
...
- ratsnest is updated now when undoing in legacy view
- select whole net regression
- local ratsnest in the GAL regression
- pick correct zone net for stitching vias
- mark nets as dirty on net propagation to force ratsnest update
Todo:
- cleanup board algorithm is still broken
2017-06-23 11:12:37 +02:00
81dbd930ae
Display zone filling progress window in GAL
2017-06-23 11:12:37 +02:00
586710c6f5
eagle_plugin: correct via size import
2017-06-23 11:12:37 +02:00
655d851d48
Fixed point-in-polygon test bugs. Connectivity now correctly recognizes zone outlines that have non-zero width
2017-06-23 11:12:37 +02:00
d8018ded0b
fix build with Python
2017-06-23 11:12:37 +02:00
de7f4d7aa4
fixed unresolved symbols while running cvpcb
2017-06-23 11:12:37 +02:00
56928647ef
fixed performance regression in DRC clearance test
2017-06-23 11:12:37 +02:00
2c68786fa8
Display via net labels on top
2017-06-23 11:12:37 +02:00
3b16d3cffe
further DLIST/Iterators cleanup, some code formatting
2017-06-23 11:12:37 +02:00
63f4ab697b
post-rebase fixes
2017-06-23 11:12:37 +02:00
3b7b0603b6
pcbnew: via placement tool, initial version
2017-06-23 11:12:37 +02:00
bd960f0e5c
pcbnew/dialogs: more options in track/via properties window
2017-06-23 11:12:37 +02:00
706db2a486
pcbnew: draw net labels on vias [wip]
2017-06-23 11:12:37 +02:00
96865d45e3
icons for via placement tool
2017-06-23 11:12:37 +02:00
bfdd1191ab
pcbnew: rename PLACEMENT_TOOL to ALIGN_DISTRIBUTE_TOOL, some fixes in the connectivity algo
2017-06-23 11:12:37 +02:00
c4c329e393
Connectivity: local ratsnest for both legacy & GAL. Further removal of legacy code
2017-06-23 11:12:37 +02:00
07b7600ae5
TRACKS_CLEANER: fixes after changing the connectivity algorithm
2017-06-23 11:12:37 +02:00
6008abaad9
DRC connectivity check
2017-06-23 11:12:37 +02:00
edf1aac357
Fixed some compilation warnings. Missing features so far: single-module ratsnest & DRC unconnected report
2017-06-23 11:12:37 +02:00
3cba1007eb
Removed legacy connectivity/ratsnest algorithm, replaced with the new one. No legacy autorouting for the moment
2017-06-23 11:12:37 +02:00
9ad886344b
New connectivity algorithm.
2017-06-23 11:12:36 +02:00
eaba60b89a
profile.h: added PROF_COUNTER C++ class
2017-06-23 11:12:36 +02:00
94a80acb36
DLIST_ITERATOR improvements
2017-06-23 11:12:36 +02:00
Simon Kueppers
Wayne Stambaugh
Maciej Suminski
jean-pierre charras
Jean-Samuel Reynaud
Tomasz Włostowski
Simon Richter