dd6aadc54d
jtag: Add verbosity about devices found.
2020-12-06 15:18:08 +01:00
e318f884bf
Change the type of 'cortexm_wait_timeout' to unsigned.
...
It makes sense that the timeout value is unsigned, it also
resolves build errors on some platforms.
2020-12-04 11:44:50 +01:00
e3fd12ebc6
gd32f1/f3 detection and ram/flash autoset
2020-12-03 11:16:47 +01:00
575c25e570
Add support for STM32F1 clone with new AP_DESIGNER id
2020-12-01 10:23:16 +01:00
48a79ff9da
adiv5: More checks for a sensible DPIDR.
2020-11-29 21:11:11 +01:00
752bc26536
adiv5: Fix memleak with duplicated base.
2020-11-29 21:11:11 +01:00
acec489647
adiv5_jtagdp: Always set idcode.
2020-11-29 21:11:11 +01:00
f45c56af83
adiv5/swdp: Check early for valid DP idcode.
2020-11-29 15:48:50 +01:00
7df314e265
Firmware/Jlink: Fix double free when debug power-up fails ( #780 )
2020-11-29 15:48:50 +01:00
bf548e92c0
swd: After write low_access, always append 8 clk to move data through SW-DP.
...
Especially needed when leaving the debugger or during debug unit power-up.
ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
tells to clock the data through SW-DP to either :
- immediate start a new transaction
- continue to drive idle cycles
- or clock at least 8 idle cycles
Implement last option to favour correctness over slight speed decrease
Implement only for adapters where we assemble the seq_out_parity in our code,
as on firmware, ftdi and jlink. Hopefully the high level adapters do it right.
Reverts 2c33cde63fcde7726b87
2020-11-27 22:26:48 +01:00
3ee31473c6
cortexm.c: LPC15xx has designer 43b and Partno 4c3
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Thanks to JojoS!
2020-11-27 22:26:48 +01:00
19e1fddba2
adiv5: Remove unnescessary read.
2020-11-27 22:26:48 +01:00
cda83d3084
Fix memleaks.
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Happened e.g. when Stlink could not enter debug or when cortexm_prepare timed out.
2020-11-27 22:26:48 +01:00
9ac5adfcef
adiv5: Additional decoding.
2020-11-27 22:26:48 +01:00
d78d7838d3
stm32f1: Always read DBGMCU_IDCODE for t->idcode ( #770 )
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At least STM32F042 has 0x440 as romtable partno vs 0x445 as DBGMCU_IDCODE.
Thanks to Andrey Melnikov(aam335) for pointing out!
2020-11-27 22:26:48 +01:00
653d486ee2
cortexm: Store CPUID in target structure.
2020-11-27 22:26:48 +01:00
80154c5c7a
adiv5_swdp: Fix more memory leak.
2020-11-27 22:26:48 +01:00
35bcb4f7c6
Switch on the lpc546xx target
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Enable the lpc546xx target. Tested on the LPCXpresso54628 dev board,
able to flash and debug.
2020-11-24 21:32:39 +01:00
e9c02296f2
target: kinetis: add S32K118
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This adds support for the NXP S32K118. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-11-14 13:06:23 +01:00
f18be6ef7a
Add support for Kinetis K12 and placeholders for other K-series MCUs
2020-11-07 12:44:05 +01:00
2c33cde63f
cortexm.c/cortexm_halt_resume: Add some clock cycles to always get CPU going ( #768 )
2020-11-01 21:53:23 +01:00
1f7a716710
adiv5.c: Run cortexm_prepare on all suspected CortexM instances.
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Gets all debug units of the second CPU of a STM32H745 visible.
2020-10-23 09:40:15 +02:00
18673d9a56
adiv5: Rework DP/AP refcounting.
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ASAN non longer reports leaks with the STM32H745.
2020-10-23 09:40:15 +02:00
f76a7c4e92
adiv5: Release devices after scan.
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Before, scanning only kept device stopped until POR or attach/detach cycle.
2020-10-23 09:40:15 +02:00
59dc1b7eb4
cortex-m7: Give hint about buggy core revision.
2020-10-23 09:40:15 +02:00
976c763747
jtag remote: Start fixing handling M0 (second jtag) for LPC4322 in high-level
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- LPC11: Only print none-null unknown idcodes.
2020-10-23 09:40:15 +02:00
c161521c26
cortexm: Designer ARM must be in the default path when probing.
2020-10-23 09:40:15 +02:00
cdd07544d5
Cortexm: Allow pure debug on devices not yet handled for flashing
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- Recognize STM32L552 and MIMXRT10XX
- Fix another PIDR
- Fix bad debug print string.
2020-10-23 09:40:15 +02:00
0ffb4f7b18
cortexm: Fix protected SAM detection
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- Only run cortex_prepare() if reading cidr fails
- With Atmel DSU detected, run cortexm_probe()
2020-10-17 12:49:37 +02:00
5bc743d221
samd: Propagate security after setting security by chip reset.
2020-10-17 12:49:37 +02:00
8b929c12c9
hosted/jtag: Transfer jtag_devs to firmware.
2020-10-16 20:03:03 +02:00
3d92b82678
jtag: Use index and not device structure for jtag_dev_write_ir and jtag_dev_shift_dr
2020-10-16 20:03:03 +02:00
7ccf0d3e03
jtag_dev_t: Make dev, idcode and desc less generic.
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No codechange intended.
2020-10-16 20:03:03 +02:00
87b546777a
nrf51: Be more verbose about the protection status.
2020-10-16 12:16:33 +02:00
4108b649c2
stm32h7: Add support for new product lines
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Add support for:
* STM32H7B3/B0/A3 (RM0455)
* STM32H723/33/25/35/30 (RM0468)
Successfully tested with:
* STM32H7A3ZIT (RM0455)
* STM32H747XIH (check for regressions)
2020-10-10 22:09:34 +02:00
877b4be8ee
cortexm: Restrict probing by using the ap_designer.
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More designers need to be observed and reported by users and added.
Request users to send needed data.
2020-10-07 20:12:35 +02:00
91d1ef8bf6
target/stm32: Use t->idcode with probe.
2020-10-07 20:12:35 +02:00
44bfb62715
Adiv5: Print Designer/Partno when device is not recognized
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t->idcode is now 16 bit.
2020-10-07 20:12:35 +02:00
c456fc7f61
adiv5: Store AP designer and partno in the AP structure.
2020-10-07 20:12:32 +02:00
159196c2ad
Cortexm: Remove forced_halt.
2020-10-07 20:11:33 +02:00
9bb2807706
adiv5/romtable: Prepare CortexM devices to read the ROMTABLE
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It seems, writing to DHCSR fails silent when the device is sleeping.
Reading DHCS during sleep may return nonsense.
Repeated write may at some point catch the device running and succeed.
With devices sleeping for long time and running on faster clock the
chance for a successful hotplug gets smaller.
- Try hard to halt a sleeping device
- Prepare vector catch and enable all debug units by TRACENA
- Release reset
- Apply device specific fixes
-- STM32F7: Store old value of DBGMCU_CR, enable debug in sleep in
DBGMCU before reading PIDR and restore DBGMCU on detach.
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
2020-10-07 20:11:17 +02:00
dc8924a2bc
stm32h7: Don't tc_printf from flash functions ( #747 )
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* stm32h7: Don't tc_printf from flash functions
Receving an 'O' packet while flashing confuses GDB and then
weird stuff happens.
* Replace tc_printf with DEBUG_WARN
2020-10-05 10:45:18 +02:00
014abf6cc9
adiv5.c: Reduce number of errors if reading cidr fails.
2020-10-01 15:33:28 +02:00
be40d2b851
adiv5: Check Debug Base Address early
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Reduces printout when scanning the romtable
2020-10-01 15:22:17 +02:00
38bc5bbf82
Add LPC546xx support #741 #553
2020-09-30 12:56:53 +02:00
2fdd94adeb
STM32F7: Add another missing Arch ID.
2020-09-24 16:20:34 +02:00
bdb351a6ea
adiv5_swdp: On ACK_FAULT, error() and try again once #731
...
when writing CSW.
2020-09-18 20:07:32 +02:00
120b3134bb
Add SAM4SD32C/B support.
2020-09-07 17:36:15 +02:00
8a2bce26f2
Hosted: Fix memory leak when platform_swdptap_init fails.
2020-09-04 11:49:13 +02:00
f65afb1588
Use correct IAP entry address for LPC84x
2020-08-14 20:00:18 +02:00
Uwe Bonnes
Stoyan Shopov
mean
Jonathan Giles
Noah Pendleton
Sean Cross
jbuonagurio
Richard Meadows
Gareth McMullin
Eivind Alexander Bergem
Damien Merenne
David Lawrence