kicad/pcbnew/drc/drc_engine.cpp

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2004-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
* Copyright (C) 2014 Dick Hollenbeck, dick@softplc.com
* Copyright (C) 2017-2021 KiCad Developers, see AUTHORS.txt for contributors.
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*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
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#include <atomic>
#include <thread>
#include <reporter.h>
#include <progress_reporter.h>
#include <string_utils.h>
#include <board_design_settings.h>
#include <drc/drc_engine.h>
#include <drc/drc_rtree.h>
#include <drc/drc_rule_parser.h>
#include <drc/drc_rule.h>
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#include <drc/drc_rule_condition.h>
#include <drc/drc_test_provider.h>
#include <drc/drc_item.h>
#include <footprint.h>
#include <pad.h>
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#include <pcb_track.h>
#include <zone.h>
#include <geometry/shape.h>
#include <geometry/shape_segment.h>
#include <geometry/shape_null.h>
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// wxListBox's performance degrades horrifically with very large datasets. It's not clear
// they're useful to the user anyway.
#define ERROR_LIMIT 199
#define EXTENDED_ERROR_LIMIT 499
void drcPrintDebugMessage( int level, const wxString& msg, const char *function, int line )
{
wxString valueStr;
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if( wxGetEnv( wxT( "DRC_DEBUG" ), &valueStr ) )
{
int setLevel = wxAtoi( valueStr );
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if( level <= setLevel )
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printf( "%-30s:%d | %s\n", function, line, (const char *) msg.c_str() );
}
}
DRC_ENGINE::DRC_ENGINE( BOARD* aBoard, BOARD_DESIGN_SETTINGS *aSettings ) :
m_designSettings ( aSettings ),
m_board( aBoard ),
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m_drawingSheet( nullptr ),
m_schematicNetlist( nullptr ),
m_rulesValid( false ),
m_userUnits( EDA_UNITS::MILLIMETRES ),
m_reportAllTrackErrors( false ),
m_testFootprints( false ),
m_reporter( nullptr ),
m_progressReporter( nullptr )
{
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m_errorLimits.resize( DRCE_LAST + 1 );
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for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
m_errorLimits[ ii ] = ERROR_LIMIT;
}
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DRC_ENGINE::~DRC_ENGINE()
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{
m_rules.clear();
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for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
{
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for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
delete constraint;
delete pair.second;
}
}
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static bool isKeepoutZone( const BOARD_ITEM* aItem, bool aCheckFlags )
{
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if( !aItem )
return false;
if( aItem->Type() != PCB_ZONE_T && aItem->Type() != PCB_FP_ZONE_T )
return false;
const ZONE* zone = static_cast<const ZONE*>( aItem );
if( !zone->GetIsRuleArea() )
return false;
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if( aCheckFlags )
{
if( !zone->GetDoNotAllowTracks()
&& !zone->GetDoNotAllowVias()
&& !zone->GetDoNotAllowPads()
&& !zone->GetDoNotAllowCopperPour()
&& !zone->GetDoNotAllowFootprints() )
{
return false;
}
}
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return true;
}
std::shared_ptr<DRC_RULE> DRC_ENGINE::createImplicitRule( const wxString& name )
{
std::shared_ptr<DRC_RULE> rule = std::make_shared<DRC_RULE>();
rule->m_Name = name;
rule->m_Implicit = true;
addRule( rule );
return rule;
}
void DRC_ENGINE::loadImplicitRules()
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{
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ReportAux( wxString::Format( wxT( "Building implicit rules (per-item/class overrides, etc...)" ) ) );
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
// 1) global defaults
std::shared_ptr<DRC_RULE> rule = createImplicitRule( _( "board setup constraints" ) );
DRC_CONSTRAINT clearanceConstraint( CLEARANCE_CONSTRAINT );
clearanceConstraint.Value().SetMin( bds.m_MinClearance );
rule->AddConstraint( clearanceConstraint );
DRC_CONSTRAINT widthConstraint( TRACK_WIDTH_CONSTRAINT );
widthConstraint.Value().SetMin( bds.m_TrackMinWidth );
rule->AddConstraint( widthConstraint );
DRC_CONSTRAINT drillConstraint( HOLE_SIZE_CONSTRAINT );
drillConstraint.Value().SetMin( bds.m_MinThroughDrill );
rule->AddConstraint( drillConstraint );
DRC_CONSTRAINT annulusConstraint( ANNULAR_WIDTH_CONSTRAINT );
annulusConstraint.Value().SetMin( bds.m_ViasMinAnnularWidth );
rule->AddConstraint( annulusConstraint );
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DRC_CONSTRAINT diameterConstraint( VIA_DIAMETER_CONSTRAINT );
diameterConstraint.Value().SetMin( bds.m_ViasMinSize );
rule->AddConstraint( diameterConstraint );
DRC_CONSTRAINT holeToHoleConstraint( HOLE_TO_HOLE_CONSTRAINT );
holeToHoleConstraint.Value().SetMin( bds.m_HoleToHoleMin );
rule->AddConstraint( holeToHoleConstraint );
DRC_CONSTRAINT diffPairGapConstraint( DIFF_PAIR_GAP_CONSTRAINT );
diffPairGapConstraint.Value().SetMin( bds.m_MinClearance );
rule->AddConstraint( diffPairGapConstraint );
rule = createImplicitRule( _( "default" ) );
DRC_CONSTRAINT thermalSpokeCountConstraint( MIN_RESOLVED_SPOKES_CONSTRAINT );
thermalSpokeCountConstraint.Value().SetMin( bds.m_MinResolvedSpokes );
rule->AddConstraint( thermalSpokeCountConstraint );
rule = createImplicitRule( _( "board setup constraints silk" ) );
rule->m_LayerCondition = LSET( 2, F_SilkS, B_SilkS );
DRC_CONSTRAINT silkClearanceConstraint( SILK_CLEARANCE_CONSTRAINT );
silkClearanceConstraint.Value().SetMin( bds.m_SilkClearance );
rule->AddConstraint( silkClearanceConstraint );
DRC_CONSTRAINT silkTextHeightConstraint( TEXT_HEIGHT_CONSTRAINT );
silkTextHeightConstraint.Value().SetMin( bds.m_MinSilkTextHeight );
rule->AddConstraint( silkTextHeightConstraint );
DRC_CONSTRAINT silkTextThicknessConstraint( TEXT_THICKNESS_CONSTRAINT );
silkTextThicknessConstraint.Value().SetMin( bds.m_MinSilkTextThickness );
rule->AddConstraint( silkTextThicknessConstraint );
rule = createImplicitRule( _( "board setup constraints hole" ) );
DRC_CONSTRAINT holeClearanceConstraint( HOLE_CLEARANCE_CONSTRAINT );
holeClearanceConstraint.Value().SetMin( bds.m_HoleClearance );
rule->AddConstraint( holeClearanceConstraint );
rule = createImplicitRule( _( "board setup constraints edge" ) );
DRC_CONSTRAINT edgeClearanceConstraint( EDGE_CLEARANCE_CONSTRAINT );
edgeClearanceConstraint.Value().SetMin( bds.m_CopperEdgeClearance );
rule->AddConstraint( edgeClearanceConstraint );
rule = createImplicitRule( _( "board setup constraints courtyard" ) );
DRC_CONSTRAINT courtyardClearanceConstraint( COURTYARD_CLEARANCE_CONSTRAINT );
holeToHoleConstraint.Value().SetMin( 0 );
rule->AddConstraint( courtyardClearanceConstraint );
// 2) micro-via specific defaults (new DRC doesn't treat microvias in any special way)
std::shared_ptr<DRC_RULE> uViaRule = createImplicitRule( _( "board setup micro-via constraints" ) );
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uViaRule->m_Condition = new DRC_RULE_CONDITION( wxT( "A.Via_Type == 'Micro'" ) );
DRC_CONSTRAINT uViaDrillConstraint( HOLE_SIZE_CONSTRAINT );
uViaDrillConstraint.Value().SetMin( bds.m_MicroViasMinDrill );
uViaRule->AddConstraint( uViaDrillConstraint );
DRC_CONSTRAINT uViaDiameterConstraint( VIA_DIAMETER_CONSTRAINT );
uViaDiameterConstraint.Value().SetMin( bds.m_MicroViasMinSize );
uViaRule->AddConstraint( uViaDiameterConstraint );
if( !bds.m_MicroViasAllowed )
{
DRC_CONSTRAINT disallowConstraint( DISALLOW_CONSTRAINT );
disallowConstraint.m_DisallowFlags = DRC_DISALLOW_MICRO_VIAS;
uViaRule->AddConstraint( disallowConstraint );
}
if( !bds.m_BlindBuriedViaAllowed )
{
std::shared_ptr<DRC_RULE> bbViaRule = createImplicitRule( _( "board setup constraints" ) );
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bbViaRule->m_Condition = new DRC_RULE_CONDITION( wxT( "A.Via_Type == 'Blind/buried'" ) );
DRC_CONSTRAINT disallowConstraint( DISALLOW_CONSTRAINT );
disallowConstraint.m_DisallowFlags = DRC_DISALLOW_BB_VIAS;
bbViaRule->AddConstraint( disallowConstraint );
}
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// 3) per-netclass rules
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std::vector<std::shared_ptr<DRC_RULE>> netclassClearanceRules;
std::vector<std::shared_ptr<DRC_RULE>> netclassItemSpecificRules;
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auto makeNetclassRules =
[&]( const NETCLASSPTR& nc, bool isDefault )
{
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wxString ncName = nc->GetName();
wxString expr;
if( nc->GetClearance() || nc->GetTrackWidth() )
{
std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
netclassRule->m_Implicit = true;
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expr = wxString::Format( wxT( "A.NetClass == '%s'" ), ncName );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassClearanceRules.push_back( netclassRule );
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if( nc->GetClearance() )
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{
DRC_CONSTRAINT constraint( CLEARANCE_CONSTRAINT );
constraint.Value().SetMin( std::max( bds.m_MinClearance,
nc->GetClearance() ) );
netclassRule->AddConstraint( constraint );
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}
if( nc->GetTrackWidth() )
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{
DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
constraint.Value().SetMin( bds.m_TrackMinWidth );
constraint.Value().SetOpt( nc->GetTrackWidth() );
netclassRule->AddConstraint( constraint );
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}
}
if( nc->GetDiffPairWidth() )
{
std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
netclassRule->m_Name = wxString::Format( _( "netclass '%s' (diff pair)" ),
ncName );
netclassRule->m_Implicit = true;
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expr = wxString::Format( wxT( "A.NetClass == '%s' && A.inDiffPair('*')" ),
ncName );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
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DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
constraint.Value().SetMin( bds.m_TrackMinWidth );
constraint.Value().SetOpt( nc->GetDiffPairWidth() );
netclassRule->AddConstraint( constraint );
}
if( nc->GetDiffPairGap() )
{
std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
netclassRule->m_Name = wxString::Format( _( "netclass '%s' (diff pair)" ),
ncName );
netclassRule->m_Implicit = true;
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expr = wxString::Format( wxT( "A.NetClass == '%s'" ), ncName );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
DRC_CONSTRAINT constraint( DIFF_PAIR_GAP_CONSTRAINT );
constraint.Value().SetMin( bds.m_MinClearance );
constraint.Value().SetOpt( nc->GetDiffPairGap() );
netclassRule->AddConstraint( constraint );
// A narrower diffpair gap overrides the netclass min clearance (but is still
// trimmed to the board min clearance, which is absolute).
if( nc->GetDiffPairGap() < nc->GetClearance() )
{
netclassRule = std::make_shared<DRC_RULE>();
netclassRule->m_Name = wxString::Format( _( "netclass '%s' (diff pair)" ),
ncName );
netclassRule->m_Implicit = true;
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expr = wxString::Format( wxT( "A.NetClass == '%s' && AB.isCoupledDiffPair()" ),
ncName );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
DRC_CONSTRAINT min_clearanceConstraint( CLEARANCE_CONSTRAINT );
min_clearanceConstraint.Value().SetMin( std::max( bds.m_MinClearance,
nc->GetDiffPairGap() ) );
netclassRule->AddConstraint( min_clearanceConstraint );
}
}
if( nc->GetViaDiameter() || nc->GetViaDrill() )
{
std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
netclassRule->m_Implicit = true;
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expr = wxString::Format( wxT( "A.NetClass == '%s' && A.Via_Type != 'Micro'" ),
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ncName );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
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if( nc->GetViaDiameter() )
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{
DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
constraint.Value().SetMin( bds.m_ViasMinSize );
constraint.Value().SetOpt( nc->GetViaDiameter() );
netclassRule->AddConstraint( constraint );
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}
if( nc->GetViaDrill() )
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{
DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
constraint.Value().SetMin( bds.m_MinThroughDrill );
constraint.Value().SetOpt( nc->GetViaDrill() );
netclassRule->AddConstraint( constraint );
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}
}
if( nc->GetuViaDiameter() || nc->GetuViaDrill() )
{
std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
netclassRule->m_Implicit = true;
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expr = wxString::Format( wxT( "A.NetClass == '%s' && A.Via_Type == 'Micro'" ),
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ncName );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
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if( nc->GetuViaDiameter() )
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{
DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
constraint.Value().SetMin( bds.m_MicroViasMinSize );
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constraint.Value().SetMin( nc->GetuViaDiameter() );
netclassRule->AddConstraint( constraint );
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}
if( nc->GetuViaDrill() )
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{
DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
constraint.Value().SetMin( bds.m_MicroViasMinDrill );
constraint.Value().SetOpt( nc->GetuViaDrill() );
netclassRule->AddConstraint( constraint );
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}
}
};
m_board->SynchronizeNetsAndNetClasses();
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makeNetclassRules( bds.GetNetClasses().GetDefault(), true );
for( const std::pair<const wxString, NETCLASSPTR>& netclass : bds.GetNetClasses() )
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makeNetclassRules( netclass.second, false );
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// The netclass clearance rules have to be sorted by min clearance so the right one fires
// if 'A' and 'B' belong to two different netclasses.
//
// The item-specific netclass rules are all unary, so there's no 'A' vs 'B' issue.
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std::sort( netclassClearanceRules.begin(), netclassClearanceRules.end(),
[]( const std::shared_ptr<DRC_RULE>& lhs, const std::shared_ptr<DRC_RULE>& rhs )
{
return lhs->m_Constraints[0].m_Value.Min()
< rhs->m_Constraints[0].m_Value.Min();
} );
for( std::shared_ptr<DRC_RULE>& ncRule : netclassClearanceRules )
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addRule( ncRule );
for( std::shared_ptr<DRC_RULE>& ncRule : netclassItemSpecificRules )
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addRule( ncRule );
// 3) keepout area rules
std::vector<ZONE*> keepoutZones;
for( ZONE* zone : m_board->Zones() )
{
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if( isKeepoutZone( zone, true ) )
keepoutZones.push_back( zone );
}
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for( FOOTPRINT* footprint : m_board->Footprints() )
{
for( ZONE* zone : footprint->Zones() )
{
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if( isKeepoutZone( zone, true ) )
keepoutZones.push_back( zone );
}
}
for( ZONE* zone : keepoutZones )
{
wxString name = zone->GetZoneName();
if( name.IsEmpty() )
rule = createImplicitRule( _( "keepout area" ) );
else
rule = createImplicitRule( wxString::Format( _( "keepout area '%s'" ), name ) );
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rule->m_Condition = new DRC_RULE_CONDITION( wxString::Format( wxT( "A.insideArea('%s')" ),
zone->m_Uuid.AsString() ) );
rule->m_LayerCondition = zone->GetLayerSet();
int disallowFlags = 0;
if( zone->GetDoNotAllowTracks() )
disallowFlags |= DRC_DISALLOW_TRACKS;
if( zone->GetDoNotAllowVias() )
disallowFlags |= DRC_DISALLOW_VIAS;
if( zone->GetDoNotAllowPads() )
disallowFlags |= DRC_DISALLOW_PADS;
if( zone->GetDoNotAllowCopperPour() )
disallowFlags |= DRC_DISALLOW_ZONES;
if( zone->GetDoNotAllowFootprints() )
disallowFlags |= DRC_DISALLOW_FOOTPRINTS;
DRC_CONSTRAINT disallowConstraint( DISALLOW_CONSTRAINT );
disallowConstraint.m_DisallowFlags = disallowFlags;
rule->AddConstraint( disallowConstraint );
}
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ReportAux( wxString::Format( wxT( "Building %d implicit netclass rules" ),
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(int) netclassClearanceRules.size() ) );
}
void DRC_ENGINE::loadRules( const wxFileName& aPath )
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{
if( aPath.FileExists() )
{
std::vector<std::shared_ptr<DRC_RULE>> rules;
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FILE* fp = wxFopen( aPath.GetFullPath(), wxT( "rt" ) );
if( fp )
{
DRC_RULES_PARSER parser( fp, aPath.GetFullPath() );
parser.Parse( rules, m_reporter );
}
// Copy the rules into the member variable afterwards so that if Parse() throws then
// the possibly malformed rules won't contaminate the current ruleset.
for( std::shared_ptr<DRC_RULE>& rule : rules )
m_rules.push_back( rule );
}
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}
void DRC_ENGINE::compileRules()
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{
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ReportAux( wxString::Format( wxT( "Compiling Rules (%d rules): " ), (int) m_rules.size() ) );
for( std::shared_ptr<DRC_RULE>& rule : m_rules )
{
DRC_RULE_CONDITION* condition = nullptr;
if( rule->m_Condition && !rule->m_Condition->GetExpression().IsEmpty() )
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{
condition = rule->m_Condition;
condition->Compile( nullptr );
}
for( const DRC_CONSTRAINT& constraint : rule->m_Constraints )
{
if( !m_constraintMap.count( constraint.m_Type ) )
m_constraintMap[ constraint.m_Type ] = new std::vector<DRC_ENGINE_CONSTRAINT*>();
DRC_ENGINE_CONSTRAINT* engineConstraint = new DRC_ENGINE_CONSTRAINT;
engineConstraint->layerTest = rule->m_LayerCondition;
engineConstraint->condition = condition;
engineConstraint->constraint = constraint;
engineConstraint->parentRule = rule;
m_constraintMap[ constraint.m_Type ]->push_back( engineConstraint );
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}
}
}
void DRC_ENGINE::InitEngine( const wxFileName& aRulePath )
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{
m_testProviders = DRC_TEST_PROVIDER_REGISTRY::Instance().GetTestProviders();
for( DRC_TEST_PROVIDER* provider : m_testProviders )
{
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ReportAux( wxString::Format( wxT( "Create DRC provider: '%s'" ), provider->GetName() ) );
provider->SetDRCEngine( this );
}
m_rules.clear();
m_rulesValid = false;
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for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
{
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for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
delete constraint;
delete pair.second;
}
m_constraintMap.clear();
m_board->IncrementTimeStamp(); // Clear board-level caches
try // attempt to load full set of rules (implicit + user rules)
{
loadImplicitRules();
loadRules( aRulePath );
compileRules();
}
catch( PARSE_ERROR& original_parse_error )
{
try // try again with just our implicit rules
{
loadImplicitRules();
compileRules();
}
catch( PARSE_ERROR& )
{
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wxFAIL_MSG( wxT( "Compiling implicit rules failed." ) );
}
throw original_parse_error;
}
for( int ii = DRCE_FIRST; ii < DRCE_LAST; ++ii )
m_errorLimits[ ii ] = ERROR_LIMIT;
m_rulesValid = true;
}
void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aTestFootprints )
{
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m_userUnits = aUnits;
m_reportAllTrackErrors = aReportAllTrackErrors;
m_testFootprints = aTestFootprints;
for( int ii = DRCE_FIRST; ii < DRCE_LAST; ++ii )
{
if( m_designSettings->Ignore( ii ) )
m_errorLimits[ ii ] = 0;
else if( ii == DRCE_CLEARANCE || ii == DRCE_UNCONNECTED_ITEMS )
m_errorLimits[ ii ] = EXTENDED_ERROR_LIMIT;
else
m_errorLimits[ ii ] = ERROR_LIMIT;
}
DRC_TEST_PROVIDER::Init();
m_board->IncrementTimeStamp(); // Invalidate all caches
if( !ReportPhase( _( "Tessellating copper zones..." ) ) )
return;
// Cache zone bounding boxes, triangulation, copper zone rtrees, and footprint courtyards
// before we start.
//
std::vector<ZONE*> allZones = m_board->Zones();
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for( FOOTPRINT* footprint : m_board->Footprints() )
{
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for( ZONE* zone : footprint->Zones() )
allZones.push_back( zone );
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footprint->BuildPolyCourtyards();
}
size_t count = allZones.size();
std::atomic<size_t> next( 0 );
std::atomic<size_t> done( 0 );
std::atomic<size_t> threads_finished( 0 );
size_t parallelThreadCount = std::max<size_t>( std::thread::hardware_concurrency(), 2 );
for( size_t ii = 0; ii < parallelThreadCount; ++ii )
{
std::thread t = std::thread(
[ this, &allZones, &done, &threads_finished, &next, count ]( )
{
for( size_t i = next.fetch_add( 1 ); i < count; i = next.fetch_add( 1 ) )
{
ZONE* zone = allZones[ i ];
zone->CacheBoundingBox();
zone->CacheTriangulation();
if( !zone->GetIsRuleArea() && zone->IsOnCopperLayer() )
{
std::unique_ptr<DRC_RTREE> rtree = std::make_unique<DRC_RTREE>();
for( PCB_LAYER_ID layer : zone->GetLayerSet().Seq() )
{
if( IsCopperLayer( layer ) )
rtree->Insert( zone, layer );
}
std::unique_lock<std::mutex> cacheLock( m_board->m_CachesMutex );
m_board->m_CopperZoneRTrees[ zone ] = std::move( rtree );
}
if( IsCancelled() )
break;
done.fetch_add( 1 );
}
threads_finished.fetch_add( 1 );
} );
t.detach();
}
while( threads_finished < parallelThreadCount )
{
ReportProgress( (double) done / (double) count );
std::this_thread::sleep_for( std::chrono::milliseconds( 100 ) );
}
// Now run the tests.
//
for( DRC_TEST_PROVIDER* provider : m_testProviders )
{
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ReportAux( wxString::Format( wxT( "Run DRC provider: '%s'" ), provider->GetName() ) );
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if( !provider->Run() )
break;
}
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}
#define REPORT( s ) { if( aReporter ) { aReporter->Report( s ); } }
#define UNITS aReporter ? aReporter->GetUnits() : EDA_UNITS::MILLIMETRES
#define REPORT_VALUE( v ) MessageTextFromValue( UNITS, v )
DRC_CONSTRAINT DRC_ENGINE::EvalZoneConnection( const BOARD_ITEM* a, const BOARD_ITEM* b,
PCB_LAYER_ID aLayer, REPORTER* aReporter )
{
DRC_CONSTRAINT constraint = EvalRules( ZONE_CONNECTION_CONSTRAINT, a, b, aLayer, aReporter );
REPORT( "" )
REPORT( wxString::Format( _( "Resolved zone connection type: %s." ),
EscapeHTML( PrintZoneConnection( constraint.m_ZoneConnection ) ) ) )
if( constraint.m_ZoneConnection == ZONE_CONNECTION::THT_THERMAL )
{
const PAD* pad = nullptr;
if( a->Type() == PCB_PAD_T )
pad = static_cast<const PAD*>( a );
else if( b->Type() == PCB_PAD_T )
pad = static_cast<const PAD*>( b );
if( pad && pad->GetAttribute() == PAD_ATTRIB::PTH )
{
constraint.m_ZoneConnection = ZONE_CONNECTION::THERMAL;
}
else
{
REPORT( wxString::Format( _( "Pad is not a through hole pad; connection will be: %s." ),
EscapeHTML( PrintZoneConnection( ZONE_CONNECTION::FULL ) ) ) )
constraint.m_ZoneConnection = ZONE_CONNECTION::FULL;
}
}
return constraint;
}
DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM* a,
const BOARD_ITEM* b, PCB_LAYER_ID aLayer,
REPORTER* aReporter )
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{
/*
* NOTE: all string manipulation MUST BE KEPT INSIDE the REPORT macro. It absolutely
* kills performance when running bulk DRC tests (where aReporter is nullptr).
*/
const BOARD_CONNECTED_ITEM* ac = a && a->IsConnected() ?
static_cast<const BOARD_CONNECTED_ITEM*>( a ) : nullptr;
const BOARD_CONNECTED_ITEM* bc = b && b->IsConnected() ?
static_cast<const BOARD_CONNECTED_ITEM*>( b ) : nullptr;
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bool a_is_non_copper = a && ( !a->IsOnCopperLayer() || isKeepoutZone( a, false ) );
bool b_is_non_copper = b && ( !b->IsOnCopperLayer() || isKeepoutZone( b, false ) );
const PAD* pad = nullptr;
const ZONE* zone = nullptr;
if( aConstraintType == ZONE_CONNECTION_CONSTRAINT
|| aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT
|| aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT )
{
if( a && a->Type() == PCB_PAD_T )
pad = static_cast<const PAD*>( a );
else if( a && ( a->Type() == PCB_ZONE_T || a->Type() == PCB_FP_ZONE_T ) )
zone = static_cast<const ZONE*>( a );
if( b && b->Type() == PCB_PAD_T )
pad = static_cast<const PAD*>( b );
else if( b && ( b->Type() == PCB_ZONE_T || b->Type() == PCB_FP_ZONE_T ) )
zone = static_cast<const ZONE*>( b );
}
DRC_CONSTRAINT constraint;
constraint.m_Type = aConstraintType;
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// Local overrides take precedence over everything *except* board min clearance
if( aConstraintType == CLEARANCE_CONSTRAINT || aConstraintType == HOLE_CLEARANCE_CONSTRAINT )
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{
int override = 0;
if( ac && !b_is_non_copper )
{
int overrideA = ac->GetLocalClearanceOverrides( nullptr );
if( overrideA > 0 )
{
REPORT( "" )
REPORT( wxString::Format( _( "Local override on %s; clearance: %s." ),
EscapeHTML( a->GetSelectMenuText( UNITS ) ),
REPORT_VALUE( overrideA ) ) )
override = ac->GetLocalClearanceOverrides( &m_msg );
}
}
if( bc && !a_is_non_copper )
{
int overrideB = bc->GetLocalClearanceOverrides( nullptr );
if( overrideB > 0 )
{
REPORT( "" )
REPORT( wxString::Format( _( "Local override on %s; clearance: %s." ),
EscapeHTML( b->GetSelectMenuText( UNITS ) ),
EscapeHTML( REPORT_VALUE( overrideB ) ) ) )
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if( overrideB > override )
override = bc->GetLocalClearanceOverrides( &m_msg );
}
}
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if( override )
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{
if( aConstraintType == CLEARANCE_CONSTRAINT )
{
if( override < m_designSettings->m_MinClearance )
{
override = m_designSettings->m_MinClearance;
m_msg = _( "board minimum" );
REPORT( "" )
REPORT( wxString::Format( _( "Board minimum clearance: %s." ),
REPORT_VALUE( override ) ) )
}
}
else
{
if( override < m_designSettings->m_HoleClearance )
{
override = m_designSettings->m_HoleClearance;
m_msg = _( "board minimum hole" );
REPORT( "" )
REPORT( wxString::Format( _( "Board minimum hole clearance: %s." ),
REPORT_VALUE( override ) ) )
}
}
constraint.SetName( m_msg );
constraint.m_Value.SetMin( override );
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return constraint;
}
}
else if( aConstraintType == ZONE_CONNECTION_CONSTRAINT )
{
if( pad && pad->GetLocalZoneConnectionOverride( nullptr ) != ZONE_CONNECTION::INHERITED )
{
ZONE_CONNECTION override = pad->GetLocalZoneConnectionOverride( &m_msg );
REPORT( "" )
REPORT( wxString::Format( _( "Local override on %s; zone connection: %s." ),
EscapeHTML( pad->GetSelectMenuText( UNITS ) ),
EscapeHTML( PrintZoneConnection( override ) ) ) )
constraint.SetName( m_msg );
constraint.m_ZoneConnection = override;
return constraint;
}
}
else if( aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT )
{
if( pad && pad->GetLocalThermalGapOverride( nullptr ) > 0 )
{
int gap_override = pad->GetLocalThermalGapOverride( &m_msg );
REPORT( "" )
REPORT( wxString::Format( _( "Local override on %s; thermal relief gap: %s." ),
EscapeHTML( pad->GetSelectMenuText( UNITS ) ),
EscapeHTML( REPORT_VALUE( gap_override ) ) ) )
constraint.SetName( m_msg );
constraint.m_Value.SetMin( gap_override );
return constraint;
}
}
else if( aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT )
{
if( pad && pad->GetLocalSpokeWidthOverride( nullptr ) > 0 )
{
int spoke_override = pad->GetLocalSpokeWidthOverride( &m_msg );
REPORT( "" )
REPORT( wxString::Format( _( "Local override on %s; thermal spoke width: %s." ),
EscapeHTML( pad->GetSelectMenuText( UNITS ) ),
EscapeHTML( REPORT_VALUE( spoke_override ) ) ) )
if( zone && zone->GetMinThickness() > spoke_override )
{
spoke_override = zone->GetMinThickness();
REPORT( "" )
REPORT( wxString::Format( _( "Zone %s min thickness: %s." ),
EscapeHTML( zone->GetSelectMenuText( UNITS ) ),
EscapeHTML( REPORT_VALUE( spoke_override ) ) ) )
}
constraint.SetName( m_msg );
constraint.m_Value.SetMin( spoke_override );
return constraint;
}
}
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auto testAssertion =
[&]( const DRC_ENGINE_CONSTRAINT* c )
{
REPORT( wxString::Format( _( "Checking assertion \"%s\"." ),
EscapeHTML( c->constraint.m_Test->GetExpression() ) ) )
if( c->constraint.m_Test->EvaluateFor( a, b, aLayer, aReporter ) )
REPORT( _( "Assertion passed." ) )
else
REPORT( EscapeHTML( _( "--> Assertion failed. <--" ) ) )
};
auto processConstraint =
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[&]( const DRC_ENGINE_CONSTRAINT* c ) -> bool
{
bool implicit = c->parentRule && c->parentRule->m_Implicit;
REPORT( "" )
switch( c->constraint.m_Type )
{
case CLEARANCE_CONSTRAINT:
case COURTYARD_CLEARANCE_CONSTRAINT:
case SILK_CLEARANCE_CONSTRAINT:
case HOLE_CLEARANCE_CONSTRAINT:
case EDGE_CLEARANCE_CONSTRAINT:
{
int val = c->constraint.m_Value.Min();
REPORT( wxString::Format( _( "Checking %s clearance: %s." ),
EscapeHTML( c->constraint.GetName() ),
REPORT_VALUE( val ) ) )
break;
}
case TRACK_WIDTH_CONSTRAINT:
case ANNULAR_WIDTH_CONSTRAINT:
case VIA_DIAMETER_CONSTRAINT:
case TEXT_HEIGHT_CONSTRAINT:
case TEXT_THICKNESS_CONSTRAINT:
{
if( aReporter )
{
wxString min = wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" );
wxString opt = wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" );
wxString max = wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" );
wxString msg;
if( implicit )
{
opt = StringFromValue( UNITS, c->constraint.m_Value.Opt(), true );
switch( c->constraint.m_Type )
{
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case TRACK_WIDTH_CONSTRAINT: msg = _( "track width" ); break;
case ANNULAR_WIDTH_CONSTRAINT: msg = _( "annular width" ); break;
case VIA_DIAMETER_CONSTRAINT: msg = _( "via diameter" ); break;
default: msg = _( "constraint" ); break;
}
REPORT( wxString::Format( _( "Checking %s %s: %s." ),
EscapeHTML( c->constraint.GetName() ),
EscapeHTML( msg ),
opt ) )
}
else
{
if( c->constraint.m_Value.HasMin() )
min = StringFromValue( UNITS, c->constraint.m_Value.Min(), true );
if( c->constraint.m_Value.HasOpt() )
opt = StringFromValue( UNITS, c->constraint.m_Value.Opt(), true );
if( c->constraint.m_Value.HasMax() )
max = StringFromValue( UNITS, c->constraint.m_Value.Max(), true );
REPORT( wxString::Format( _( "Checking %s: min %s; opt %s; max %s." ),
EscapeHTML( c->constraint.GetName() ),
min,
opt,
max ) )
}
}
break;
}
default:
REPORT( wxString::Format( _( "Checking %s." ),
EscapeHTML( c->constraint.GetName() ) ) )
}
if( c->constraint.m_Type == CLEARANCE_CONSTRAINT )
{
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if( implicit && ( a_is_non_copper || b_is_non_copper ) )
{
REPORT( _( "Board and netclass clearances apply only between copper "
"items." ) );
return true;
}
}
else if( c->constraint.m_Type == DISALLOW_CONSTRAINT )
{
int mask;
if( a->GetFlags() & HOLE_PROXY )
{
mask = DRC_DISALLOW_HOLES;
}
else if( a->Type() == PCB_VIA_T )
{
mask = DRC_DISALLOW_VIAS;
switch( static_cast<const PCB_VIA*>( a )->GetViaType() )
{
case VIATYPE::BLIND_BURIED: mask |= DRC_DISALLOW_BB_VIAS; break;
case VIATYPE::MICROVIA: mask |= DRC_DISALLOW_MICRO_VIAS; break;
default: break;
}
}
else
{
switch( a->Type() )
{
case PCB_TRACE_T: mask = DRC_DISALLOW_TRACKS; break;
case PCB_ARC_T: mask = DRC_DISALLOW_TRACKS; break;
case PCB_PAD_T: mask = DRC_DISALLOW_PADS; break;
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case PCB_FOOTPRINT_T: mask = DRC_DISALLOW_FOOTPRINTS; break;
case PCB_SHAPE_T: mask = DRC_DISALLOW_GRAPHICS; break;
case PCB_FP_SHAPE_T: mask = DRC_DISALLOW_GRAPHICS; break;
case PCB_TEXT_T: mask = DRC_DISALLOW_TEXTS; break;
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case PCB_TEXTBOX_T: mask = DRC_DISALLOW_TEXTS; break;
case PCB_FP_TEXT_T: mask = DRC_DISALLOW_TEXTS; break;
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case PCB_FP_TEXTBOX_T: mask = DRC_DISALLOW_TEXTS; break;
case PCB_ZONE_T: mask = DRC_DISALLOW_ZONES; break;
case PCB_FP_ZONE_T: mask = DRC_DISALLOW_ZONES; break;
case PCB_LOCATE_HOLE_T: mask = DRC_DISALLOW_HOLES; break;
default: mask = 0; break;
}
}
if( ( c->constraint.m_DisallowFlags & mask ) == 0 )
{
if( implicit )
REPORT( _( "Keepout constraint not met." ) )
else
REPORT( _( "Disallow constraint not met." ) )
return false;
}
LSET itemLayers = a->GetLayerSet();
if( a->Type() == PCB_FOOTPRINT_T )
{
const FOOTPRINT* footprint = static_cast<const FOOTPRINT*>( a );
if( !footprint->GetPolyCourtyard( F_CrtYd ).IsEmpty() )
itemLayers |= LSET::FrontMask();
if( !footprint->GetPolyCourtyard( B_CrtYd ).IsEmpty() )
itemLayers |= LSET::BackMask();
}
if( !( c->layerTest & itemLayers ).any() )
{
if( implicit )
{
REPORT( _( "Keepout layer(s) not matched." ) )
}
else if( c->parentRule )
{
REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
EscapeHTML( c->parentRule->m_LayerSource ) ) )
}
else
{
REPORT( _( "Rule layer not matched; rule ignored." ) )
}
return false;
}
}
if( ( aLayer != UNDEFINED_LAYER && !c->layerTest.test( aLayer ) )
|| ( m_board->GetEnabledLayers() & c->layerTest ).count() == 0 )
{
if( implicit )
{
REPORT( "Constraint layer not matched." )
}
else if( c->parentRule )
{
REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
EscapeHTML( c->parentRule->m_LayerSource ) ) )
}
else
{
REPORT( _( "Rule layer not matched; rule ignored." ) )
}
return false;
}
if( !c->condition || c->condition->GetExpression().IsEmpty() )
{
if( aReporter )
{
if( implicit )
{
REPORT( _( "Unconditional constraint applied." ) )
}
else if( constraint.m_Type == ASSERTION_CONSTRAINT )
{
REPORT( _( "Unconditional rule applied." ) )
testAssertion( c );
}
else
{
REPORT( _( "Unconditional rule applied; overrides previous constraints." ) )
}
}
constraint = c->constraint;
return true;
}
else
{
if( implicit )
{
// Don't report on implicit rule conditions; they're synthetic.
}
else
{
REPORT( wxString::Format( _( "Checking rule condition \"%s\"." ),
EscapeHTML( c->condition->GetExpression() ) ) )
}
if( c->condition->EvaluateFor( a, b, aLayer, aReporter ) )
{
if( aReporter )
{
if( implicit )
{
REPORT( _( "Constraint applied." ) )
}
else if( constraint.m_Type == ASSERTION_CONSTRAINT )
{
REPORT( _( "Rule applied." ) )
testAssertion( c );
}
else
{
REPORT( _( "Rule applied; overrides previous constraints." ) )
}
}
if( c->constraint.m_Value.HasMin() )
constraint.m_Value.SetMin( c->constraint.m_Value.Min() );
if( c->constraint.m_Value.HasOpt() )
constraint.m_Value.SetOpt( c->constraint.m_Value.Opt() );
if( c->constraint.m_Value.HasMax() )
constraint .m_Value.SetMax( c->constraint.m_Value.Max() );
// While the expectation would be to OR the disallow flags, we've already
// masked them down to aItem's type -- so we're really only looking for a
// boolean here.
constraint.m_DisallowFlags = c->constraint.m_DisallowFlags;
constraint.m_ZoneConnection = c->constraint.m_ZoneConnection;
constraint.SetParentRule( c->constraint.GetParentRule() );
return true;
}
else
{
REPORT( implicit ? _( "Membership not satisfied; constraint ignored." )
: _( "Condition not satisfied; rule ignored." ) )
return false;
}
}
};
if( m_constraintMap.count( aConstraintType ) )
{
std::vector<DRC_ENGINE_CONSTRAINT*>* ruleset = m_constraintMap[ aConstraintType ];
for( int ii = 0; ii < (int) ruleset->size(); ++ii )
processConstraint( ruleset->at( ii ) );
}
if( constraint.GetParentRule() && !constraint.GetParentRule()->m_Implicit )
return constraint;
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// Unfortunately implicit rules don't work for local clearances (such as zones) because
// they have to be max'ed with netclass values (which are already implicit rules), and our
// rule selection paradigm is "winner takes all".
if( aConstraintType == CLEARANCE_CONSTRAINT )
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{
int global = constraint.m_Value.Min();
int localA = ac ? ac->GetLocalClearance( nullptr ) : 0;
int localB = bc ? bc->GetLocalClearance( nullptr ) : 0;
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int clearance = global;
if( localA > 0 )
{
REPORT( "" )
REPORT( wxString::Format( _( "Local clearance on %s; clearance: %s." ),
EscapeHTML( a->GetSelectMenuText( UNITS ) ),
REPORT_VALUE( localA ) ) )
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if( localA > clearance )
clearance = ac->GetLocalClearance( &m_msg );
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}
if( localB > 0 )
{
REPORT( "" )
REPORT( wxString::Format( _( "Local clearance on %s; clearance: %s." ),
EscapeHTML( b->GetSelectMenuText( UNITS ) ),
REPORT_VALUE( localB ) ) )
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if( localB > clearance )
clearance = bc->GetLocalClearance( &m_msg );
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}
if( localA > global || localB > global )
{
constraint.SetParentRule( nullptr );
constraint.SetName( m_msg );
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constraint.m_Value.SetMin( clearance );
return constraint;
}
}
else if( aConstraintType == ZONE_CONNECTION_CONSTRAINT )
{
if( pad && pad->GetParent() )
{
FOOTPRINT* footprint = static_cast<FOOTPRINT*>( pad->GetParent() );
ZONE_CONNECTION local = footprint->GetZoneConnection();
if( local != ZONE_CONNECTION::INHERITED )
{
REPORT( "" )
REPORT( wxString::Format( _( "Footprint %s zone connection: %s." ),
EscapeHTML( footprint->GetSelectMenuText( UNITS ) ),
EscapeHTML( PrintZoneConnection( local ) ) ) )
constraint.SetParentRule( nullptr );
constraint.SetName( _( "footprint" ) );
constraint.m_ZoneConnection = local;
return constraint;
}
}
if( zone )
{
ZONE_CONNECTION local = zone->GetPadConnection();
REPORT( "" )
REPORT( wxString::Format( _( "Zone %s pad connection: %s." ),
EscapeHTML( zone->GetSelectMenuText( UNITS ) ),
EscapeHTML( PrintZoneConnection( local ) ) ) )
constraint.SetParentRule( nullptr );
constraint.SetName( _( "zone" ) );
constraint.m_ZoneConnection = local;
return constraint;
}
}
else if( aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT )
{
if( zone )
{
int local = zone->GetThermalReliefGap();
REPORT( "" )
REPORT( wxString::Format( _( "Zone %s thermal relief gap: %s." ),
EscapeHTML( zone->GetSelectMenuText( UNITS ) ),
EscapeHTML( REPORT_VALUE( local ) ) ) )
constraint.SetParentRule( nullptr );
constraint.SetName( _( "zone" ) );
constraint.m_Value.SetMin( local );
return constraint;
}
}
else if( aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT )
{
if( zone )
{
int local = zone->GetThermalReliefSpokeWidth();
REPORT( "" )
REPORT( wxString::Format( _( "Zone %s thermal spoke width: %s." ),
EscapeHTML( zone->GetSelectMenuText( UNITS ) ),
EscapeHTML( REPORT_VALUE( local ) ) ) )
constraint.SetParentRule( nullptr );
constraint.SetName( _( "zone" ) );
constraint.m_Value.SetMin( local );
return constraint;
}
}
if( !constraint.GetParentRule() )
{
constraint.m_Type = NULL_CONSTRAINT;
constraint.m_DisallowFlags = 0;
}
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return constraint;
}
void DRC_ENGINE::ProcessAssertions( const BOARD_ITEM* a,
std::function<void( const DRC_CONSTRAINT* )> aFailureHandler,
REPORTER* aReporter )
{
/*
* NOTE: all string manipulation MUST BE KEPT INSIDE the REPORT macro. It absolutely
* kills performance when running bulk DRC tests (where aReporter is nullptr).
*/
auto testAssertion =
[&]( const DRC_ENGINE_CONSTRAINT* c )
{
REPORT( wxString::Format( _( "Checking rule assertion \"%s\"." ),
EscapeHTML( c->constraint.m_Test->GetExpression() ) ) )
if( c->constraint.m_Test->EvaluateFor( a, nullptr, a->GetLayer(), aReporter ) )
{
REPORT( _( "Assertion passed." ) )
}
else
{
REPORT( EscapeHTML( _( "--> Assertion failed. <--" ) ) )
aFailureHandler( &c->constraint );
}
};
auto processConstraint =
[&]( const DRC_ENGINE_CONSTRAINT* c )
{
REPORT( "" )
REPORT( wxString::Format( _( "Checking %s." ), c->constraint.GetName() ) )
if( !( a->GetLayerSet() & c->layerTest ).any() )
{
REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
EscapeHTML( c->parentRule->m_LayerSource ) ) )
}
if( !c->condition || c->condition->GetExpression().IsEmpty() )
{
REPORT( _( "Unconditional rule applied." ) )
testAssertion( c );
}
else
{
REPORT( wxString::Format( _( "Checking rule condition \"%s\"." ),
EscapeHTML( c->condition->GetExpression() ) ) )
if( c->condition->EvaluateFor( a, nullptr, a->GetLayer(), aReporter ) )
{
REPORT( _( "Rule applied." ) )
testAssertion( c );
}
else
{
REPORT( _( "Condition not satisfied; rule ignored." ) )
}
}
};
if( m_constraintMap.count( ASSERTION_CONSTRAINT ) )
{
std::vector<DRC_ENGINE_CONSTRAINT*>* ruleset = m_constraintMap[ ASSERTION_CONSTRAINT ];
for( int ii = 0; ii < (int) ruleset->size(); ++ii )
processConstraint( ruleset->at( ii ) );
}
}
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#undef REPORT
#undef UNITS
#undef REPORT_VALUE
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bool DRC_ENGINE::IsErrorLimitExceeded( int error_code )
{
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assert( error_code >= 0 && error_code <= DRCE_LAST );
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return m_errorLimits[ error_code ] <= 0;
}
void DRC_ENGINE::ReportViolation( const std::shared_ptr<DRC_ITEM>& aItem, const VECTOR2I& aPos,
PCB_LAYER_ID aMarkerLayer )
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{
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m_errorLimits[ aItem->GetErrorCode() ] -= 1;
if( m_violationHandler )
m_violationHandler( aItem, aPos, aMarkerLayer );
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if( m_reporter )
{
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wxString msg = wxString::Format( wxT( "Test '%s': %s (code %d)" ),
aItem->GetViolatingTest()->GetName(),
aItem->GetErrorMessage(),
aItem->GetErrorCode() );
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DRC_RULE* rule = aItem->GetViolatingRule();
if( rule )
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msg += wxString::Format( wxT( ", violating rule: '%s'" ), rule->m_Name );
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m_reporter->Report( msg );
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wxString violatingItemsStr = wxT( "Violating items: " );
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m_reporter->Report( wxString::Format( wxT( " |- violating position (%d, %d)" ),
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aPos.x,
aPos.y ) );
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}
}
void DRC_ENGINE::ReportAux ( const wxString& aStr )
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{
if( !m_reporter )
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return;
m_reporter->Report( aStr, RPT_SEVERITY_INFO );
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}
bool DRC_ENGINE::ReportProgress( double aProgress )
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{
if( !m_progressReporter )
return true;
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m_progressReporter->SetCurrentProgress( aProgress );
return m_progressReporter->KeepRefreshing( false );
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}
bool DRC_ENGINE::ReportPhase( const wxString& aMessage )
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{
if( !m_progressReporter )
return true;
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m_progressReporter->AdvancePhase( aMessage );
return m_progressReporter->KeepRefreshing( false );
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}
bool DRC_ENGINE::IsCancelled() const
{
return m_progressReporter && m_progressReporter->IsCancelled();
}
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bool DRC_ENGINE::HasRulesForConstraintType( DRC_CONSTRAINT_T constraintID )
{
//drc_dbg(10,"hascorrect id %d size %d\n", ruleID, m_ruleMap[ruleID]->sortedRules.size( ) );
if( m_constraintMap.count( constraintID ) )
return m_constraintMap[ constraintID ]->size() > 0;
return false;
}
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bool DRC_ENGINE::QueryWorstConstraint( DRC_CONSTRAINT_T aConstraintId, DRC_CONSTRAINT& aConstraint )
{
int worst = 0;
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if( m_constraintMap.count( aConstraintId ) )
{
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for( DRC_ENGINE_CONSTRAINT* c : *m_constraintMap[aConstraintId] )
{
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int current = c->constraint.GetValue().Min();
if( current > worst )
{
worst = current;
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aConstraint = c->constraint;
}
}
}
return worst > 0;
}
// fixme: move two functions below to pcbcommon?
int DRC_ENGINE::MatchDpSuffix( const wxString& aNetName, wxString& aComplementNet,
wxString& aBaseDpName )
{
int rv = 0;
int count = 0;
for( auto it = aNetName.rbegin(); it != aNetName.rend() && rv == 0; ++it, ++count )
{
int ch = *it;
if( ( ch >= '0' && ch <= '9' ) || ch == '_' )
{
continue;
}
else if( ch == '+' )
{
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aComplementNet = wxT( "-" );
rv = 1;
}
else if( ch == '-' )
{
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aComplementNet = wxT( "+" );
rv = -1;
}
else if( ch == 'N' )
{
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aComplementNet = wxT( "P" );
rv = -1;
}
else if ( ch == 'P' )
{
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aComplementNet = wxT( "N" );
rv = 1;
}
else
{
break;
}
}
if( rv != 0 && count >= 1 )
{
aBaseDpName = aNetName.Left( aNetName.Length() - count );
aComplementNet = aBaseDpName + aComplementNet + aNetName.Right( count - 1 );
}
return rv;
}
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bool DRC_ENGINE::IsNetADiffPair( BOARD* aBoard, NETINFO_ITEM* aNet, int& aNetP, int& aNetN )
{
wxString refName = aNet->GetNetname();
wxString dummy, coupledNetName;
if( int polarity = MatchDpSuffix( refName, coupledNetName, dummy ) )
{
NETINFO_ITEM* net = aBoard->FindNet( coupledNetName );
if( !net )
return false;
if( polarity > 0 )
{
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aNetP = aNet->GetNetCode();
aNetN = net->GetNetCode();
}
else
{
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aNetP = net->GetNetCode();
aNetN = aNet->GetNetCode();
}
return true;
}
return false;
}
bool DRC_ENGINE::IsNetTie( BOARD_ITEM* aItem )
{
if( aItem->GetParent() && aItem->GetParent()->Type() == PCB_FOOTPRINT_T )
return static_cast<FOOTPRINT*>( aItem->GetParent() )->IsNetTie();
return false;
}
DRC_TEST_PROVIDER* DRC_ENGINE::GetTestProvider( const wxString& name ) const
{
for( auto prov : m_testProviders )
{
if( name == prov->GetName() )
return prov;
}
return nullptr;
}