also fix USB speed class stuff because uuurgh

This now includes the proper pico_sdk_import.cmake so the normal pico-sdk specification and logic works

.gitignore

@@ -1,4 +1,5 @@
 cmake-build/
-build/
+build*/
 ex/
 compile_commands.json
+_old/

.gitmodules

@@ -1,6 +1,3 @@
 [submodule "tinyusb"]
 	path = tinyusb
 	url = https://github.com/hathach/tinyusb
-[submodule "CMSIS_5"]
-	path = CMSIS_5
-	url = https://github.com/ARM-software/CMSIS_5.git

CMSIS-DAP/Core/Include/cachel1_armv7.h

@@ -0,0 +1,411 @@
+/******************************************************************************
+ * @file     cachel1_armv7.h
+ * @brief    CMSIS Level 1 Cache API for Armv7-M and later
+ * @version  V1.0.1
+ * @date     19. April 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_CACHEL1_ARMV7_H
+#define ARM_CACHEL1_ARMV7_H
+
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   I-Cache Invalidate by address
+  \details Invalidates I-Cache for the given address.
+           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           I-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   isize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if ( isize > 0 ) {
+       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_ICACHE_LINE_SIZE;
+        op_size -= __SCB_ICACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address.
+           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr +=          __SCB_DCACHE_LINE_SIZE;
+        op_size -=          __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_CACHEL1_ARMV7_H */

CMSIS-DAP/Core/Include/cmsis_armcc.h

@@ -0,0 +1,888 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.3.2
+ * @date     27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+  __ISB();
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

CMSIS-DAP/Core/Include/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

CMSIS-DAP/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.4
+ * @date     23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

CMSIS-DAP/Core/Include/core_cm0.h

@@ -0,0 +1,952 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to access vector */
+  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to access vector */
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

CMSIS-DAP/Core/Include/core_cm1.h

@@ -0,0 +1,979 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.1
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

CMSIS-DAP/Core/Include/mpu_armv7.h

@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.2
+ * @date     25. May 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

CMSIS-DAP/Core/Include/mpu_armv8.h

@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.3
+ * @date     03. February 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

CMSIS-DAP/Core/Include/pmu_armv8.h

@@ -0,0 +1,337 @@
+/******************************************************************************
+ * @file     pmu_armv8.h
+ * @brief    CMSIS PMU API for Armv8.1-M PMU
+ * @version  V1.0.1
+ * @date     15. April 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_PMU_ARMV8_H
+#define ARM_PMU_ARMV8_H
+
+/**
+ * \brief PMU Events
+ * \note  See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
+ * */
+
+#define ARM_PMU_SW_INCR                              0x0000             /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
+#define ARM_PMU_L1I_CACHE_REFILL                     0x0001             /*!< L1 I-Cache refill */
+#define ARM_PMU_L1D_CACHE_REFILL                     0x0003             /*!< L1 D-Cache refill */
+#define ARM_PMU_L1D_CACHE                            0x0004             /*!< L1 D-Cache access */
+#define ARM_PMU_LD_RETIRED                           0x0006             /*!< Memory-reading instruction architecturally executed and condition code check pass */
+#define ARM_PMU_ST_RETIRED                           0x0007             /*!< Memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_INST_RETIRED                         0x0008             /*!< Instruction architecturally executed */
+#define ARM_PMU_EXC_TAKEN                            0x0009             /*!< Exception entry */
+#define ARM_PMU_EXC_RETURN                           0x000A             /*!< Exception return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_PC_WRITE_RETIRED                     0x000C             /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
+#define ARM_PMU_BR_IMMED_RETIRED                     0x000D             /*!< Immediate branch architecturally executed */
+#define ARM_PMU_BR_RETURN_RETIRED                    0x000E             /*!< Function return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_UNALIGNED_LDST_RETIRED               0x000F             /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BR_MIS_PRED                          0x0010             /*!< Mispredicted or not predicted branch speculatively executed */
+#define ARM_PMU_CPU_CYCLES                           0x0011             /*!< Cycle */
+#define ARM_PMU_BR_PRED                              0x0012             /*!< Predictable branch speculatively executed */
+#define ARM_PMU_MEM_ACCESS                           0x0013             /*!< Data memory access */
+#define ARM_PMU_L1I_CACHE                            0x0014             /*!< Level 1 instruction cache access */
+#define ARM_PMU_L1D_CACHE_WB                         0x0015             /*!< Level 1 data cache write-back */
+#define ARM_PMU_L2D_CACHE                            0x0016             /*!< Level 2 data cache access */
+#define ARM_PMU_L2D_CACHE_REFILL                     0x0017             /*!< Level 2 data cache refill */
+#define ARM_PMU_L2D_CACHE_WB                         0x0018             /*!< Level 2 data cache write-back */
+#define ARM_PMU_BUS_ACCESS                           0x0019             /*!< Bus access */
+#define ARM_PMU_MEMORY_ERROR                         0x001A             /*!< Local memory error */
+#define ARM_PMU_INST_SPEC                            0x001B             /*!< Instruction speculatively executed */
+#define ARM_PMU_BUS_CYCLES                           0x001D             /*!< Bus cycles */
+#define ARM_PMU_CHAIN                                0x001E             /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
+#define ARM_PMU_L1D_CACHE_ALLOCATE                   0x001F             /*!< Level 1 data cache allocation without refill */
+#define ARM_PMU_L2D_CACHE_ALLOCATE                   0x0020             /*!< Level 2 data cache allocation without refill */
+#define ARM_PMU_BR_RETIRED                           0x0021             /*!< Branch instruction architecturally executed */
+#define ARM_PMU_BR_MIS_PRED_RETIRED                  0x0022             /*!< Mispredicted branch instruction architecturally executed */
+#define ARM_PMU_STALL_FRONTEND                       0x0023             /*!< No operation issued because of the frontend */
+#define ARM_PMU_STALL_BACKEND                        0x0024             /*!< No operation issued because of the backend */
+#define ARM_PMU_L2I_CACHE                            0x0027             /*!< Level 2 instruction cache access */
+#define ARM_PMU_L2I_CACHE_REFILL                     0x0028             /*!< Level 2 instruction cache refill */
+#define ARM_PMU_L3D_CACHE_ALLOCATE                   0x0029             /*!< Level 3 data cache allocation without refill */
+#define ARM_PMU_L3D_CACHE_REFILL                     0x002A             /*!< Level 3 data cache refill */
+#define ARM_PMU_L3D_CACHE                            0x002B             /*!< Level 3 data cache access */
+#define ARM_PMU_L3D_CACHE_WB                         0x002C             /*!< Level 3 data cache write-back */
+#define ARM_PMU_LL_CACHE_RD                          0x0036             /*!< Last level data cache read */
+#define ARM_PMU_LL_CACHE_MISS_RD                     0x0037             /*!< Last level data cache read miss */
+#define ARM_PMU_L1D_CACHE_MISS_RD                    0x0039             /*!< Level 1 data cache read miss */
+#define ARM_PMU_OP_COMPLETE                          0x003A             /*!< Operation retired */
+#define ARM_PMU_OP_SPEC                              0x003B             /*!< Operation speculatively executed */
+#define ARM_PMU_STALL                                0x003C             /*!< Stall cycle for instruction or operation not sent for execution */
+#define ARM_PMU_STALL_OP_BACKEND                     0x003D             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
+#define ARM_PMU_STALL_OP_FRONTEND                    0x003E             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
+#define ARM_PMU_STALL_OP                             0x003F             /*!< Instruction or operation slots not occupied each cycle */
+#define ARM_PMU_L1D_CACHE_RD                         0x0040             /*!< Level 1 data cache read */
+#define ARM_PMU_LE_RETIRED                           0x0100             /*!< Loop end instruction executed */
+#define ARM_PMU_LE_SPEC                              0x0101             /*!< Loop end instruction speculatively executed */
+#define ARM_PMU_BF_RETIRED                           0x0104             /*!< Branch future instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BF_SPEC                              0x0105             /*!< Branch future instruction speculatively executed and condition code check pass */
+#define ARM_PMU_LE_CANCEL                            0x0108             /*!< Loop end instruction not taken */
+#define ARM_PMU_BF_CANCEL                            0x0109             /*!< Branch future instruction not taken */
+#define ARM_PMU_SE_CALL_S                            0x0114             /*!< Call to secure function, resulting in Security state change */
+#define ARM_PMU_SE_CALL_NS                           0x0115             /*!< Call to non-secure function, resulting in Security state change */
+#define ARM_PMU_DWT_CMPMATCH0                        0x0118             /*!< DWT comparator 0 match */
+#define ARM_PMU_DWT_CMPMATCH1                        0x0119             /*!< DWT comparator 1 match */
+#define ARM_PMU_DWT_CMPMATCH2                        0x011A             /*!< DWT comparator 2 match */
+#define ARM_PMU_DWT_CMPMATCH3                        0x011B             /*!< DWT comparator 3 match */
+#define ARM_PMU_MVE_INST_RETIRED                     0x0200             /*!< MVE instruction architecturally executed */
+#define ARM_PMU_MVE_INST_SPEC                        0x0201             /*!< MVE instruction speculatively executed */
+#define ARM_PMU_MVE_FP_RETIRED                       0x0204             /*!< MVE floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SPEC                          0x0205             /*!< MVE floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_HP_RETIRED                    0x0208             /*!< MVE half-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_HP_SPEC                       0x0209             /*!< MVE half-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_SP_RETIRED                    0x020C             /*!< MVE single-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SP_SPEC                       0x020D             /*!< MVE single-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_MAC_RETIRED                   0x0214             /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_FP_MAC_SPEC                      0x0215             /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_INT_RETIRED                      0x0224             /*!< MVE integer instruction architecturally executed */
+#define ARM_PMU_MVE_INT_SPEC                         0x0225             /*!< MVE integer instruction speculatively executed */
+#define ARM_PMU_MVE_INT_MAC_RETIRED                  0x0228             /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_INT_MAC_SPEC                     0x0229             /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_RETIRED                     0x0238             /*!< MVE load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_SPEC                        0x0239             /*!< MVE load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_RETIRED                       0x023C             /*!< MVE load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_SPEC                          0x023D             /*!< MVE load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_RETIRED                       0x0240             /*!< MVE store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_SPEC                          0x0241             /*!< MVE store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_CONTIG_RETIRED              0x0244             /*!< MVE contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_CONTIG_SPEC                 0x0245             /*!< MVE contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_CONTIG_RETIRED                0x0248             /*!< MVE contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_CONTIG_SPEC                   0x0249             /*!< MVE contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_CONTIG_RETIRED                0x024C             /*!< MVE contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_CONTIG_SPEC                   0x024D             /*!< MVE contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED           0x0250             /*!< MVE non-contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC              0x0251             /*!< MVE non-contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED             0x0254             /*!< MVE non-contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_SPEC                0x0255             /*!< MVE non-contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED             0x0258             /*!< MVE non-contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_SPEC                0x0259             /*!< MVE non-contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_MULTI_RETIRED               0x025C             /*!< MVE memory instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LDST_MULTI_SPEC                  0x025D             /*!< MVE memory instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LD_MULTI_RETIRED                 0x0260             /*!< MVE memory load instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LD_MULTI_SPEC                    0x0261             /*!< MVE memory load instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_ST_MULTI_RETIRED                 0x0261             /*!< MVE memory store instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_ST_MULTI_SPEC                    0x0265             /*!< MVE memory store instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED           0x028C             /*!< MVE unaligned memory load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC              0x028D             /*!< MVE unaligned memory load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED             0x0290             /*!< MVE unaligned load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_SPEC                0x0291             /*!< MVE unaligned load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED             0x0294             /*!< MVE unaligned store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_SPEC                0x0295             /*!< MVE unaligned store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298             /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC    0x0299             /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_RETIRED                  0x02A0             /*!< MVE vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_SPEC                     0x02A1             /*!< MVE vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_FP_RETIRED               0x02A4             /*!< MVE floating-point vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_FP_SPEC                  0x02A5             /*!< MVE floating-point vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_INT_RETIRED              0x02A8             /*!< MVE integer vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_INT_SPEC                 0x02A9             /*!< MVE integer vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_PRED                             0x02B8             /*!< Cycles where one or more predicated beats architecturally executed */
+#define ARM_PMU_MVE_STALL                            0x02CC             /*!< Stall cycles caused by an MVE instruction */
+#define ARM_PMU_MVE_STALL_RESOURCE                   0x02CD             /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_MEM               0x02CE             /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_FP                0x02CF             /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_INT               0x02D0             /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
+#define ARM_PMU_MVE_STALL_BREAK                      0x02D3             /*!< Stall cycles caused by an MVE chain break */
+#define ARM_PMU_MVE_STALL_DEPENDENCY                 0x02D4             /*!< Stall cycles caused by MVE register dependency */
+#define ARM_PMU_ITCM_ACCESS                          0x4007             /*!< Instruction TCM access */
+#define ARM_PMU_DTCM_ACCESS                          0x4008             /*!< Data TCM access */
+#define ARM_PMU_TRCEXTOUT0                           0x4010             /*!< ETM external output 0 */
+#define ARM_PMU_TRCEXTOUT1                           0x4011             /*!< ETM external output 1 */
+#define ARM_PMU_TRCEXTOUT2                           0x4012             /*!< ETM external output 2 */
+#define ARM_PMU_TRCEXTOUT3                           0x4013             /*!< ETM external output 3 */
+#define ARM_PMU_CTI_TRIGOUT4                         0x4018             /*!< Cross-trigger Interface output trigger 4 */
+#define ARM_PMU_CTI_TRIGOUT5                         0x4019             /*!< Cross-trigger Interface output trigger 5 */
+#define ARM_PMU_CTI_TRIGOUT6                         0x401A             /*!< Cross-trigger Interface output trigger 6 */
+#define ARM_PMU_CTI_TRIGOUT7                         0x401B             /*!< Cross-trigger Interface output trigger 7 */
+
+/** \brief PMU Functions */
+
+__STATIC_INLINE void ARM_PMU_Enable(void);
+__STATIC_INLINE void ARM_PMU_Disable(void);
+
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
+
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
+
+/** 
+  \brief   Enable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Enable(void) 
+{
+  PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
+}
+
+/** 
+  \brief   Disable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Disable(void) 
+{
+  PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
+}
+
+/** 
+  \brief   Set event to count for PMU eventer counter
+  \param [in]    num     Event counter (0-30) to configure
+  \param [in]    type    Event to count
+*/
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
+{
+  PMU->EVTYPER[num] = type;
+}
+
+/** 
+  \brief  Reset cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
+{
+  PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
+}
+
+/** 
+  \brief  Reset all event counters
+*/
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
+{
+  PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
+}
+
+/** 
+  \brief  Enable counters 
+  \param [in]     mask    Counters to enable
+  \note   Enables one or more of the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
+{
+  PMU->CNTENSET = mask;
+}
+
+/** 
+  \brief  Disable counters
+  \param [in]     mask    Counters to enable
+  \note   Disables one or more of the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
+{
+  PMU->CNTENCLR = mask;
+}
+
+/** 
+  \brief  Read cycle counter
+  \return                 Cycle count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
+{
+  return PMU->CCNTR;
+}
+
+/** 
+  \brief   Read event counter
+  \param [in]     num     Event counter (0-30) to read
+  \return                 Event count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
+{
+  return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
+}
+
+/** 
+  \brief   Read counter overflow status
+  \return  Counter overflow status bits for the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
+{
+  return PMU->OVSSET;	
+}
+
+/** 
+  \brief   Clear counter overflow status
+  \param [in]     mask    Counter overflow status bits to clear
+  \note    Clears overflow status bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
+{
+  PMU->OVSCLR = mask;
+}
+
+/** 
+  \brief   Enable counter overflow interrupt request 
+  \param [in]     mask    Counter overflow interrupt request bits to set
+  \note    Sets overflow interrupt request bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
+{
+  PMU->INTENSET = mask;
+}
+
+/** 
+  \brief   Disable counter overflow interrupt request 
+  \param [in]     mask    Counter overflow interrupt request bits to clear
+  \note    Clears overflow interrupt request bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
+{
+  PMU->INTENCLR = mask;
+}
+
+/** 
+  \brief   Software increment event counter 
+  \param [in]     mask    Counters to increment
+  \note    Software increment bits for one or more event counters (0-30)
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
+{
+  PMU->SWINC = mask;
+}
+
+#endif

CMSIS-DAP/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

CMSIS-DAP/Driver/Include/Driver_CAN.h

@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2015-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V1.3
+ *
+ * Project:      CAN (Controller Area Network) Driver definitions
+ */
+
+/* History:
+ *  Version 1.3
+ *    Removed volatile from ARM_CAN_STATUS
+ *  Version 1.2
+ *    Added ARM_CAN_UNIT_STATE_BUS_OFF unit state and
+ *    ARM_CAN_EVENT_UNIT_INACTIVE unit event
+ *  Version 1.1
+ *    ARM_CAN_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_CAN_H_
+#define DRIVER_CAN_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,3)  /* API version */
+
+
+#define _ARM_Driver_CAN_(n)      Driver_CAN##n
+#define  ARM_Driver_CAN_(n) _ARM_Driver_CAN_(n)
+
+
+/****** CAN Bitrate selection codes *****/
+typedef enum _ARM_CAN_BITRATE_SELECT {
+  ARM_CAN_BITRATE_NOMINAL,              ///< Select nominal (flexible data-rate arbitration) bitrate
+  ARM_CAN_BITRATE_FD_DATA               ///< Select flexible data-rate data bitrate
+} ARM_CAN_BITRATE_SELECT;
+
+/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/
+#define ARM_CAN_BIT_PROP_SEG_Pos        0UL       ///< bits 7..0
+#define ARM_CAN_BIT_PROP_SEG_Msk       (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)
+#define ARM_CAN_BIT_PROP_SEG(x)      (((x)     << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk)
+
+/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG1_Pos      8UL       ///< bits 15..8
+#define ARM_CAN_BIT_PHASE_SEG1_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)
+#define ARM_CAN_BIT_PHASE_SEG1(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk)
+
+/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG2_Pos      16UL      ///< bits 23..16
+#define ARM_CAN_BIT_PHASE_SEG2_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)
+#define ARM_CAN_BIT_PHASE_SEG2(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk)
+
+/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/
+#define ARM_CAN_BIT_SJW_Pos             24UL      ///< bits 28..24
+#define ARM_CAN_BIT_SJW_Msk            (0x1FUL << ARM_CAN_BIT_SJW_Pos)
+#define ARM_CAN_BIT_SJW(x)           (((x)     << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk)
+
+/****** CAN Mode codes *****/
+typedef enum _ARM_CAN_MODE {
+  ARM_CAN_MODE_INITIALIZATION,          ///< Initialization mode
+  ARM_CAN_MODE_NORMAL,                  ///< Normal operation mode
+  ARM_CAN_MODE_RESTRICTED,              ///< Restricted operation mode
+  ARM_CAN_MODE_MONITOR,                 ///< Bus monitoring mode
+  ARM_CAN_MODE_LOOPBACK_INTERNAL,       ///< Loopback internal mode
+  ARM_CAN_MODE_LOOPBACK_EXTERNAL        ///< Loopback external mode
+} ARM_CAN_MODE;
+
+/****** CAN Filter Operation codes *****/
+typedef enum _ARM_CAN_FILTER_OPERATION {
+  ARM_CAN_FILTER_ID_EXACT_ADD,          ///< Add    exact id filter
+  ARM_CAN_FILTER_ID_EXACT_REMOVE,       ///< Remove exact id filter
+  ARM_CAN_FILTER_ID_RANGE_ADD,          ///< Add    range id filter
+  ARM_CAN_FILTER_ID_RANGE_REMOVE,       ///< Remove range id filter
+  ARM_CAN_FILTER_ID_MASKABLE_ADD,       ///< Add    maskable id filter
+  ARM_CAN_FILTER_ID_MASKABLE_REMOVE     ///< Remove maskable id filter
+} ARM_CAN_FILTER_OPERATION;
+
+/****** CAN Object Configuration codes *****/
+typedef enum _ARM_CAN_OBJ_CONFIG {
+  ARM_CAN_OBJ_INACTIVE,                 ///< CAN object inactive
+  ARM_CAN_OBJ_TX,                       ///< CAN transmit object
+  ARM_CAN_OBJ_RX,                       ///< CAN receive object
+  ARM_CAN_OBJ_RX_RTR_TX_DATA,           ///< CAN object that on RTR reception automatically transmits Data Frame
+  ARM_CAN_OBJ_TX_RTR_RX_DATA            ///< CAN object that transmits RTR and automatically receives Data Frame
+} ARM_CAN_OBJ_CONFIG;
+
+/**
+\brief CAN Object Capabilities
+*/
+typedef struct _ARM_CAN_OBJ_CAPABILITIES {
+  uint32_t tx               : 1;        ///< Object supports transmission
+  uint32_t rx               : 1;        ///< Object supports reception
+  uint32_t rx_rtr_tx_data   : 1;        ///< Object supports RTR reception and automatic Data Frame transmission
+  uint32_t tx_rtr_rx_data   : 1;        ///< Object supports RTR transmission and automatic Data Frame reception
+  uint32_t multiple_filters : 1;        ///< Object allows assignment of multiple filters to it
+  uint32_t exact_filtering  : 1;        ///< Object supports exact identifier filtering
+  uint32_t range_filtering  : 1;        ///< Object supports range identifier filtering
+  uint32_t mask_filtering   : 1;        ///< Object supports mask identifier filtering
+  uint32_t message_depth    : 8;        ///< Number of messages buffers (FIFO) for that object
+  uint32_t reserved         : 16;       ///< Reserved (must be zero)
+} ARM_CAN_OBJ_CAPABILITIES;
+
+/****** CAN Control Function Operation codes *****/
+#define ARM_CAN_CONTROL_Pos             0UL
+#define ARM_CAN_CONTROL_Msk            (0xFFUL << ARM_CAN_CONTROL_Pos)
+#define ARM_CAN_SET_FD_MODE            (1UL    << ARM_CAN_CONTROL_Pos)          ///< Set FD operation mode;                   arg: 0 = disable, 1 = enable
+#define ARM_CAN_ABORT_MESSAGE_SEND     (2UL    << ARM_CAN_CONTROL_Pos)          ///< Abort sending of CAN message;            arg = object
+#define ARM_CAN_CONTROL_RETRANSMISSION (3UL    << ARM_CAN_CONTROL_Pos)          ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state)
+#define ARM_CAN_SET_TRANSCEIVER_DELAY  (4UL    << ARM_CAN_CONTROL_Pos)          ///< Set transceiver delay;                   arg = delay in time quanta
+
+/****** CAN ID Frame Format codes *****/
+#define ARM_CAN_ID_IDE_Pos              31UL
+#define ARM_CAN_ID_IDE_Msk             (1UL    << ARM_CAN_ID_IDE_Pos)
+
+/****** CAN Identifier encoding *****/
+#define ARM_CAN_STANDARD_ID(id)        (id & 0x000007FFUL)                      ///< CAN identifier in standard format (11-bits)
+#define ARM_CAN_EXTENDED_ID(id)       ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits)
+
+/**
+\brief CAN Message Information
+*/
+typedef struct _ARM_CAN_MSG_INFO {
+  uint32_t id;                          ///< CAN identifier with frame format specifier (bit 31)
+  uint32_t rtr              : 1;        ///< Remote transmission request frame
+  uint32_t edl              : 1;        ///< Flexible data-rate format extended data length
+  uint32_t brs              : 1;        ///< Flexible data-rate format with bitrate switch 
+  uint32_t esi              : 1;        ///< Flexible data-rate format error state indicator
+  uint32_t dlc              : 4;        ///< Data length code
+  uint32_t reserved         : 24;
+} ARM_CAN_MSG_INFO;
+
+/****** CAN specific error code *****/
+#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1)          ///< Bitrate selection not supported
+#define ARM_CAN_INVALID_BITRATE        (ARM_DRIVER_ERROR_SPECIFIC - 2)          ///< Requested bitrate not supported
+#define ARM_CAN_INVALID_BIT_PROP_SEG   (ARM_DRIVER_ERROR_SPECIFIC - 3)          ///< Propagation segment value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4)          ///< Phase segment 1 value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5)          ///< Phase segment 2 value not supported
+#define ARM_CAN_INVALID_BIT_SJW        (ARM_DRIVER_ERROR_SPECIFIC - 6)          ///< SJW value not supported
+#define ARM_CAN_NO_MESSAGE_AVAILABLE   (ARM_DRIVER_ERROR_SPECIFIC - 7)          ///< Message is not available
+
+/****** CAN Status codes *****/
+#define ARM_CAN_UNIT_STATE_INACTIVE    (0U)             ///< Unit state: Not active on bus (initialization)
+#define ARM_CAN_UNIT_STATE_ACTIVE      (1U)             ///< Unit state: Active on bus (can generate active error frame)
+#define ARM_CAN_UNIT_STATE_PASSIVE     (2U)             ///< Unit state: Error passive (can not generate active error frame)
+#define ARM_CAN_UNIT_STATE_BUS_OFF     (3U)             ///< Unit state: Bus-off (can recover to active state)
+#define ARM_CAN_LEC_NO_ERROR           (0U)             ///< Last error code: No error
+#define ARM_CAN_LEC_BIT_ERROR          (1U)             ///< Last error code: Bit error
+#define ARM_CAN_LEC_STUFF_ERROR        (2U)             ///< Last error code: Bit stuffing error
+#define ARM_CAN_LEC_CRC_ERROR          (3U)             ///< Last error code: CRC error
+#define ARM_CAN_LEC_FORM_ERROR         (4U)             ///< Last error code: Illegal fixed-form bit
+#define ARM_CAN_LEC_ACK_ERROR          (5U)             ///< Last error code: Acknowledgment error
+
+/**
+\brief CAN Status
+*/
+typedef struct _ARM_CAN_STATUS {
+  uint32_t unit_state       : 4;        ///< Unit bus state
+  uint32_t last_error_code  : 4;        ///< Last error code
+  uint32_t tx_error_count   : 8;        ///< Transmitter error count
+  uint32_t rx_error_count   : 8;        ///< Receiver error count
+  uint32_t reserved         : 8;
+} ARM_CAN_STATUS;
+
+
+/****** CAN Unit Event *****/
+#define ARM_CAN_EVENT_UNIT_INACTIVE    (0U)             ///< Unit entered Inactive state
+#define ARM_CAN_EVENT_UNIT_ACTIVE      (1U)             ///< Unit entered Error Active state
+#define ARM_CAN_EVENT_UNIT_WARNING     (2U)             ///< Unit entered Error Warning state (one or both error counters >= 96)
+#define ARM_CAN_EVENT_UNIT_PASSIVE     (3U)             ///< Unit entered Error Passive state
+#define ARM_CAN_EVENT_UNIT_BUS_OFF     (4U)             ///< Unit entered Bus-off state
+
+/****** CAN Send/Receive Event *****/
+#define ARM_CAN_EVENT_SEND_COMPLETE    (1UL << 0)       ///< Send complete
+#define ARM_CAN_EVENT_RECEIVE          (1UL << 1)       ///< Message received
+#define ARM_CAN_EVENT_RECEIVE_OVERRUN  (1UL << 2)       ///< Received message overrun
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_CAN_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                                           ARM_CAN_SignalObjectEvent_t cb_object_event)
+  \brief       Initialize CAN interface and register signal (callback) functions.
+  \param[in]   cb_unit_event   Pointer to \ref ARM_CAN_SignalUnitEvent callback function
+  \param[in]   cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_Uninitialize (void)
+  \brief       De-initialize CAN interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)
+  \brief       Control CAN interface power.
+  \param[in]   state  Power state
+                 - \ref ARM_POWER_OFF :  power off: no operation possible
+                 - \ref ARM_POWER_LOW :  low power mode: retain state, detect and signal wake-up events
+                 - \ref ARM_POWER_FULL : power on: full operation at maximum performance
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_CAN_GetClock (void)
+  \brief       Retrieve CAN base clock frequency.
+  \return      base clock frequency
+
+  \fn          int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)
+  \brief       Set bitrate for CAN interface.
+  \param[in]   select       Bitrate selection
+                 - \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate
+                 - \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate
+  \param[in]   bitrate      Bitrate
+  \param[in]   bit_segments Bit segments settings
+                 - \ref ARM_CAN_BIT_PROP_SEG(x) :   number of time quanta for propagation time segment
+                 - \ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1
+                 - \ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2
+                 - \ref ARM_CAN_BIT_SJW(x) :        number of time quanta for (re-)synchronization jump width
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)
+  \brief       Set operating mode for CAN interface.
+  \param[in]   mode   Operating mode
+                 - \ref ARM_CAN_MODE_INITIALIZATION :    initialization mode
+                 - \ref ARM_CAN_MODE_NORMAL :            normal operation mode
+                 - \ref ARM_CAN_MODE_RESTRICTED :        restricted operation mode
+                 - \ref ARM_CAN_MODE_MONITOR :           bus monitoring mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)
+  \brief       Retrieve capabilities of an object.
+  \param[in]   obj_idx  Object index
+  \return      \ref ARM_CAN_OBJ_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)
+  \brief       Add or remove filter for message reception.
+  \param[in]   obj_idx      Object index of object that filter should be or is assigned to
+  \param[in]   operation    Operation on filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_ADD :       add    exact id filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_REMOVE :    remove exact id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_ADD :       add    range id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_REMOVE :    remove range id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_ADD :    add    maskable id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter
+  \param[in]   id           ID or start of ID range (depending on filter type)
+  \param[in]   arg          Mask or end of ID range (depending on filter type)
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)
+  \brief       Configure object.
+  \param[in]   obj_idx  Object index
+  \param[in]   obj_cfg  Object configuration state
+                 - \ref ARM_CAN_OBJ_INACTIVE :       deactivate object
+                 - \ref ARM_CAN_OBJ_RX :             configure object for reception
+                 - \ref ARM_CAN_OBJ_TX :             configure object for transmission
+                 - \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame
+                 - \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)
+  \brief       Send message on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[in]   msg_info Pointer to CAN message information
+  \param[in]   data     Pointer to data buffer
+  \param[in]   size     Number of data bytes to send
+  \return      value >= 0  number of data bytes accepted to send
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)
+  \brief       Read message received on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[out]  msg_info Pointer to read CAN message information
+  \param[out]  data     Pointer to data buffer for read data
+  \param[in]   size     Maximum number of data bytes to read
+  \return      value >= 0  number of data bytes read
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)
+  \brief       Control CAN interface.
+  \param[in]   control  Operation
+                 - \ref ARM_CAN_SET_FD_MODE :            set FD operation mode
+                 - \ref ARM_CAN_ABORT_MESSAGE_SEND :     abort sending of CAN message
+                 - \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission
+                 - \ref ARM_CAN_SET_TRANSCEIVER_DELAY :  set transceiver delay
+  \param[in]   arg      Argument of operation
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_STATUS ARM_CAN_GetStatus (void)
+  \brief       Get CAN status.
+  \return      CAN status \ref ARM_CAN_STATUS
+
+  \fn          void ARM_CAN_SignalUnitEvent (uint32_t event)
+  \brief       Signal CAN unit event.
+  \param[in]   event \ref CAN_unit_events
+  \return      none
+
+  \fn          void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)
+  \brief       Signal CAN object event.
+  \param[in]   obj_idx  Object index
+  \param[in]   event \ref CAN_events
+  \return      none
+*/
+
+typedef void (*ARM_CAN_SignalUnitEvent_t)   (uint32_t event);                   ///< Pointer to \ref ARM_CAN_SignalUnitEvent   : Signal CAN Unit Event.
+typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event.
+
+
+/**
+\brief CAN Device Driver Capabilities.
+*/
+typedef struct _ARM_CAN_CAPABILITIES {
+  uint32_t num_objects            : 8;  ///< Number of \ref can_objects available
+  uint32_t reentrant_operation    : 1;  ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control
+  uint32_t fd_mode                : 1;  ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control)
+  uint32_t restricted_mode        : 1;  ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode)
+  uint32_t monitor_mode           : 1;  ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode)
+  uint32_t internal_loopback      : 1;  ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t external_loopback      : 1;  ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t reserved               : 18; ///< Reserved (must be zero)
+} ARM_CAN_CAPABILITIES;
+
+
+/**
+\brief Access structure of the CAN Driver.
+*/
+typedef struct _ARM_DRIVER_CAN {
+  ARM_DRIVER_VERSION       (*GetVersion)            (void);                             ///< Pointer to \ref ARM_CAN_GetVersion            : Get driver version.
+  ARM_CAN_CAPABILITIES     (*GetCapabilities)       (void);                             ///< Pointer to \ref ARM_CAN_GetCapabilities       : Get driver capabilities.
+  int32_t                  (*Initialize)            (ARM_CAN_SignalUnitEvent_t   cb_unit_event,                     
+                                                     ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface.
+  int32_t                  (*Uninitialize)          (void);                             ///< Pointer to \ref ARM_CAN_Uninitialize          : De-initialize CAN interface.
+  int32_t                  (*PowerControl)          (ARM_POWER_STATE          state);   ///< Pointer to \ref ARM_CAN_PowerControl          : Control CAN interface power.
+  uint32_t                 (*GetClock)              (void);                             ///< Pointer to \ref ARM_CAN_GetClock              : Retrieve CAN base clock frequency.
+  int32_t                  (*SetBitrate)            (ARM_CAN_BITRATE_SELECT   select,
+                                                     uint32_t                 bitrate,
+                                                     uint32_t                 bit_segments);       ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface.
+  int32_t                  (*SetMode)               (ARM_CAN_MODE             mode);    ///< Pointer to \ref ARM_CAN_SetMode               : Set operating mode for CAN interface.
+  ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t                 obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object.
+  int32_t                  (*ObjectSetFilter)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_FILTER_OPERATION operation,
+                                                     uint32_t                 id,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_ObjectSetFilter       : Add or remove filter for message reception.
+  int32_t                  (*ObjectConfigure)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_OBJ_CONFIG       obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure       : Configure object.
+  int32_t                  (*MessageSend)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     const uint8_t           *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageSend           : Send message on CAN bus.
+  int32_t                  (*MessageRead)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     uint8_t                 *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageRead           : Read message received on CAN bus.
+  int32_t                  (*Control)               (uint32_t                 control,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_Control               : Control CAN interface.
+  ARM_CAN_STATUS           (*GetStatus)             (void);                             ///< Pointer to \ref ARM_CAN_GetStatus             : Get CAN status.
+} const ARM_DRIVER_CAN;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_CAN_H_ */

CMSIS-DAP/Driver/Include/Driver_Common.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.0
+ *
+ * Project:      Common Driver definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Added General return codes definitions
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_COMMON_H_
+#define DRIVER_COMMON_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded 
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors 
+
+/**
+\brief General power states
+*/ 
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* DRIVER_COMMON_H_ */

CMSIS-DAP/Driver/Include/Driver_ETH.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.2
+ *
+ * Project:      Ethernet PHY and MAC Driver common definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    Removed volatile from ARM_ETH_LINK_INFO
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    Removed ARM_ETH_STATUS enumerator
+ *    Removed ARM_ETH_MODE enumerator
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_H_
+#define DRIVER_ETH_H_
+
+#include "Driver_Common.h"
+
+/**
+\brief Ethernet Media Interface type
+*/
+#define ARM_ETH_INTERFACE_MII           (0U)    ///< Media Independent Interface (MII)
+#define ARM_ETH_INTERFACE_RMII          (1U)    ///< Reduced Media Independent Interface (RMII)
+#define ARM_ETH_INTERFACE_SMII          (2U)    ///< Serial Media Independent Interface (SMII)
+
+/**
+\brief Ethernet link speed
+*/
+#define ARM_ETH_SPEED_10M               (0U)    ///< 10 Mbps link speed
+#define ARM_ETH_SPEED_100M              (1U)    ///< 100 Mbps link speed
+#define ARM_ETH_SPEED_1G                (2U)    ///< 1 Gpbs link speed
+
+/**
+\brief Ethernet duplex mode
+*/
+#define ARM_ETH_DUPLEX_HALF             (0U)    ///< Half duplex link
+#define ARM_ETH_DUPLEX_FULL             (1U)    ///< Full duplex link
+
+/**
+\brief Ethernet link state
+*/
+typedef enum _ARM_ETH_LINK_STATE {
+  ARM_ETH_LINK_DOWN,                    ///< Link is down
+  ARM_ETH_LINK_UP                       ///< Link is up
+} ARM_ETH_LINK_STATE;
+
+/**
+\brief Ethernet link information
+*/
+typedef struct _ARM_ETH_LINK_INFO {
+  uint32_t speed    : 2;                ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
+  uint32_t duplex   : 1;                ///< Duplex mode: 0= Half, 1= Full
+  uint32_t reserved : 29;
+} ARM_ETH_LINK_INFO;
+
+/**
+\brief Ethernet MAC Address
+*/
+typedef struct _ARM_ETH_MAC_ADDR {
+  uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first
+} ARM_ETH_MAC_ADDR;
+
+#endif /* DRIVER_ETH_H_ */

CMSIS-DAP/Driver/Include/Driver_ETH_MAC.h

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.2
+ *
+ * Project:      Ethernet MAC (Media Access Control) Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    Removed volatile from ARM_ETH_LINK_INFO
+ *  Version 2.1
+ *    Added ARM_ETH_MAC_SLEEP Control
+ *  Version 2.0
+ *    Changed MAC Address handling:
+ *      moved from ARM_ETH_MAC_Initialize
+ *      to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress
+ *    Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter
+ *    Extended ARM_ETH_MAC_SendFrame function with flags
+ *    Added ARM_ETH_MAC_Control function:
+ *      more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)
+ *      replaces ARM_ETH_MAC_SetMode
+ *      replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx
+ *    Added optional event on transmitted frame
+ *    Added support for PTP (Precision Time Protocol) through new functions:
+ *       ARM_ETH_MAC_ControlTimer
+ *       ARM_ETH_MAC_GetRxFrameTime
+ *       ARM_ETH_MAC_GetTxFrameTime
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Name space prefix ARM_ added
+ *  Version 1.01
+ *    Renamed capabilities items for checksum offload
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_MAC_H_
+#define DRIVER_ETH_MAC_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+#define _ARM_Driver_ETH_MAC_(n)      Driver_ETH_MAC##n
+#define  ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)
+
+
+/****** Ethernet MAC Control Codes *****/
+
+#define ARM_ETH_MAC_CONFIGURE           (0x01UL)    ///< Configure MAC; arg = configuration
+#define ARM_ETH_MAC_CONTROL_TX          (0x02UL)    ///< Transmitter; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_CONTROL_RX          (0x03UL)    ///< Receiver; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_FLUSH               (0x04UL)    ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...
+#define ARM_ETH_MAC_SLEEP               (0x05UL)    ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
+#define ARM_ETH_MAC_VLAN_FILTER         (0x06UL)    ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
+
+/*----- Ethernet MAC Configuration -----*/
+#define ARM_ETH_MAC_SPEED_Pos            0
+#define ARM_ETH_MAC_SPEED_Msk           (3UL                 << ARM_ETH_MAC_SPEED_Pos)
+#define ARM_ETH_MAC_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_MAC_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_MAC_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_MAC_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_MAC_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_MAC_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_MAC_DUPLEX_Pos           2
+#define ARM_ETH_MAC_DUPLEX_Msk          (1UL                 << ARM_ETH_MAC_DUPLEX_Pos)
+#define ARM_ETH_MAC_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_MAC_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_MAC_LOOPBACK            (1UL << 4)  ///< Loop-back test mode
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5)  ///< Receiver Checksum offload
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6)  ///< Transmitter Checksum offload
+#define ARM_ETH_MAC_ADDRESS_BROADCAST   (1UL << 7)  ///< Accept frames with Broadcast address
+#define ARM_ETH_MAC_ADDRESS_MULTICAST   (1UL << 8)  ///< Accept frames with any Multicast address
+#define ARM_ETH_MAC_ADDRESS_ALL         (1UL << 9)  ///< Accept frames with any address (Promiscuous Mode)
+
+/*----- Ethernet MAC Flush Flags -----*/
+#define ARM_ETH_MAC_FLUSH_RX            (1UL << 0)  ///< Flush Receive buffer
+#define ARM_ETH_MAC_FLUSH_TX            (1UL << 1)  ///< Flush Transmit buffer
+
+/*----- Ethernet MAC VLAN Filter Flag -----*/
+#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
+
+
+/****** Ethernet MAC Frame Transmit Flags *****/
+#define ARM_ETH_MAC_TX_FRAME_FRAGMENT   (1UL << 0)  ///< Indicate frame fragment
+#define ARM_ETH_MAC_TX_FRAME_EVENT      (1UL << 1)  ///< Generate event when frame is transmitted
+#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP  (1UL << 2)  ///< Capture frame time stamp
+
+
+/****** Ethernet MAC Timer Control Codes *****/
+#define ARM_ETH_MAC_TIMER_GET_TIME      (0x01UL)    ///< Get current time
+#define ARM_ETH_MAC_TIMER_SET_TIME      (0x02UL)    ///< Set new time
+#define ARM_ETH_MAC_TIMER_INC_TIME      (0x03UL)    ///< Increment current time
+#define ARM_ETH_MAC_TIMER_DEC_TIME      (0x04UL)    ///< Decrement current time
+#define ARM_ETH_MAC_TIMER_SET_ALARM     (0x05UL)    ///< Set alarm time
+#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK  (0x06UL)    ///< Adjust clock frequency; time->ns: correction factor * 2^31
+
+
+/**
+\brief Ethernet MAC Time
+*/
+typedef struct _ARM_ETH_MAC_TIME {
+  uint32_t ns;                          ///< Nano seconds
+  uint32_t sec;                         ///< Seconds
+} ARM_ETH_MAC_TIME;
+
+
+/****** Ethernet MAC Event *****/
+#define ARM_ETH_MAC_EVENT_RX_FRAME      (1UL << 0)  ///< Frame Received
+#define ARM_ETH_MAC_EVENT_TX_FRAME      (1UL << 1)  ///< Frame Transmitted
+#define ARM_ETH_MAC_EVENT_WAKEUP        (1UL << 2)  ///< Wake-up (on Magic Packet)
+#define ARM_ETH_MAC_EVENT_TIMER_ALARM   (1UL << 3)  ///< Timer Alarm
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_ETH_MAC_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
+  \brief       Initialize Ethernet MAC Device.
+  \param[in]   cb_event  Pointer to \ref ARM_ETH_MAC_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Uninitialize (void)
+  \brief       De-initialize Ethernet MAC Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet MAC Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Get Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Set Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
+                                                           uint32_t          num_addr)
+  \brief       Configure Address Filter.
+  \param[in]   ptr_addr  Pointer to addresses
+  \param[in]   num_addr  Number of addresses to configure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
+  \brief       Send Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer with data to send
+  \param[in]   len    Frame buffer length in bytes
+  \param[in]   flags  Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)
+  \brief       Read data of received Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer for data to read into
+  \param[in]   len    Frame buffer length in bytes
+  \return      number of data bytes read or execution status
+                 - value >= 0: number of data bytes read
+                 - value < 0: error occurred, value is execution status as defined with \ref execution_status 
+*/
+/**
+  \fn          uint32_t ARM_ETH_MAC_GetRxFrameSize (void)
+  \brief       Get size of received Ethernet frame.
+  \return      number of bytes in received frame
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of received Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of transmitted Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)
+  \brief       Control Ethernet Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
+  \brief       Control Precision Timer.
+  \param[in]   control  Operation
+  \param[in]   time     Pointer to time structure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+  \brief       Read Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[out]  data      Pointer where the result is written to
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+  \brief       Write Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[in]   data      16-bit data to write
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_ETH_MAC_SignalEvent (uint32_t event)
+  \brief       Callback function that signals a Ethernet Event.
+  \param[in]   event  event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.
+
+
+/**
+\brief Ethernet MAC Capabilities
+*/
+typedef struct _ARM_ETH_MAC_CAPABILITIES {
+  uint32_t checksum_offload_rx_ip4  : 1;        ///< 1 = IPv4 header checksum verified on receive
+  uint32_t checksum_offload_rx_ip6  : 1;        ///< 1 = IPv6 checksum verification supported on receive
+  uint32_t checksum_offload_rx_udp  : 1;        ///< 1 = UDP payload checksum verified on receive
+  uint32_t checksum_offload_rx_tcp  : 1;        ///< 1 = TCP payload checksum verified on receive
+  uint32_t checksum_offload_rx_icmp : 1;        ///< 1 = ICMP payload checksum verified on receive
+  uint32_t checksum_offload_tx_ip4  : 1;        ///< 1 = IPv4 header checksum generated on transmit
+  uint32_t checksum_offload_tx_ip6  : 1;        ///< 1 = IPv6 checksum generation supported on transmit
+  uint32_t checksum_offload_tx_udp  : 1;        ///< 1 = UDP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_tcp  : 1;        ///< 1 = TCP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_icmp : 1;        ///< 1 = ICMP payload checksum generated on transmit
+  uint32_t media_interface          : 2;        ///< Ethernet Media Interface type
+  uint32_t mac_address              : 1;        ///< 1 = driver provides initial valid MAC address
+  uint32_t event_rx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated
+  uint32_t event_tx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated
+  uint32_t event_wakeup             : 1;        ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated
+  uint32_t precision_timer          : 1;        ///< 1 = Precision Timer supported
+  uint32_t reserved                 : 15;       ///< Reserved (must be zero)
+} ARM_ETH_MAC_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Ethernet MAC Driver
+*/
+typedef struct _ARM_DRIVER_ETH_MAC {
+  ARM_DRIVER_VERSION       (*GetVersion)      (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version.
+  ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)      (ARM_ETH_MAC_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.
+  int32_t                  (*Uninitialize)    (void);                                                ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.
+  int32_t                  (*PowerControl)    (ARM_POWER_STATE state);                               ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.
+  int32_t                  (*GetMacAddress)   (      ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.
+  int32_t                  (*SetMacAddress)   (const ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.
+  int32_t                  (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.
+  int32_t                  (*SendFrame)       (const uint8_t *frame, uint32_t len, uint32_t flags);  ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.
+  int32_t                  (*ReadFrame)       (      uint8_t *frame, uint32_t len);                  ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.
+  uint32_t                 (*GetRxFrameSize)  (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.
+  int32_t                  (*GetRxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.
+  int32_t                  (*GetTxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.
+  int32_t                  (*ControlTimer)    (uint32_t control, ARM_ETH_MAC_TIME *time);            ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.
+  int32_t                  (*Control)         (uint32_t control, uint32_t arg);                      ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface.
+  int32_t                  (*PHY_Read)        (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.
+  int32_t                  (*PHY_Write)       (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.
+} const ARM_DRIVER_ETH_MAC;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_MAC_H_ */

CMSIS-DAP/Driver/Include/Driver_ETH_PHY.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.2
+ *
+ * Project:      Ethernet PHY (Physical Transceiver) Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    Removed volatile from ARM_ETH_LINK_INFO
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    changed parameter "mode" in function ARM_ETH_PHY_SetMode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_PHY_H_
+#define DRIVER_ETH_PHY_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+#define _ARM_Driver_ETH_PHY_(n)      Driver_ETH_PHY##n
+#define  ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)
+
+
+/****** Ethernet PHY Mode *****/
+#define ARM_ETH_PHY_SPEED_Pos            0
+#define ARM_ETH_PHY_SPEED_Msk           (3UL                 << ARM_ETH_PHY_SPEED_Pos)
+#define ARM_ETH_PHY_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_PHY_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_PHY_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_PHY_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_PHY_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_PHY_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_PHY_DUPLEX_Pos           2
+#define ARM_ETH_PHY_DUPLEX_Msk          (1UL                 << ARM_ETH_PHY_DUPLEX_Pos)
+#define ARM_ETH_PHY_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_PHY_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_PHY_AUTO_NEGOTIATE      (1UL << 3)                                      ///< Auto Negotiation mode
+#define ARM_ETH_PHY_LOOPBACK            (1UL << 4)                                      ///< Loop-back test mode
+#define ARM_ETH_PHY_ISOLATE             (1UL << 5)                                      ///< Isolate PHY from MII/RMII interface
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t  fn_read,
+                                               ARM_ETH_PHY_Write_t fn_write)
+  \brief       Initialize Ethernet PHY Device.
+  \param[in]   fn_read   Pointer to \ref ARM_ETH_MAC_PHY_Read
+  \param[in]   fn_write  Pointer to \ref ARM_ETH_MAC_PHY_Write
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Uninitialize (void)
+  \brief       De-initialize Ethernet PHY Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet PHY Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)
+  \brief       Set Ethernet Media Interface.
+  \param[in]   interface  Media Interface type
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetMode (uint32_t mode)
+  \brief       Set Ethernet PHY Device Operation mode.
+  \param[in]   mode  Operation Mode
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)
+  \brief       Get Ethernet PHY Device Link state.
+  \return      current link status \ref ARM_ETH_LINK_STATE
+*/
+/**
+  \fn          ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)
+  \brief       Get Ethernet PHY Device Link information.
+  \return      current link parameters \ref ARM_ETH_LINK_INFO
+*/
+
+
+typedef int32_t (*ARM_ETH_PHY_Read_t)  (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.
+typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.
+
+
+/**
+\brief Access structure of the Ethernet PHY Driver
+*/
+typedef struct _ARM_DRIVER_ETH_PHY {
+  ARM_DRIVER_VERSION (*GetVersion)   (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version.
+  int32_t            (*Initialize)   (ARM_ETH_PHY_Read_t  fn_read,
+                                      ARM_ETH_PHY_Write_t fn_write);  ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device.
+  int32_t            (*Uninitialize) (void);                          ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.
+  int32_t            (*PowerControl) (ARM_POWER_STATE state);         ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.
+  int32_t            (*SetInterface) (uint32_t interface);            ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.
+  int32_t            (*SetMode)      (uint32_t mode);                 ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.
+  ARM_ETH_LINK_STATE (*GetLinkState) (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.
+  ARM_ETH_LINK_INFO  (*GetLinkInfo)  (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.
+} const ARM_DRIVER_ETH_PHY;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_PHY_H_ */

CMSIS-DAP/Driver/Include/Driver_Flash.h

@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.3
+ *
+ * Project:      Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Removed volatile from ARM_FLASH_STATUS
+ *  Version 2.2
+ *    Padding bytes added to ARM_FLASH_INFO
+ *  Version 2.1
+ *    ARM_FLASH_STATUS made volatile
+ *  Version 2.0
+ *    Renamed driver NOR -> Flash (more generic)
+ *    Non-blocking operation
+ *    Added Events, Status and Capabilities
+ *    Linked Flash information (GetInfo)
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_FLASH_H_
+#define DRIVER_FLASH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_Flash_(n)      Driver_Flash##n
+#define  ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
+
+
+#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
+
+/**
+\brief Flash Sector information
+*/
+typedef struct _ARM_FLASH_SECTOR {
+  uint32_t start;                       ///< Sector Start address
+  uint32_t end;                         ///< Sector End address (start+size-1)
+} const ARM_FLASH_SECTOR;
+
+/**
+\brief Flash information
+*/
+typedef struct _ARM_FLASH_INFO {
+  ARM_FLASH_SECTOR *sector_info;        ///< Sector layout information (NULL=Uniform sectors)
+  uint32_t          sector_count;       ///< Number of sectors
+  uint32_t          sector_size;        ///< Uniform sector size in bytes (0=sector_info used) 
+  uint32_t          page_size;          ///< Optimal programming page size in bytes
+  uint32_t          program_unit;       ///< Smallest programmable unit in bytes
+  uint8_t           erased_value;       ///< Contents of erased memory (usually 0xFF)
+  uint8_t           reserved[3];        ///< Reserved (must be zero)
+} const ARM_FLASH_INFO;
+
+
+/**
+\brief Flash Status
+*/
+typedef struct _ARM_FLASH_STATUS {
+  uint32_t busy     : 1;                ///< Flash busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_FLASH_STATUS;
+
+
+/****** Flash Event *****/
+#define ARM_FLASH_EVENT_READY           (1UL << 0)  ///< Flash Ready
+#define ARM_FLASH_EVENT_ERROR           (1UL << 1)  ///< Read/Program/Erase Error
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_FLASH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
+  \brief       Initialize the Flash Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_Flash_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_Uninitialize (void)
+  \brief       De-initialize the Flash Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Flash interface power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
+  \brief       Read data from Flash.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   cnt   Number of data items to read.
+  \return      number of data items read or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
+  \brief       Program data to Flash.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseSector (uint32_t addr)
+  \brief       Erase Flash Sector.
+  \param[in]   addr  Sector address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseChip (void)
+  \brief       Erase complete Flash.
+               Optional function for faster full chip erase.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
+  \brief       Get Flash status.
+  \return      Flash status \ref ARM_FLASH_STATUS
+*/
+/**
+  \fn          ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
+  \brief       Get Flash information.
+  \return      Pointer to Flash information \ref ARM_FLASH_INFO
+*/
+
+/**
+  \fn          void ARM_Flash_SignalEvent (uint32_t event)
+  \brief       Signal Flash event.
+  \param[in]   event  Event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event);    ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
+
+
+/**
+\brief Flash Driver Capabilities.
+*/
+typedef struct _ARM_FLASH_CAPABILITIES {
+  uint32_t event_ready  : 1;            ///< Signal Flash Ready event
+  uint32_t data_width   : 2;            ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
+  uint32_t erase_chip   : 1;            ///< Supports EraseChip operation
+  uint32_t reserved     : 28;           ///< Reserved (must be zero)
+} ARM_FLASH_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Flash Driver
+*/
+typedef struct _ARM_DRIVER_FLASH {
+  ARM_DRIVER_VERSION     (*GetVersion)     (void);                                          ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
+  ARM_FLASH_CAPABILITIES (*GetCapabilities)(void);                                          ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)     (ARM_Flash_SignalEvent_t cb_event);              ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
+  int32_t                (*Uninitialize)   (void);                                          ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
+  int32_t                (*PowerControl)   (ARM_POWER_STATE state);                         ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
+  int32_t                (*ReadData)       (uint32_t addr,       void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
+  int32_t                (*ProgramData)    (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
+  int32_t                (*EraseSector)    (uint32_t addr);                                 ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
+  int32_t                (*EraseChip)      (void);                                          ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
+  ARM_FLASH_STATUS       (*GetStatus)      (void);                                          ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
+  ARM_FLASH_INFO *       (*GetInfo)        (void);                                          ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
+} const ARM_DRIVER_FLASH;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_FLASH_H_ */

CMSIS-DAP/Driver/Include/Driver_I2C.h

@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      I2C (Inter-Integrated Circuit) Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_I2C_STATUS
+ *  Version 2.3
+ *    ARM_I2C_STATUS made volatile
+ *  Version 2.2
+ *    Removed function ARM_I2C_MasterTransfer in order to simplify drivers
+ *      and added back parameter "xfer_pending" to functions
+ *      ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *  Version 2.1
+ *    Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending"
+ *      from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *    Added function ARM_I2C_GetDataCount
+ *    Removed flag "address_nack" from ARM_I2C_STATUS
+ *    Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE
+ *      with event ARM_I2C_EVENT_TRANSFER_DONE
+ *    Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE
+ *    Removed parameter "arg" from function ARM_I2C_SignalEvent
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_I2C_H_
+#define DRIVER_I2C_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_I2C_(n)      Driver_I2C##n
+#define  ARM_Driver_I2C_(n) _ARM_Driver_I2C_(n)
+
+
+/****** I2C Control Codes *****/
+
+#define ARM_I2C_OWN_ADDRESS             (0x01UL)    ///< Set Own Slave Address; arg = address 
+#define ARM_I2C_BUS_SPEED               (0x02UL)    ///< Set Bus Speed; arg = speed
+#define ARM_I2C_BUS_CLEAR               (0x03UL)    ///< Execute Bus clear: send nine clock pulses
+#define ARM_I2C_ABORT_TRANSFER          (0x04UL)    ///< Abort Master/Slave Transmit/Receive
+
+/*----- I2C Bus Speed -----*/
+#define ARM_I2C_BUS_SPEED_STANDARD      (0x01UL)    ///< Standard Speed (100kHz)
+#define ARM_I2C_BUS_SPEED_FAST          (0x02UL)    ///< Fast Speed     (400kHz)
+#define ARM_I2C_BUS_SPEED_FAST_PLUS     (0x03UL)    ///< Fast+ Speed    (  1MHz)
+#define ARM_I2C_BUS_SPEED_HIGH          (0x04UL)    ///< High Speed     (3.4MHz)
+
+
+/****** I2C Address Flags *****/
+
+#define ARM_I2C_ADDRESS_10BIT           (0x0400UL)  ///< 10-bit address flag
+#define ARM_I2C_ADDRESS_GC              (0x8000UL)  ///< General Call flag
+
+
+/**
+\brief I2C Status
+*/
+typedef struct _ARM_I2C_STATUS {
+  uint32_t busy             : 1;        ///< Busy flag
+  uint32_t mode             : 1;        ///< Mode: 0=Slave, 1=Master
+  uint32_t direction        : 1;        ///< Direction: 0=Transmitter, 1=Receiver
+  uint32_t general_call     : 1;        ///< General Call indication (cleared on start of next Slave operation)
+  uint32_t arbitration_lost : 1;        ///< Master lost arbitration (cleared on start of next Master operation)
+  uint32_t bus_error        : 1;        ///< Bus error detected (cleared on start of next Master/Slave operation)
+  uint32_t reserved         : 26;
+} ARM_I2C_STATUS;
+
+
+/****** I2C Event *****/
+#define ARM_I2C_EVENT_TRANSFER_DONE       (1UL << 0)  ///< Master/Slave Transmit/Receive finished
+#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1)  ///< Master/Slave Transmit/Receive incomplete transfer
+#define ARM_I2C_EVENT_SLAVE_TRANSMIT      (1UL << 2)  ///< Addressed as Slave Transmitter but transmit operation is not set.
+#define ARM_I2C_EVENT_SLAVE_RECEIVE       (1UL << 3)  ///< Addressed as Slave Receiver but receive operation is not set.
+#define ARM_I2C_EVENT_ADDRESS_NACK        (1UL << 4)  ///< Address not acknowledged from Slave
+#define ARM_I2C_EVENT_GENERAL_CALL        (1UL << 5)  ///< Slave addressed with general call address
+#define ARM_I2C_EVENT_ARBITRATION_LOST    (1UL << 6)  ///< Master lost arbitration
+#define ARM_I2C_EVENT_BUS_ERROR           (1UL << 7)  ///< Bus error detected (START/STOP at illegal position)
+#define ARM_I2C_EVENT_BUS_CLEAR           (1UL << 8)  ///< Bus clear finished
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_I2C_CAPABILITIES
+
+  \fn          int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
+  \brief       Initialize I2C Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_I2C_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_Uninitialize (void)
+  \brief       De-initialize I2C Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)
+  \brief       Control I2C Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start transmitting data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[in]   data          Pointer to buffer with data to transmit to I2C Slave
+  \param[in]   num           Number of data bytes to transmit
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start receiving data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[out]  data          Pointer to buffer for data to receive from I2C Slave
+  \param[in]   num           Number of data bytes to receive
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)
+  \brief       Start transmitting data as I2C Slave.
+  \param[in]   data  Pointer to buffer with data to transmit to I2C Master
+  \param[in]   num   Number of data bytes to transmit
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)
+  \brief       Start receiving data as I2C Slave.
+  \param[out]  data  Pointer to buffer for data to receive from I2C Master
+  \param[in]   num   Number of data bytes to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data bytes transferred; -1 when Slave is not addressed by Master
+
+  \fn          int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)
+  \brief       Control I2C Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+
+  \fn          ARM_I2C_STATUS ARM_I2C_GetStatus (void)
+  \brief       Get I2C status.
+  \return      I2C status \ref ARM_I2C_STATUS
+
+  \fn          void ARM_I2C_SignalEvent (uint32_t event)
+  \brief       Signal I2C Events.
+  \param[in]   event  \ref I2C_events notification mask
+*/
+
+typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event.
+
+
+/**
+\brief I2C Driver Capabilities.
+*/
+typedef struct _ARM_I2C_CAPABILITIES {
+  uint32_t address_10_bit : 1;          ///< supports 10-bit addressing
+  uint32_t reserved       : 31;         ///< Reserved (must be zero)
+} ARM_I2C_CAPABILITIES;
+
+
+/**
+\brief Access structure of the I2C Driver.
+*/
+typedef struct _ARM_DRIVER_I2C {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                                                                ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version.
+  ARM_I2C_CAPABILITIES (*GetCapabilities)(void);                                                                ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_I2C_SignalEvent_t cb_event);                                      ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface.
+  int32_t              (*Uninitialize)   (void);                                                                ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);                                               ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power.
+  int32_t              (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.
+  int32_t              (*MasterReceive)  (uint32_t addr,       uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.
+  int32_t              (*SlaveTransmit)  (               const uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.
+  int32_t              (*SlaveReceive)   (                     uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.
+  int32_t              (*GetDataCount)   (void);                                                                ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg);                                      ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface.
+  ARM_I2C_STATUS       (*GetStatus)      (void);                                                                ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status.
+} const ARM_DRIVER_I2C;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_I2C_H_ */

CMSIS-DAP/Driver/Include/Driver_MCI.h

@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      MCI (Memory Card Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_MCI_STATUS
+ *  Version 2.3
+ *    ARM_MCI_STATUS made volatile
+ *  Version 2.2
+ *    Added timeout and error flags to ARM_MCI_STATUS
+ *    Added support for controlling optional RST_n pin (eMMC)
+ *    Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)
+ *    Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT
+ *  Version 2.1
+ *    Decoupled SPI mode from MCI driver
+ *    Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP
+ *  Version 2.0
+ *    Added support for:
+ *      SD UHS-I (Ultra High Speed)
+ *      SD I/O Interrupt
+ *      Read Wait (SD I/O)
+ *      Suspend/Resume (SD I/O)
+ *      MMC Interrupt
+ *      MMC Boot
+ *      Stream Data transfer (MMC)
+ *      VCCQ Power Supply Control (eMMC)
+ *      Command Completion Signal (CCS) for CE-ATA
+ *    Added ARM_MCI_Control function
+ *    Added ARM_MCI_GetStatus function
+ *    Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions
+ *      (replaced by ARM_MCI_Control)
+ *    Changed ARM_MCI_CardPower function (voltage parameter)
+ *    Changed ARM_MCI_SendCommnad function (flags parameter)
+ *    Changed ARM_MCI_SetupTransfer function (mode parameter)
+ *    Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_MCI_H_
+#define DRIVER_MCI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_MCI_(n)      Driver_MCI##n
+#define  ARM_Driver_MCI_(n) _ARM_Driver_MCI_(n)
+
+
+/****** MCI Send Command Flags *****/
+#define ARM_MCI_RESPONSE_Pos             0
+#define ARM_MCI_RESPONSE_Msk            (3UL << ARM_MCI_RESPONSE_Pos)
+#define ARM_MCI_RESPONSE_NONE           (0UL << ARM_MCI_RESPONSE_Pos)   ///< No response expected (default)
+#define ARM_MCI_RESPONSE_SHORT          (1UL << ARM_MCI_RESPONSE_Pos)   ///< Short response (48-bit)
+#define ARM_MCI_RESPONSE_SHORT_BUSY     (2UL << ARM_MCI_RESPONSE_Pos)   ///< Short response with busy signal (48-bit)
+#define ARM_MCI_RESPONSE_LONG           (3UL << ARM_MCI_RESPONSE_Pos)   ///< Long response (136-bit)
+
+#define ARM_MCI_RESPONSE_INDEX          (1UL << 2)  ///< Check command index in response
+#define ARM_MCI_RESPONSE_CRC            (1UL << 3)  ///< Check CRC in response
+
+#define ARM_MCI_WAIT_BUSY               (1UL << 4)  ///< Wait until busy before sending the command
+
+#define ARM_MCI_TRANSFER_DATA           (1UL << 5)  ///< Activate Data transfer
+
+#define ARM_MCI_CARD_INITIALIZE         (1UL << 6)  ///< Execute Memory Card initialization sequence
+
+#define ARM_MCI_INTERRUPT_COMMAND       (1UL << 7)  ///< Send Interrupt command (CMD40 - MMC only)
+#define ARM_MCI_INTERRUPT_RESPONSE      (1UL << 8)  ///< Send Interrupt response (CMD40 - MMC only)
+
+#define ARM_MCI_BOOT_OPERATION          (1UL << 9)  ///< Execute Boot operation (MMC only)
+#define ARM_MCI_BOOT_ALTERNATIVE        (1UL << 10) ///< Execute Alternative Boot operation (MMC only)
+#define ARM_MCI_BOOT_ACK                (1UL << 11) ///< Expect Boot Acknowledge (MMC only)
+
+#define ARM_MCI_CCSD                    (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device
+#define ARM_MCI_CCS                     (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device
+
+
+/****** MCI Setup Transfer Mode *****/
+#define ARM_MCI_TRANSFER_READ           (0UL << 0)  ///< Data Read Transfer (from MCI)
+#define ARM_MCI_TRANSFER_WRITE          (1UL << 0)  ///< Data Write Transfer (to MCI)
+#define ARM_MCI_TRANSFER_BLOCK          (0UL << 1)  ///< Block Data transfer (default)
+#define ARM_MCI_TRANSFER_STREAM         (1UL << 1)  ///< Stream Data transfer (MMC only)
+
+
+/****** MCI Control Codes *****/
+#define ARM_MCI_BUS_SPEED               (0x01UL)    ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s
+#define ARM_MCI_BUS_SPEED_MODE          (0x02UL)    ///< Set Bus Speed Mode as specified with arg
+#define ARM_MCI_BUS_CMD_MODE            (0x03UL)    ///< Set CMD Line Mode as specified with arg
+#define ARM_MCI_BUS_DATA_WIDTH          (0x04UL)    ///< Set Bus Data Width as specified with arg
+#define ARM_MCI_DRIVER_STRENGTH         (0x05UL)    ///< Set SD UHS-I Driver Strength as specified with arg 
+#define ARM_MCI_CONTROL_RESET           (0x06UL)    ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active 
+#define ARM_MCI_CONTROL_CLOCK_IDLE      (0x07UL)    ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled
+#define ARM_MCI_UHS_TUNING_OPERATION    (0x08UL)    ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute
+#define ARM_MCI_UHS_TUNING_RESULT       (0x09UL)    ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error
+#define ARM_MCI_DATA_TIMEOUT            (0x0AUL)    ///< Set Data timeout; arg = timeout in bus cycles
+#define ARM_MCI_CSS_TIMEOUT             (0x0BUL)    ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles
+#define ARM_MCI_MONITOR_SDIO_INTERRUPT  (0x0CUL)    ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled
+#define ARM_MCI_CONTROL_READ_WAIT       (0x0DUL)    ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled
+#define ARM_MCI_SUSPEND_TRANSFER        (0x0EUL)    ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer
+#define ARM_MCI_RESUME_TRANSFER         (0x0FUL)    ///< Resume Data transfer (SD I/O)
+
+/*----- MCI Bus Speed Mode -----*/
+#define ARM_MCI_BUS_DEFAULT_SPEED       (0x00UL)    ///< SD/MMC: Default Speed mode up to 25/26MHz
+#define ARM_MCI_BUS_HIGH_SPEED          (0x01UL)    ///< SD/MMC: High    Speed mode up to 50/52MHz
+#define ARM_MCI_BUS_UHS_SDR12           (0x02UL)    ///< SD: SDR12  (Single Data Rate) up to  25MHz,  12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR25           (0x03UL)    ///< SD: SDR25  (Single Data Rate) up to  50MHz,  25  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR50           (0x04UL)    ///< SD: SDR50  (Single Data Rate) up to 100MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR104          (0x05UL)    ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_DDR50           (0x06UL)    ///< SD: DDR50  (Dual Data Rate)   up to  50MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+
+/*----- MCI CMD Line Mode -----*/
+#define ARM_MCI_BUS_CMD_PUSH_PULL       (0x00UL)    ///< Push-Pull CMD line (default)
+#define ARM_MCI_BUS_CMD_OPEN_DRAIN      (0x01UL)    ///< Open Drain CMD line (MMC only)
+
+/*----- MCI Bus Data Width -----*/
+#define ARM_MCI_BUS_DATA_WIDTH_1        (0x00UL)    ///< Bus data width: 1 bit (default)
+#define ARM_MCI_BUS_DATA_WIDTH_4        (0x01UL)    ///< Bus data width: 4 bits
+#define ARM_MCI_BUS_DATA_WIDTH_8        (0x02UL)    ///< Bus data width: 8 bits
+#define ARM_MCI_BUS_DATA_WIDTH_4_DDR    (0x03UL)    ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only
+#define ARM_MCI_BUS_DATA_WIDTH_8_DDR    (0x04UL)    ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only
+
+/*----- MCI Driver Strength -----*/
+#define ARM_MCI_DRIVER_TYPE_A           (0x01UL)    ///< SD UHS-I Driver Type A
+#define ARM_MCI_DRIVER_TYPE_B           (0x00UL)    ///< SD UHS-I Driver Type B (default)
+#define ARM_MCI_DRIVER_TYPE_C           (0x02UL)    ///< SD UHS-I Driver Type C
+#define ARM_MCI_DRIVER_TYPE_D           (0x03UL)    ///< SD UHS-I Driver Type D
+
+
+/****** MCI Card Power *****/
+#define ARM_MCI_POWER_VDD_Pos            0
+#define ARM_MCI_POWER_VDD_Msk           (0x0FUL << ARM_MCI_POWER_VDD_Pos)
+#define ARM_MCI_POWER_VDD_OFF           (0x01UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) turned off
+#define ARM_MCI_POWER_VDD_3V3           (0x02UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 3.3V
+#define ARM_MCI_POWER_VDD_1V8           (0x03UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 1.8V
+#define ARM_MCI_POWER_VCCQ_Pos           4
+#define ARM_MCI_POWER_VCCQ_Msk          (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
+#define ARM_MCI_POWER_VCCQ_OFF          (0x01UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ turned off
+#define ARM_MCI_POWER_VCCQ_3V3          (0x02UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 3.3V
+#define ARM_MCI_POWER_VCCQ_1V8          (0x03UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.8V
+#define ARM_MCI_POWER_VCCQ_1V2          (0x04UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.2V
+
+
+/**
+\brief MCI Status
+*/
+typedef struct _ARM_MCI_STATUS {
+  uint32_t command_active   : 1;        ///< Command active flag
+  uint32_t command_timeout  : 1;        ///< Command timeout flag (cleared on start of next command)
+  uint32_t command_error    : 1;        ///< Command error flag (cleared on start of next command)
+  uint32_t transfer_active  : 1;        ///< Transfer active flag
+  uint32_t transfer_timeout : 1;        ///< Transfer timeout flag (cleared on start of next command)
+  uint32_t transfer_error   : 1;        ///< Transfer error flag (cleared on start of next command)
+  uint32_t sdio_interrupt   : 1;        ///< SD I/O Interrupt flag (cleared on start of monitoring)
+  uint32_t ccs              : 1;        ///< CCS flag (cleared on start of next command)
+  uint32_t reserved         : 24;
+} ARM_MCI_STATUS;
+
+
+/****** MCI Card Event *****/
+#define ARM_MCI_EVENT_CARD_INSERTED     (1UL << 0)  ///< Memory Card inserted
+#define ARM_MCI_EVENT_CARD_REMOVED      (1UL << 1)  ///< Memory Card removed
+#define ARM_MCI_EVENT_COMMAND_COMPLETE  (1UL << 2)  ///< Command completed
+#define ARM_MCI_EVENT_COMMAND_TIMEOUT   (1UL << 3)  ///< Command timeout
+#define ARM_MCI_EVENT_COMMAND_ERROR     (1UL << 4)  ///< Command response error (CRC error or invalid response)
+#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5)  ///< Data transfer completed
+#define ARM_MCI_EVENT_TRANSFER_TIMEOUT  (1UL << 6)  ///< Data transfer timeout
+#define ARM_MCI_EVENT_TRANSFER_ERROR    (1UL << 7)  ///< Data transfer CRC failed
+#define ARM_MCI_EVENT_SDIO_INTERRUPT    (1UL << 8)  ///< SD I/O Interrupt
+#define ARM_MCI_EVENT_CCS               (1UL << 9)  ///< Command Completion Signal (CCS)
+#define ARM_MCI_EVENT_CCS_TIMEOUT       (1UL << 10) ///< Command Completion Signal (CCS) Timeout
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_MCI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)
+  \brief         Initialize the Memory Card Interface
+  \param[in]     cb_event  Pointer to \ref ARM_MCI_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Uninitialize (void)
+  \brief         De-initialize Memory Card Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control Memory Card Interface Power.
+  \param[in]     state   Power state \ref ARM_POWER_STATE
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_CardPower (uint32_t voltage)
+  \brief         Set Memory Card Power supply voltage.
+  \param[in]     voltage  Memory Card Power supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadCD (void)
+  \brief         Read Card Detect (CD) state.
+  \return        1:card detected, 0:card not detected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadWP (void)
+  \brief         Read Write Protect (WP) state.
+  \return        1:write protected, 0:not write protected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_SendCommand (uint32_t  cmd,
+                                              uint32_t  arg,
+                                              uint32_t  flags,
+                                              uint32_t *response)
+  \brief         Send Command to card and get the response.
+  \param[in]     cmd       Memory Card command
+  \param[in]     arg       Command argument
+  \param[in]     flags     Command flags
+  \param[out]    response  Pointer to buffer for response
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_SetupTransfer (uint8_t *data,
+                                                uint32_t block_count,
+                                                uint32_t block_size,
+                                                uint32_t mode)
+  \brief         Setup read or write transfer operation.
+  \param[in,out] data         Pointer to data block(s) to be written or read
+  \param[in]     block_count  Number of blocks
+  \param[in]     block_size   Size of a block in bytes
+  \param[in]     mode         Transfer mode
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_AbortTransfer (void)
+  \brief         Abort current read/write data transfer.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)
+  \brief         Control MCI Interface.
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation (optional)
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_MCI_STATUS ARM_MCI_GetStatus (void)
+  \brief         Get MCI status.
+  \return        MCI status \ref ARM_MCI_STATUS
+*/
+
+/**
+  \fn            void ARM_MCI_SignalEvent (uint32_t event)
+  \brief         Callback function that signals a MCI Card Event.
+  \param[in]     event \ref mci_event_gr
+  \return        none
+*/
+
+typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event.
+
+
+/**
+\brief  MCI Driver Capabilities.
+*/
+typedef struct _ARM_MCI_CAPABILITIES {
+  uint32_t cd_state          : 1;       ///< Card Detect State available
+  uint32_t cd_event          : 1;       ///< Signal Card Detect change event
+  uint32_t wp_state          : 1;       ///< Write Protect State available
+  uint32_t vdd               : 1;       ///< Supports VDD Card Power Supply Control
+  uint32_t vdd_1v8           : 1;       ///< Supports 1.8 VDD Card Power Supply
+  uint32_t vccq              : 1;       ///< Supports VCCQ Card Power Supply Control (eMMC)
+  uint32_t vccq_1v8          : 1;       ///< Supports 1.8 VCCQ Card Power Supply (eMMC)
+  uint32_t vccq_1v2          : 1;       ///< Supports 1.2 VCCQ Card Power Supply (eMMC)
+  uint32_t data_width_4      : 1;       ///< Supports 4-bit data
+  uint32_t data_width_8      : 1;       ///< Supports 8-bit data
+  uint32_t data_width_4_ddr  : 1;       ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t data_width_8_ddr  : 1;       ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t high_speed        : 1;       ///< Supports SD/MMC High Speed Mode
+  uint32_t uhs_signaling     : 1;       ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling 
+  uint32_t uhs_tuning        : 1;       ///< Supports SD UHS-I tuning 
+  uint32_t uhs_sdr50         : 1;       ///< Supports SD UHS-I SDR50  (Single Data Rate) up to  50MB/s
+  uint32_t uhs_sdr104        : 1;       ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s
+  uint32_t uhs_ddr50         : 1;       ///< Supports SD UHS-I DDR50  (Dual   Data Rate) up to  50MB/s
+  uint32_t uhs_driver_type_a : 1;       ///< Supports SD UHS-I Driver Type A
+  uint32_t uhs_driver_type_c : 1;       ///< Supports SD UHS-I Driver Type C
+  uint32_t uhs_driver_type_d : 1;       ///< Supports SD UHS-I Driver Type D 
+  uint32_t sdio_interrupt    : 1;       ///< Supports SD I/O Interrupt 
+  uint32_t read_wait         : 1;       ///< Supports Read Wait (SD I/O)
+  uint32_t suspend_resume    : 1;       ///< Supports Suspend/Resume (SD I/O)
+  uint32_t mmc_interrupt     : 1;       ///< Supports MMC Interrupt 
+  uint32_t mmc_boot          : 1;       ///< Supports MMC Boot 
+  uint32_t rst_n             : 1;       ///< Supports RST_n Pin Control (eMMC)
+  uint32_t ccs               : 1;       ///< Supports Command Completion Signal (CCS) for CE-ATA
+  uint32_t ccs_timeout       : 1;       ///< Supports Command Completion Signal (CCS) timeout for CE-ATA
+  uint32_t reserved          : 3;       ///< Reserved (must be zero)
+} ARM_MCI_CAPABILITIES;
+
+
+/**
+\brief  Access structure of the MCI Driver.
+*/
+typedef struct _ARM_DRIVER_MCI {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                           ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version.
+  ARM_MCI_CAPABILITIES (*GetCapabilities)(void);                           ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface.
+  int32_t              (*Uninitialize)   (void);                           ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);          ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power.
+  int32_t              (*CardPower)      (uint32_t voltage);               ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage.
+  int32_t              (*ReadCD)         (void);                           ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state.
+  int32_t              (*ReadWP)         (void);                           ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state.
+  int32_t              (*SendCommand)    (uint32_t cmd, 
+                                          uint32_t arg, 
+                                          uint32_t flags,
+                                          uint32_t *response);             ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response.
+  int32_t              (*SetupTransfer)  (uint8_t *data,
+                                          uint32_t block_count,
+                                          uint32_t block_size,
+                                          uint32_t mode);                  ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation.
+  int32_t              (*AbortTransfer)  (void);                           ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface.
+  ARM_MCI_STATUS       (*GetStatus)      (void);                           ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status.
+} const ARM_DRIVER_MCI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_MCI_H_ */

CMSIS-DAP/Driver/Include/Driver_NAND.h

@@ -0,0 +1,426 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      NAND Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_NAND_STATUS
+ *  Version 2.3
+ *    Extended ARM_NAND_ECC_INFO structure
+ *  Version 2.2
+ *    ARM_NAND_STATUS made volatile
+ *  Version 2.1
+ *    Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (command agnostic)
+ *    Added support for:
+ *      NV-DDR & NV-DDR2 Interface (ONFI specification)
+ *      VCC, VCCQ and VPP Power Supply Control
+ *      WP (Write Protect) Control
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_NAND_H_
+#define DRIVER_NAND_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_NAND_(n)      Driver_NAND##n
+#define  ARM_Driver_NAND_(n) _ARM_Driver_NAND_(n)
+
+
+/****** NAND Device Power *****/
+#define ARM_NAND_POWER_VCC_Pos           0
+#define ARM_NAND_POWER_VCC_Msk          (0x07UL << ARM_NAND_POWER_VCC_Pos)
+#define ARM_NAND_POWER_VCC_OFF          (0x01UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC Power off
+#define ARM_NAND_POWER_VCC_3V3          (0x02UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 3.3V
+#define ARM_NAND_POWER_VCC_1V8          (0x03UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 1.8V
+#define ARM_NAND_POWER_VCCQ_Pos          3
+#define ARM_NAND_POWER_VCCQ_Msk         (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
+#define ARM_NAND_POWER_VCCQ_OFF         (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
+#define ARM_NAND_POWER_VCCQ_3V3         (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
+#define ARM_NAND_POWER_VCCQ_1V8         (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
+#define ARM_NAND_POWER_VPP_OFF          (1UL << 6)                          ///< VPP off
+#define ARM_NAND_POWER_VPP_ON           (1UL << 7)                          ///< VPP on
+
+
+/****** NAND Control Codes *****/
+#define ARM_NAND_BUS_MODE               (0x01UL)    ///< Set Bus Mode as specified with arg
+#define ARM_NAND_BUS_DATA_WIDTH         (0x02UL)    ///< Set Bus Data Width as specified with arg
+#define ARM_NAND_DRIVER_STRENGTH        (0x03UL)    ///< Set Driver Strength as specified with arg
+#define ARM_NAND_DEVICE_READY_EVENT     (0x04UL)    ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled 
+#define ARM_NAND_DRIVER_READY_EVENT     (0x05UL)    ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled 
+
+/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_BUS_INTERFACE_Pos       4
+#define ARM_NAND_BUS_INTERFACE_Msk      (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
+#define ARM_NAND_BUS_SDR                (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface:    SDR  (Single Data Rate) - Traditional interface (default)
+#define ARM_NAND_BUS_DDR                (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR  (Double Data Rate)
+#define ARM_NAND_BUS_DDR2               (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR2 (Double Data Rate)
+#define ARM_NAND_BUS_TIMING_MODE_Pos     0
+#define ARM_NAND_BUS_TIMING_MODE_Msk    (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
+#define ARM_NAND_BUS_TIMING_MODE_0      (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 0 (default)
+#define ARM_NAND_BUS_TIMING_MODE_1      (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 1
+#define ARM_NAND_BUS_TIMING_MODE_2      (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 2
+#define ARM_NAND_BUS_TIMING_MODE_3      (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 3
+#define ARM_NAND_BUS_TIMING_MODE_4      (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 4 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_5      (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 5 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_6      (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 6 (NV-DDR2 only)
+#define ARM_NAND_BUS_TIMING_MODE_7      (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 7 (NV-DDR2 only)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos    8
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DO_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DO_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos    12
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DI_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DI_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_VEN           (1UL << 16)                               ///< DDR2 Enable external VREFQ as reference
+#define ARM_NAND_BUS_DDR2_CMPD          (1UL << 17)                               ///< DDR2 Enable complementary DQS (DQS_c) signal
+#define ARM_NAND_BUS_DDR2_CMPR          (1UL << 18)                               ///< DDR2 Enable complementary RE_n (RE_c) signal
+
+/*----- NAND Data Bus Width -----*/
+#define ARM_NAND_BUS_DATA_WIDTH_8       (0x00UL)   ///< Bus Data Width:  8 bit (default)
+#define ARM_NAND_BUS_DATA_WIDTH_16      (0x01UL)   ///< Bus Data Width: 16 bit
+
+/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_DRIVER_STRENGTH_18     (0x00UL)   ///< Driver Strength 2.0x = 18 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_25     (0x01UL)   ///< Driver Strength 1.4x = 25 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_35     (0x02UL)   ///< Driver Strength 1.0x = 35 Ohms (default)
+#define ARM_NAND_DRIVER_STRENGTH_50     (0x03UL)   ///< Driver Strength 0.7x = 50 Ohms
+
+
+/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_ECC_INDEX_Pos           0
+#define ARM_NAND_ECC_INDEX_Msk          (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
+#define ARM_NAND_ECC(n)                 ((n) & ARM_NAND_ECC_INDEX_Msk)     ///< Select ECC
+#define ARM_NAND_ECC0                   (1UL << 8)                         ///< Use ECC0 of selected ECC
+#define ARM_NAND_ECC1                   (1UL << 9)                         ///< Use ECC1 of selected ECC
+
+/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_DRIVER_DONE_EVENT      (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
+
+/****** NAND Sequence Execution Code *****/
+#define ARM_NAND_CODE_SEND_CMD1         (1UL << 17) ///< Send Command 1
+#define ARM_NAND_CODE_SEND_ADDR_COL1    (1UL << 18) ///< Send Column Address 1
+#define ARM_NAND_CODE_SEND_ADDR_COL2    (1UL << 19) ///< Send Column Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW1    (1UL << 20) ///< Send Row Address 1
+#define ARM_NAND_CODE_SEND_ADDR_ROW2    (1UL << 21) ///< Send Row Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW3    (1UL << 22) ///< Send Row Address 3
+#define ARM_NAND_CODE_INC_ADDR_ROW      (1UL << 23) ///< Auto-increment Row Address
+#define ARM_NAND_CODE_WRITE_DATA        (1UL << 24) ///< Write Data
+#define ARM_NAND_CODE_SEND_CMD2         (1UL << 25) ///< Send Command 2
+#define ARM_NAND_CODE_WAIT_BUSY         (1UL << 26) ///< Wait while R/Bn busy
+#define ARM_NAND_CODE_READ_DATA         (1UL << 27) ///< Read Data
+#define ARM_NAND_CODE_SEND_CMD3         (1UL << 28) ///< Send Command 3
+#define ARM_NAND_CODE_READ_STATUS       (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
+
+/*----- NAND Sequence Execution Code: Command -----*/
+#define ARM_NAND_CODE_CMD1_Pos           0
+#define ARM_NAND_CODE_CMD1_Msk          (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
+#define ARM_NAND_CODE_CMD2_Pos           8
+#define ARM_NAND_CODE_CMD2_Msk          (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
+#define ARM_NAND_CODE_CMD3_Pos           16
+#define ARM_NAND_CODE_CMD3_Msk          (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
+
+/*----- NAND Sequence Execution Code: Column Address -----*/
+#define ARM_NAND_CODE_ADDR_COL1_Pos      0
+#define ARM_NAND_CODE_ADDR_COL1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
+#define ARM_NAND_CODE_ADDR_COL2_Pos      8
+#define ARM_NAND_CODE_ADDR_COL2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
+
+/*----- NAND Sequence Execution Code: Row Address -----*/
+#define ARM_NAND_CODE_ADDR_ROW1_Pos      0
+#define ARM_NAND_CODE_ADDR_ROW1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
+#define ARM_NAND_CODE_ADDR_ROW2_Pos      8
+#define ARM_NAND_CODE_ADDR_ROW2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
+#define ARM_NAND_CODE_ADDR_ROW3_Pos      16
+#define ARM_NAND_CODE_ADDR_ROW3_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
+
+
+/****** NAND specific error codes *****/
+#define ARM_NAND_ERROR_ECC              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< ECC generation/correction failed
+
+
+/**
+\brief NAND ECC (Error Correction Code) Information
+*/
+typedef struct _ARM_NAND_ECC_INFO {
+  uint32_t type             :  2;       ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare
+  uint32_t page_layout      :  1;       ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|
+  uint32_t page_count       :  3;       ///< Number of virtual pages: N = 2 ^ page_count
+  uint32_t page_size        :  4;       ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description)
+  uint32_t reserved         : 14;       ///< Reserved (must be zero)
+  uint32_t correctable_bits :  8;       ///< Number of correctable bits (based on 512 byte codeword size)
+  uint16_t codeword_size     [2];       ///< Number of bytes over which ECC is calculated
+  uint16_t ecc_size          [2];       ///< ECC size in bytes (rounded up)
+  uint16_t ecc_offset        [2];       ///< ECC offset in bytes (where ECC starts in Spare)
+  /* Extended description */
+  uint16_t virtual_page_size [2];       ///< Virtual Page size in bytes (Main/Spare)
+  uint16_t codeword_offset   [2];       ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare)
+  uint16_t codeword_gap      [2];       ///< Codeword gap in bytes till next protected data
+  uint16_t ecc_gap           [2];       ///< ECC gap in bytes till next generated ECC
+} ARM_NAND_ECC_INFO;
+
+
+/**
+\brief NAND Status
+*/
+typedef struct _ARM_NAND_STATUS {
+  uint32_t busy      : 1;               ///< Driver busy flag
+  uint32_t ecc_error : 1;               ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
+  uint32_t reserved  : 30;
+} ARM_NAND_STATUS;
+
+
+/****** NAND Event *****/
+#define ARM_NAND_EVENT_DEVICE_READY     (1UL << 0)  ///< Device Ready: R/Bn rising edge
+#define ARM_NAND_EVENT_DRIVER_READY     (1UL << 1)  ///< Driver Ready
+#define ARM_NAND_EVENT_DRIVER_DONE      (1UL << 2)  ///< Driver operation done
+#define ARM_NAND_EVENT_ECC_ERROR        (1UL << 3)  ///< ECC could not correct data
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_NAND_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
+  \brief         Initialize the NAND Interface.
+  \param[in]     cb_event  Pointer to \ref ARM_NAND_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Uninitialize (void)
+  \brief         De-initialize the NAND Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
+  \brief         Control the NAND interface power.
+  \param[in]     state  Power state
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_DevicePower (uint32_t voltage)
+  \brief         Set device power supply voltage.
+  \param[in]     voltage  NAND Device supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
+  \brief         Control WPn (Write Protect).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Write Protect off
+                - \b true  Write Protect on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
+  \brief         Control CEn (Chip Enable).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Chip Enable off
+                - \b true  Chip Enable on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
+  \brief         Get Device Busy pin state.
+  \param[in]     dev_num  Device number
+  \return        1=busy, 0=not busy, or error
+*/
+/**
+  \fn            int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
+  \brief         Send command to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     cmd      Command
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
+  \brief         Send address to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     addr     Address
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
+  \brief         Read data from NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer for data to read from NAND device
+  \param[in]     cnt      Number of data items to read
+  \param[in]     mode     Operation mode
+  \return        number of data items read or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
+  \brief         Write data to NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer with data to write to NAND device
+  \param[in]     cnt      Number of data items to write
+  \param[in]     mode     Operation mode
+  \return        number of data items written or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                                   uint32_t addr_col, uint32_t addr_row,
+                                                   void *data, uint32_t data_cnt,
+                                                   uint8_t *status, uint32_t *count)
+  \brief         Execute sequence of operations.
+  \param[in]     dev_num  Device number
+  \param[in]     code     Sequence code
+  \param[in]     cmd      Command(s)
+  \param[in]     addr_col Column address
+  \param[in]     addr_row Row address
+  \param[in,out] data     Pointer to data to be written or read 
+  \param[in]     data_cnt Number of data items in one iteration
+  \param[out]    status   Pointer to status read
+  \param[in,out] count    Number of iterations
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
+  \brief         Abort sequence execution.
+  \param[in]     dev_num  Device number
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
+  \brief         Control NAND Interface.
+  \param[in]     dev_num  Device number
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
+  \brief         Get NAND status.
+  \param[in]     dev_num  Device number
+  \return        NAND status \ref ARM_NAND_STATUS
+*/
+/**
+  \fn            int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
+  \brief         Inquire about available ECC.
+  \param[in]     index   Inquire ECC index
+  \param[out]    info    Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
+  \return        \ref execution_status
+*/
+
+/**
+  \fn            void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
+  \brief         Signal NAND event.
+  \param[in]     dev_num  Device number
+  \param[in]     event    Event notification mask
+  \return        none
+*/
+
+typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event);    ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
+
+
+/**
+\brief NAND Driver Capabilities.
+*/
+typedef struct _ARM_NAND_CAPABILITIES {
+  uint32_t event_device_ready  : 1;     ///< Signal Device Ready event (R/Bn rising edge)
+  uint32_t reentrant_operation : 1;     ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
+  uint32_t sequence_operation  : 1;     ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
+  uint32_t vcc                 : 1;     ///< Supports VCC Power Supply Control
+  uint32_t vcc_1v8             : 1;     ///< Supports 1.8 VCC Power Supply
+  uint32_t vccq                : 1;     ///< Supports VCCQ I/O Power Supply Control
+  uint32_t vccq_1v8            : 1;     ///< Supports 1.8 VCCQ I/O Power Supply
+  uint32_t vpp                 : 1;     ///< Supports VPP High Voltage Power Supply Control
+  uint32_t wp                  : 1;     ///< Supports WPn (Write Protect) Control
+  uint32_t ce_lines            : 4;     ///< Number of CEn (Chip Enable) lines: ce_lines + 1
+  uint32_t ce_manual           : 1;     ///< Supports manual CEn (Chip Enable) Control
+  uint32_t rb_monitor          : 1;     ///< Supports R/Bn (Ready/Busy) Monitoring
+  uint32_t data_width_16       : 1;     ///< Supports 16-bit data
+  uint32_t ddr                 : 1;     ///< Supports NV-DDR  Data Interface (ONFI)
+  uint32_t ddr2                : 1;     ///< Supports NV-DDR2 Data Interface (ONFI)
+  uint32_t sdr_timing_mode     : 3;     ///< Fastest (highest) SDR     Timing Mode supported (ONFI)
+  uint32_t ddr_timing_mode     : 3;     ///< Fastest (highest) NV_DDR  Timing Mode supported (ONFI)
+  uint32_t ddr2_timing_mode    : 3;     ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
+  uint32_t driver_strength_18  : 1;     ///< Supports Driver Strength 2.0x = 18 Ohms
+  uint32_t driver_strength_25  : 1;     ///< Supports Driver Strength 1.4x = 25 Ohms
+  uint32_t driver_strength_50  : 1;     ///< Supports Driver Strength 0.7x = 50 Ohms
+  uint32_t reserved            : 2;     ///< Reserved (must be zero)
+} ARM_NAND_CAPABILITIES;
+
+
+/**
+\brief Access structure of the NAND Driver.
+*/
+typedef struct _ARM_DRIVER_NAND {
+  ARM_DRIVER_VERSION    (*GetVersion)     (void);                                                             ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
+  ARM_NAND_CAPABILITIES (*GetCapabilities)(void);                                                             ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)     (ARM_NAND_SignalEvent_t cb_event);                                  ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
+  int32_t               (*Uninitialize)   (void);                                                             ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
+  int32_t               (*PowerControl)   (ARM_POWER_STATE state);                                            ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
+  int32_t               (*DevicePower)    (uint32_t voltage);                                                 ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
+  int32_t               (*WriteProtect)   (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
+  int32_t               (*ChipEnable)     (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
+  int32_t               (*GetDeviceBusy)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
+  int32_t               (*SendCommand)    (uint32_t dev_num, uint8_t cmd);                                    ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
+  int32_t               (*SendAddress)    (uint32_t dev_num, uint8_t addr);                                   ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
+  int32_t               (*ReadData)       (uint32_t dev_num,       void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
+  int32_t               (*WriteData)      (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
+  int32_t               (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                           uint32_t addr_col, uint32_t addr_row,
+                                           void *data, uint32_t data_cnt,
+                                           uint8_t *status, uint32_t *count);                                 ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
+  int32_t               (*AbortSequence)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. 
+  int32_t               (*Control)        (uint32_t dev_num, uint32_t control, uint32_t arg);                 ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
+  ARM_NAND_STATUS       (*GetStatus)      (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
+  int32_t               (*InquireECC)     ( int32_t index, ARM_NAND_ECC_INFO *info);                          ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. 
+} const ARM_DRIVER_NAND;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_NAND_H_ */

CMSIS-DAP/Driver/Include/Driver_SAI.h

@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V1.2
+ *
+ * Project:      SAI (Serial Audio Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 1.2
+ *    Removed volatile from ARM_SAI_STATUS
+ *  Version 1.1
+ *    ARM_SAI_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_SAI_H_
+#define DRIVER_SAI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */
+
+
+#define _ARM_Driver_SAI_(n)      Driver_SAI##n
+#define  ARM_Driver_SAI_(n) _ARM_Driver_SAI_(n)
+
+
+/****** SAI Control Codes *****/
+
+#define ARM_SAI_CONTROL_Msk             (0xFFUL)
+#define ARM_SAI_CONFIGURE_TX            (0x01UL)    ///< Configure Transmitter;  arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONFIGURE_RX            (0x02UL)    ///< Configure Receiver;     arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONTROL_TX              (0x03UL)    ///< Control Transmitter;    arg1.0: 0=disable (default), 1=enable; arg1.1: mute
+#define ARM_SAI_CONTROL_RX              (0x04UL)    ///< Control Receiver;       arg1.0: 0=disable (default), 1=enable
+#define ARM_SAI_MASK_SLOTS_TX           (0x05UL)    ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_MASK_SLOTS_RX           (0x06UL)    ///< Mask Receiver    slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_ABORT_SEND              (0x07UL)    ///< Abort \ref ARM_SAI_Send
+#define ARM_SAI_ABORT_RECEIVE           (0x08UL)    ///< Abort \ref ARM_SAI_Receive
+
+/*----- SAI Control Codes: Configuration Parameters: Mode -----*/
+#define ARM_SAI_MODE_Pos                 8
+#define ARM_SAI_MODE_Msk                (1UL << ARM_SAI_MODE_Pos)
+#define ARM_SAI_MODE_MASTER             (1UL << ARM_SAI_MODE_Pos)               ///< Master Mode
+#define ARM_SAI_MODE_SLAVE              (0UL << ARM_SAI_MODE_Pos)               ///< Slave Mode (default)
+
+/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/
+#define ARM_SAI_SYNCHRONIZATION_Pos      9
+#define ARM_SAI_SYNCHRONIZATION_Msk     (1UL << ARM_SAI_SYNCHRONIZATION_Pos)
+#define ARM_SAI_ASYNCHRONOUS            (0UL << ARM_SAI_SYNCHRONIZATION_Pos)    ///< Asynchronous (default)
+#define ARM_SAI_SYNCHRONOUS             (1UL << ARM_SAI_SYNCHRONIZATION_Pos)    ///< Synchronous
+
+/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/
+#define ARM_SAI_PROTOCOL_Pos             10
+#define ARM_SAI_PROTOCOL_Msk            (7UL << ARM_SAI_PROTOCOL_Pos)
+#define ARM_SAI_PROTOCOL_USER           (0UL << ARM_SAI_PROTOCOL_Pos)           ///< User defined (default) 
+#define ARM_SAI_PROTOCOL_I2S            (1UL << ARM_SAI_PROTOCOL_Pos)           ///< I2S
+#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED  (2UL << ARM_SAI_PROTOCOL_Pos)           ///< MSB (left) justified 
+#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED  (3UL << ARM_SAI_PROTOCOL_Pos)           ///< LSB (right) justified
+#define ARM_SAI_PROTOCOL_PCM_SHORT      (4UL << ARM_SAI_PROTOCOL_Pos)           ///< PCM with short frame
+#define ARM_SAI_PROTOCOL_PCM_LONG       (5UL << ARM_SAI_PROTOCOL_Pos)           ///< PCM with long frame
+#define ARM_SAI_PROTOCOL_AC97           (6UL << ARM_SAI_PROTOCOL_Pos)           ///< AC'97
+
+/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/
+#define ARM_SAI_DATA_SIZE_Pos            13
+#define ARM_SAI_DATA_SIZE_Msk                      (0x1FUL  << ARM_SAI_DATA_SIZE_Pos)
+#define ARM_SAI_DATA_SIZE(n)            ((((n)-1UL)&0x1FUL) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32)
+
+/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/
+#define ARM_SAI_BIT_ORDER_Pos            18
+#define ARM_SAI_BIT_ORDER_Msk           (1UL << ARM_SAI_BIT_ORDER_Pos)
+#define ARM_SAI_MSB_FIRST               (0UL << ARM_SAI_BIT_ORDER_Pos)          ///< Data is transferred with MSB first (default)
+#define ARM_SAI_LSB_FIRST               (1UL << ARM_SAI_BIT_ORDER_Pos)          ///< Data is transferred with LSB first; User Protocol only (ignored otherwise)
+
+/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/
+#define ARM_SAI_MONO_MODE               (1UL << 19)                             ///< Mono Mode (only for I2S, MSB/LSB justified)
+
+/*----- SAI Control Codes:Configuration Parameters: Companding -----*/
+#define ARM_SAI_COMPANDING_Pos           20
+#define ARM_SAI_COMPANDING_Msk          (3UL << ARM_SAI_COMPANDING_Pos)
+#define ARM_SAI_COMPANDING_NONE         (0UL << ARM_SAI_COMPANDING_Pos)         ///< No companding (default)
+#define ARM_SAI_COMPANDING_A_LAW        (2UL << ARM_SAI_COMPANDING_Pos)         ///< A-Law companding
+#define ARM_SAI_COMPANDING_U_LAW        (3UL << ARM_SAI_COMPANDING_Pos)         ///< u-Law companding
+
+/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/
+#define ARM_SAI_CLOCK_POLARITY_Pos       23
+#define ARM_SAI_CLOCK_POLARITY_Msk      (1UL << ARM_SAI_CLOCK_POLARITY_Pos)
+#define ARM_SAI_CLOCK_POLARITY_0        (0UL << ARM_SAI_CLOCK_POLARITY_Pos)     ///< Drive on falling edge, Capture on rising  edge (default)
+#define ARM_SAI_CLOCK_POLARITY_1        (1UL << ARM_SAI_CLOCK_POLARITY_Pos)     ///< Drive on rising  edge, Capture on falling edge
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/
+#define ARM_SAI_MCLK_PIN_Pos             24
+#define ARM_SAI_MCLK_PIN_Msk            (3UL << ARM_SAI_MCLK_PIN_Pos)
+#define ARM_SAI_MCLK_PIN_INACTIVE       (0UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK not used (default)
+#define ARM_SAI_MCLK_PIN_OUTPUT         (1UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK is output (Master only)
+#define ARM_SAI_MCLK_PIN_INPUT          (2UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK is input  (Master only)
+
+
+/****** SAI Configuration (arg1) *****/
+
+/*----- SAI Configuration (arg1): Frame Length -----*/
+#define ARM_SAI_FRAME_LENGTH_Pos          0
+#define ARM_SAI_FRAME_LENGTH_Msk                    (0x3FFUL  << ARM_SAI_FRAME_LENGTH_Pos)
+#define ARM_SAI_FRAME_LENGTH(n)          ((((n)-1UL)&0x3FFUL) << ARM_SAI_FRAME_LENGTH_Pos)  ///< Frame length in bits (8..1024); default depends on protocol and data
+
+/*----- SAI Configuration (arg1): Frame Sync Width -----*/
+#define ARM_SAI_FRAME_SYNC_WIDTH_Pos      10
+#define ARM_SAI_FRAME_SYNC_WIDTH_Msk                (0xFFUL  << ARM_SAI_FRAME_SYNC_WIDTH_Pos)
+#define ARM_SAI_FRAME_SYNC_WIDTH(n)      ((((n)-1UL)&0xFFUL) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/
+#define ARM_SAI_FRAME_SYNC_POLARITY_Pos   18
+#define ARM_SAI_FRAME_SYNC_POLARITY_Msk  (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)
+#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)           ///< Frame Sync is active high (default); User Protocol only (ignored otherwise)
+#define ARM_SAI_FRAME_SYNC_POLARITY_LOW  (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)           ///< Frame Sync is active low; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Early -----*/
+#define ARM_SAI_FRAME_SYNC_EARLY         (1UL << 19)                                        ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Count -----*/
+#define ARM_SAI_SLOT_COUNT_Pos            20
+#define ARM_SAI_SLOT_COUNT_Msk                      (0x1FUL  << ARM_SAI_SLOT_COUNT_Pos)
+#define ARM_SAI_SLOT_COUNT(n)            ((((n)-1UL)&0x1FUL) << ARM_SAI_SLOT_COUNT_Pos)     ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Size -----*/
+#define ARM_SAI_SLOT_SIZE_Pos             25
+#define ARM_SAI_SLOT_SIZE_Msk            (3UL << ARM_SAI_SLOT_SIZE_Pos)
+#define ARM_SAI_SLOT_SIZE_DEFAULT        (0UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size is equal to data size (default)
+#define ARM_SAI_SLOT_SIZE_16             (1UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size = 16 bits; User Protocol only (ignored otherwise)
+#define ARM_SAI_SLOT_SIZE_32             (3UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size = 32 bits; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Offset -----*/
+#define ARM_SAI_SLOT_OFFSET_Pos           27
+#define ARM_SAI_SLOT_OFFSET_Msk               (0x1FUL  << ARM_SAI_SLOT_OFFSET_Pos)
+#define ARM_SAI_SLOT_OFFSET(n)           (((n)&0x1FUL) << ARM_SAI_SLOT_OFFSET_Pos)          ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise)
+
+/****** SAI Configuration (arg2) *****/
+
+/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/
+#define ARM_SAI_AUDIO_FREQ_Msk          (0x0FFFFFUL)                                        ///< Audio frequency mask
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/
+#define ARM_SAI_MCLK_PRESCALER_Pos       20
+#define ARM_SAI_MCLK_PRESCALER_Msk      (0xFFFUL << ARM_SAI_MCLK_PRESCALER_Pos)
+#define ARM_SAI_MCLK_PRESCALER(n)       ((((n)-1UL)&0xFFFUL) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1)
+
+
+/****** SAI specific error codes *****/
+#define ARM_SAI_ERROR_SYNCHRONIZATION       (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Synchronization not supported
+#define ARM_SAI_ERROR_PROTOCOL              (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Protocol not supported
+#define ARM_SAI_ERROR_DATA_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified Data size not supported
+#define ARM_SAI_ERROR_BIT_ORDER             (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SAI_ERROR_MONO_MODE             (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Mono mode not supported
+#define ARM_SAI_ERROR_COMPANDING            (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Companding not supported
+#define ARM_SAI_ERROR_CLOCK_POLARITY        (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock polarity not supported
+#define ARM_SAI_ERROR_AUDIO_FREQ            (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Audio frequency not supported
+#define ARM_SAI_ERROR_MCLK_PIN              (ARM_DRIVER_ERROR_SPECIFIC - 9)     ///< Specified MCLK Pin setting not supported
+#define ARM_SAI_ERROR_MCLK_PRESCALER        (ARM_DRIVER_ERROR_SPECIFIC - 10)    ///< Specified MCLK Prescaler not supported
+#define ARM_SAI_ERROR_FRAME_LENGTH          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported
+#define ARM_SAI_ERROR_FRAME_LENGHT          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported @deprecated use \ref ARM_SAI_ERROR_FRAME_LENGTH instead
+#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH      (ARM_DRIVER_ERROR_SPECIFIC - 12)    ///< Specified Frame Sync width not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY   (ARM_DRIVER_ERROR_SPECIFIC - 13)    ///< Specified Frame Sync polarity not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_EARLY      (ARM_DRIVER_ERROR_SPECIFIC - 14)    ///< Specified Frame Sync early not supported
+#define ARM_SAI_ERROR_SLOT_COUNT            (ARM_DRIVER_ERROR_SPECIFIC - 15)    ///< Specified Slot count not supported
+#define ARM_SAI_ERROR_SLOT_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 16)    ///< Specified Slot size not supported
+#define ARM_SAI_ERROR_SLOT_OFFESET          (ARM_DRIVER_ERROR_SPECIFIC - 17)    ///< Specified Slot offset not supported
+
+
+/**
+\brief SAI Status
+*/
+typedef struct _ARM_SAI_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t frame_error      : 1;        ///< Sync Frame error detected (cleared on start of next send/receive operation)
+  uint32_t reserved         : 27;
+} ARM_SAI_STATUS;
+
+
+/****** SAI Event *****/
+#define ARM_SAI_EVENT_SEND_COMPLETE     (1UL << 0)  ///< Send completed
+#define ARM_SAI_EVENT_RECEIVE_COMPLETE  (1UL << 1)  ///< Receive completed
+#define ARM_SAI_EVENT_TX_UNDERFLOW      (1UL << 2)  ///< Transmit data not available
+#define ARM_SAI_EVENT_RX_OVERFLOW       (1UL << 3)  ///< Receive data overflow
+#define ARM_SAI_EVENT_FRAME_ERROR       (1UL << 4)  ///< Sync Frame error in Slave mode (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SAI_CAPABILITIES
+
+  \fn          int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
+  \brief       Initialize SAI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SAI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Uninitialize (void)
+  \brief       De-initialize SAI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SAI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SAI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SAI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SAI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SAI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SAI_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_SAI_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
+  \brief       Control SAI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg1     Argument 1 of operation (optional)
+  \param[in]   arg2     Argument 2 of operation (optional)
+  \return      common \ref execution_status and driver specific \ref sai_execution_status
+
+  \fn          ARM_SAI_STATUS ARM_SAI_GetStatus (void)
+  \brief       Get SAI status.
+  \return      SAI status \ref ARM_SAI_STATUS
+
+  \fn          void ARM_SAI_SignalEvent (uint32_t event)
+  \brief       Signal SAI Events.
+  \param[in]   event \ref SAI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event.
+
+
+/**
+\brief SAI Driver Capabilities.
+*/
+typedef struct _ARM_SAI_CAPABILITIES {
+  uint32_t asynchronous          : 1;   ///< supports asynchronous Transmit/Receive
+  uint32_t synchronous           : 1;   ///< supports synchronous Transmit/Receive
+  uint32_t protocol_user         : 1;   ///< supports user defined Protocol
+  uint32_t protocol_i2s          : 1;   ///< supports I2S Protocol
+  uint32_t protocol_justified    : 1;   ///< supports MSB/LSB justified Protocol
+  uint32_t protocol_pcm          : 1;   ///< supports PCM short/long frame Protocol
+  uint32_t protocol_ac97         : 1;   ///< supports AC'97 Protocol
+  uint32_t mono_mode             : 1;   ///< supports Mono mode
+  uint32_t companding            : 1;   ///< supports Companding
+  uint32_t mclk_pin              : 1;   ///< supports MCLK (Master Clock) pin
+  uint32_t event_frame_error     : 1;   ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
+  uint32_t reserved              : 21;  ///< Reserved (must be zero)
+} ARM_SAI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SAI Driver.
+*/
+typedef struct _ARM_DRIVER_SAI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                                            ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version.
+  ARM_SAI_CAPABILITIES (*GetCapabilities) (void);                                            ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SAI_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface.
+  int32_t              (*Uninitialize)    (void);                                            ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);                           ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface.
+  uint32_t             (*GetTxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count.
+  uint32_t             (*GetRxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg1, uint32_t arg2);  ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface.
+  ARM_SAI_STATUS       (*GetStatus)       (void);                                            ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status.
+} const ARM_DRIVER_SAI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SAI_H_ */

CMSIS-DAP/Driver/Include/Driver_SPI.h

@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.3
+ *
+ * Project:      SPI (Serial Peripheral Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Removed Simplex Mode (deprecated)
+ *    Removed volatile from ARM_SPI_STATUS
+ *  Version 2.2
+ *    ARM_SPI_STATUS made volatile
+ *  Version 2.1
+ *    Renamed status flag "tx_rx_busy" to "busy"
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *      Half-duplex Modes
+ *      Configurable number of data bits
+ *      Support for TI Mode and Microwire
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added "send_done_event" to Capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_SPI_H_
+#define DRIVER_SPI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_SPI_(n)      Driver_SPI##n
+#define  ARM_Driver_SPI_(n) _ARM_Driver_SPI_(n)
+
+
+/****** SPI Control Codes *****/
+
+#define ARM_SPI_CONTROL_Pos              0
+#define ARM_SPI_CONTROL_Msk             (0xFFUL << ARM_SPI_CONTROL_Pos)
+
+/*----- SPI Control Codes: Mode -----*/
+#define ARM_SPI_MODE_INACTIVE           (0x00UL << ARM_SPI_CONTROL_Pos)     ///< SPI Inactive
+#define ARM_SPI_MODE_MASTER             (0x01UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE              (0x02UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output on MISO, Input on MOSI)
+#define ARM_SPI_MODE_MASTER_SIMPLEX     (0x03UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps @deprecated Simplex Mode has been removed
+#define ARM_SPI_MODE_SLAVE_SIMPLEX      (0x04UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output/Input on MISO) @deprecated Simplex Mode has been removed
+
+/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
+#define ARM_SPI_FRAME_FORMAT_Pos         8
+#define ARM_SPI_FRAME_FORMAT_Msk        (7UL << ARM_SPI_FRAME_FORMAT_Pos)
+#define ARM_SPI_CPOL0_CPHA0             (0UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 0 (default)
+#define ARM_SPI_CPOL0_CPHA1             (1UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 1
+#define ARM_SPI_CPOL1_CPHA0             (2UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 0
+#define ARM_SPI_CPOL1_CPHA1             (3UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 1
+#define ARM_SPI_TI_SSI                  (4UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Texas Instruments Frame Format
+#define ARM_SPI_MICROWIRE               (5UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< National Semiconductor Microwire Frame Format
+
+/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_SPI_DATA_BITS_Pos            12
+#define ARM_SPI_DATA_BITS_Msk           (0x3FUL << ARM_SPI_DATA_BITS_Pos)
+#define ARM_SPI_DATA_BITS(n)            (((n) & 0x3FUL) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits
+
+/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
+#define ARM_SPI_BIT_ORDER_Pos            18
+#define ARM_SPI_BIT_ORDER_Msk           (1UL << ARM_SPI_BIT_ORDER_Pos)
+#define ARM_SPI_MSB_LSB                 (0UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from MSB to LSB (default)
+#define ARM_SPI_LSB_MSB                 (1UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from LSB to MSB
+
+/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
+#define ARM_SPI_SS_MASTER_MODE_Pos       19
+#define ARM_SPI_SS_MASTER_MODE_Msk      (3UL << ARM_SPI_SS_MASTER_MODE_Pos)
+#define ARM_SPI_SS_MASTER_UNUSED        (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)
+#define ARM_SPI_SS_MASTER_SW            (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled
+#define ARM_SPI_SS_MASTER_HW_OUTPUT     (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output
+#define ARM_SPI_SS_MASTER_HW_INPUT      (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input
+#define ARM_SPI_SS_SLAVE_MODE_Pos        21
+#define ARM_SPI_SS_SLAVE_MODE_Msk       (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)
+#define ARM_SPI_SS_SLAVE_HW             (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Hardware monitored (default)
+#define ARM_SPI_SS_SLAVE_SW             (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Software controlled
+
+
+/*----- SPI Control Codes: Miscellaneous Controls  -----*/
+#define ARM_SPI_SET_BUS_SPEED           (0x10UL << ARM_SPI_CONTROL_Pos)     ///< Set Bus Speed in bps; arg = value
+#define ARM_SPI_GET_BUS_SPEED           (0x11UL << ARM_SPI_CONTROL_Pos)     ///< Get Bus Speed in bps
+#define ARM_SPI_SET_DEFAULT_TX_VALUE    (0x12UL << ARM_SPI_CONTROL_Pos)     ///< Set default Transmit value; arg = value
+#define ARM_SPI_CONTROL_SS              (0x13UL << ARM_SPI_CONTROL_Pos)     ///< Control Slave Select; arg: 0=inactive, 1=active 
+#define ARM_SPI_ABORT_TRANSFER          (0x14UL << ARM_SPI_CONTROL_Pos)     ///< Abort current data transfer
+
+
+/****** SPI Slave Select Signal definitions *****/
+#define ARM_SPI_SS_INACTIVE              0UL                                ///< SPI Slave Select Signal Inactive
+#define ARM_SPI_SS_ACTIVE                1UL                                ///< SPI Slave Select Signal Active
+
+
+/****** SPI specific error codes *****/
+#define ARM_SPI_ERROR_MODE              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_SPI_ERROR_FRAME_FORMAT      (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Frame Format not supported
+#define ARM_SPI_ERROR_DATA_BITS         (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_SPI_ERROR_BIT_ORDER         (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SPI_ERROR_SS_MODE           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Slave Select Mode not supported
+
+
+/**
+\brief SPI Status
+*/
+typedef struct _ARM_SPI_STATUS {
+  uint32_t busy       : 1;              ///< Transmitter/Receiver busy flag
+  uint32_t data_lost  : 1;              ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
+  uint32_t mode_fault : 1;              ///< Mode fault detected; optional (cleared on start of transfer operation)
+  uint32_t reserved   : 29;
+} ARM_SPI_STATUS;
+
+
+/****** SPI Event *****/
+#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0)  ///< Data Transfer completed
+#define ARM_SPI_EVENT_DATA_LOST         (1UL << 1)  ///< Data lost: Receive overflow / Transmit underflow
+#define ARM_SPI_EVENT_MODE_FAULT        (1UL << 2)  ///< Master Mode Fault (SS deactivated when Master)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SPI_CAPABILITIES
+
+  \fn          int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)
+  \brief       Initialize SPI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SPI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Uninitialize (void)
+  \brief       De-initialize SPI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SPI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SPI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SPI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SPI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Transfer (const void *data_out,
+                                               void *data_in,
+                                         uint32_t    num)
+  \brief       Start sending/receiving data to/from SPI transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to SPI transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SPI_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data items transferred
+
+  \fn          int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)
+  \brief       Control SPI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref spi_execution_status
+
+  \fn          ARM_SPI_STATUS ARM_SPI_GetStatus (void)
+  \brief       Get SPI status.
+  \return      SPI status \ref ARM_SPI_STATUS
+
+  \fn          void ARM_SPI_SignalEvent (uint32_t event)
+  \brief       Signal SPI Events.
+  \param[in]   event \ref SPI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event.
+
+
+/**
+\brief SPI Driver Capabilities.
+*/
+typedef struct _ARM_SPI_CAPABILITIES {
+  uint32_t simplex          : 1;        ///< supports Simplex Mode (Master and Slave) @deprecated Reserved (must be zero)
+  uint32_t ti_ssi           : 1;        ///< supports TI Synchronous Serial Interface
+  uint32_t microwire        : 1;        ///< supports Microwire Interface
+  uint32_t event_mode_fault : 1;        ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
+  uint32_t reserved         : 28;       ///< Reserved (must be zero)
+} ARM_SPI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SPI Driver.
+*/
+typedef struct _ARM_DRIVER_SPI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                             ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version.
+  ARM_SPI_CAPABILITIES (*GetCapabilities) (void);                             ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SPI_SignalEvent_t cb_event);   ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface.
+  int32_t              (*Uninitialize)    (void);                             ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);            ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface.
+  int32_t              (*Transfer)        (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num);                  ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.
+  uint32_t             (*GetDataCount)    (void);                             ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg);   ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface.
+  ARM_SPI_STATUS       (*GetStatus)       (void);                             ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status.
+} const ARM_DRIVER_SPI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SPI_H_ */

CMSIS-DAP/Driver/Include/Driver_Storage.h

@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V1.2
+ *
+ * Project:      Storage Driver definitions
+ */
+
+/* History:
+ *  Version 1.2
+ *    Removed volatile from ARM_STORAGE_STATUS
+ *  Version 1.1
+ *    ARM_STORAGE_STATUS made volatile
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_STORAGE_H_
+#define DRIVER_STORAGE_H_
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */
+
+
+#define _ARM_Driver_Storage_(n)      Driver_Storage##n
+#define  ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
+
+#define ARM_STORAGE_INVALID_OFFSET  (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
+                                                            ///  address space). A storage block may never start at this address.
+
+#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL)          ///< Invalid address within the processor's memory address space.
+                                                            ///  Refer to memory-mapped storage, i.e. \ref ARM_DRIVER_STORAGE::ResolveAddress().
+
+/****** Storage specific error codes *****/
+#define ARM_STORAGE_ERROR_NOT_ERASABLE      (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
+#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE  (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
+#define ARM_STORAGE_ERROR_PROTECTED         (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
+
+/**
+ * \brief Attributes of the storage range within a storage block.
+ */
+typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
+  uint32_t erasable      :  1;   ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
+                                 ///   @note if 'erasable' is 0 (i.e. the 'erase' operation isn't available) then
+                                 ///   'erase_unit' (see below) is immaterial and should be 0.
+  uint32_t programmable  :  1;   ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
+                                 ///    Writes are typically achieved through the ProgramData operation (following an erase);
+                                 ///    if storage isn't erasable (see 'erasable' above) but is memory-mapped
+                                 ///    (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
+  uint32_t executable    :  1;   ///< This storage block can hold program data; the processor can fetch and execute code
+                                 ///    sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
+  uint32_t protectable   :  1;   ///< The entire block can be protected from program and erase operations. Once protection
+                                 ///    is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
+  uint32_t reserved      : 28;
+  uint32_t erase_unit;           ///< Minimum erase size in bytes.
+                                 ///    The offset of the start of the erase-range should also be aligned with this value.
+                                 ///    Applicable if the 'erasable' attribute is set for the block.
+                                 ///    @note if 'erasable' (see above) is 0 (i.e. the 'erase' operation isn't available) then
+                                 ///    'erase_unit' is immaterial and should be 0.
+  uint32_t protection_unit;      ///< Minimum protectable size in bytes. Applicable if the 'protectable'
+                                 ///    attribute is set for the block. This should be a divisor of the block's size. A
+                                 ///    block can be considered to be made up of consecutive, individually-protectable fragments.
+} ARM_STORAGE_BLOCK_ATTRIBUTES;
+
+/**
+ * \brief A storage block is a range of memory with uniform attributes.
+ */
+typedef struct _ARM_STORAGE_BLOCK {
+  uint64_t                     addr;       ///< This is the start address of the storage block. It is
+                                           ///    expressed as an offset from the start of the storage map
+                                           ///    maintained by the owning storage controller.
+  uint64_t                     size;       ///< This is the size of the storage block, in units of bytes.
+                                           ///    Together with addr, it describes a range [addr, addr+size).
+  ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
+} ARM_STORAGE_BLOCK;
+
+/**
+ * The check for a valid ARM_STORAGE_BLOCK.
+ */
+#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
+
+/**
+ * \brief Values for encoding storage memory-types with respect to programmability.
+ *
+ * Please ensure that the maximum of the following memory types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
+ */
+#define ARM_STORAGE_PROGRAMMABILITY_RAM       (0U)
+#define ARM_STORAGE_PROGRAMMABILITY_ROM       (1U)  ///< Read-only memory.
+#define ARM_STORAGE_PROGRAMMABILITY_WORM      (2U)  ///< write-once-read-only-memory (WORM).
+#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE  (3U)  ///< re-programmable based on erase. Supports multiple writes.
+
+/**
+ * Values for encoding data-retention levels for storage blocks.
+ *
+ * Please ensure that the maximum of the following retention types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
+ */
+#define ARM_RETENTION_WHILE_DEVICE_ACTIVE     (0U)  ///< Data is retained only during device activity.
+#define ARM_RETENTION_ACROSS_SLEEP            (1U)  ///< Data is retained across processor sleep.
+#define ARM_RETENTION_ACROSS_DEEP_SLEEP       (2U)  ///< Data is retained across processor deep-sleep.
+#define ARM_RETENTION_BATTERY_BACKED          (3U)  ///< Data is battery-backed. Device can be powered off.
+#define ARM_RETENTION_NVM                     (4U)  ///< Data is retained in non-volatile memory.
+
+/**
+ * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
+ */
+typedef struct _ARM_STORAGE_SECURITY_FEATURES {
+  uint32_t acls                :  1; ///< Protection against internal software attacks using ACLs.
+  uint32_t rollback_protection :  1; ///< Roll-back protection. Set to true if the creator of the storage
+                                     ///    can ensure that an external attacker can't force an
+                                     ///    older firmware to run or to revert back to a previous state.
+  uint32_t tamper_proof        :  1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
+  uint32_t internal_flash      :  1; ///< Internal flash.
+  uint32_t reserved1           : 12;
+
+  /**
+   * Encode support for hardening against various classes of attacks.
+   */
+  uint32_t software_attacks     :  1; ///< device software (malware running on the device).
+  uint32_t board_level_attacks  :  1; ///< board level attacks (debug probes, copy protection fuses.)
+  uint32_t chip_level_attacks   :  1; ///< chip level attacks (tamper-protection).
+  uint32_t side_channel_attacks :  1; ///< side channel attacks.
+  uint32_t reserved2            : 12;
+} ARM_STORAGE_SECURITY_FEATURES;
+
+#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
+
+/**
+ * Device level metadata regarding the Storage implementation.
+ */
+typedef struct _ARM_STORAGE_INFO {
+  uint64_t                      total_storage;        ///< Total available storage, in bytes.
+  uint32_t                      program_unit;         ///< Minimum programming size in bytes.
+                                                      ///    The offset of the start of the program-range should also be aligned with this value.
+                                                      ///    Applicable only if the 'programmable' attribute is set for a block.
+                                                      ///    @note setting program_unit to 0 has the effect of disabling the size and alignment
+                                                      ///    restrictions (setting it to 1 also has the same effect).
+  uint32_t                      optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
+                                                      ///    have internal buffers into which to receive data. Writing in chunks of
+                                                      ///    'optimal_program_unit' would achieve maximum programming speed.
+                                                      ///    Applicable only if the 'programmable' attribute is set for the underlying block(s).
+  uint32_t                      program_cycles;       ///< A measure of endurance for reprogramming.
+                                                      ///    Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
+  uint32_t                      erased_value    :  1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
+  uint32_t                      memory_mapped   :  1; ///< This storage device has a mapping onto the processor's memory address space.
+                                                      ///    @note For a memory-mapped block which isn't erasable but is programmable (i.e. if
+                                                      ///    'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
+                                                      ///    the memory-mapped storage without going through the ProgramData operation.
+  uint32_t                      programmability :  4; ///< A value to indicate storage programmability.
+  uint32_t                      retention_level :  4;
+  uint32_t                      reserved        : 22;
+  ARM_STORAGE_SECURITY_FEATURES security;             ///< \ref ARM_STORAGE_SECURITY_FEATURES
+} ARM_STORAGE_INFO;
+
+/**
+\brief Operating status of the storage controller.
+*/
+typedef struct _ARM_STORAGE_STATUS {
+  uint32_t busy     : 1;                ///< Controller busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_STORAGE_STATUS;
+
+/**
+ * \brief Storage Driver API Capabilities.
+ */
+typedef struct _ARM_STORAGE_CAPABILITIES {
+  uint32_t asynchronous_ops :  1; ///< Used to indicate if APIs like initialize,
+                                  ///    read, erase, program, etc. can operate in asynchronous mode.
+                                  ///    Setting this bit to 1 means that the driver is capable
+                                  ///    of launching asynchronous operations; command completion is
+                                  ///    signaled by the invocation of a completion callback. If
+                                  ///    set to 1, drivers may still complete asynchronous
+                                  ///    operations synchronously as necessary (in which case they
+                                  ///    return a positive error code to indicate synchronous completion).
+  uint32_t erase_all        :  1; ///< Supports EraseAll operation.
+  uint32_t reserved         : 30; ///< Reserved (must be zero)
+} ARM_STORAGE_CAPABILITIES;
+
+/**
+ * Command opcodes for Storage.
+ */
+typedef enum _ARM_STORAGE_OPERATION {
+  ARM_STORAGE_OPERATION_GET_VERSION,
+  ARM_STORAGE_OPERATION_GET_CAPABILITIES,
+  ARM_STORAGE_OPERATION_INITIALIZE,
+  ARM_STORAGE_OPERATION_UNINITIALIZE,
+  ARM_STORAGE_OPERATION_POWER_CONTROL,
+  ARM_STORAGE_OPERATION_READ_DATA,
+  ARM_STORAGE_OPERATION_PROGRAM_DATA,
+  ARM_STORAGE_OPERATION_ERASE,
+  ARM_STORAGE_OPERATION_ERASE_ALL,
+  ARM_STORAGE_OPERATION_GET_STATUS,
+  ARM_STORAGE_OPERATION_GET_INFO,
+  ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
+  ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
+  ARM_STORAGE_OPERATION_GET_BLOCK
+} ARM_STORAGE_OPERATION;
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_STORAGE_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)
+  \brief       Initialize the Storage interface.
+  \param [in]  callback Pointer to \ref ARM_Storage_Callback_t.
+               Caller-defined callback to be invoked upon command completion
+               for asynchronous APIs (including the completion of
+               initialization). Use a NULL pointer when no callback
+               signals are required.
+  \return      If asynchronous activity is launched, invocation
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_Uninitialize (void)
+  \brief       De-initialize the Storage Interface.
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Storage interface power.
+  \param[in]   state  Power state
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)
+  \brief       Read data from Storage.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Storage.
+  \param[in]   size  Number of bytes to read. The data buffer
+               should be at least as large as this size.
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with the number of successfully transferred bytes passed in as
+               the 'status' parameter. In the case of synchronous execution, control
+               returns after completion with a positive transfer-count. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)
+  \brief       Program data to Storage.
+  \param [in] addr This is the start address of the range to be written into. It
+               needs to be aligned to the device's \em program_unit
+               specified in \ref ARM_STORAGE_INFO.
+  \param [in] data The source of the write operation. The buffer is owned by the
+               caller and should remain accessible for the lifetime of this
+               command.
+  \param [in] size The number of bytes requested to be written. The buffer
+               should be at least as large as this size. \note 'size' should
+               be a multiple of the device's 'program_unit' (see \ref
+               ARM_STORAGE_INFO).
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with the number of successfully transferred bytes passed in as
+               the 'status' parameter. In the case of synchronous execution, control
+               returns after completion with a positive transfer-count. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)
+  \brief       Erase Storage range.
+  \param [in]  addr This is the start-address of the range to be erased. It must
+               start at an 'erase_unit' boundary of the underlying block.
+  \param [in]  size Size (in bytes) of the range to be erased. 'addr + size'
+               must be aligned with the 'erase_unit' of the underlying
+               block.
+  \return      If the range to be erased doesn't align with the erase_units of the
+               respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is
+               returned. If any part of the range is protected,
+               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the range
+               is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
+               such sanity-check failures result in the error code being
+               returned synchronously and the storage bytes within the range
+               remain unaffected. Otherwise the function executes in the
+               following ways: If asynchronous activity is launched, an
+               invocation returns ARM_DRIVER_OK, and the caller can expect to
+               receive a callback in the future with the number of successfully
+               erased bytes passed in as the 'status' parameter. In the case of
+               synchronous execution, control returns after completion with a
+               positive erase-count. Return values less than ARM_DRIVER_OK (0)
+               signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_EraseAll (void)
+  \brief       Erase complete Storage.
+  \return      If any part of the storage range is protected,
+               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the
+               storage range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is
+               returned. All such sanity-check failures result in the error code
+               being returned synchronously and the storage bytes within the
+               range remain unaffected. Otherwise the function executes in the
+               following ways: If asynchronous activity is launched, an
+               invocation returns ARM_DRIVER_OK, and the caller can expect to
+               receive a callback in the future with ARM_DRIVER_OK passed in as
+               the 'status' parameter. In the case of synchronous execution,
+               control returns after completion with a value of 1. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)
+  \brief       Get Storage status.
+  \return      Storage status \ref ARM_STORAGE_STATUS
+*/
+/**
+  \fn          int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)
+  \brief       Get Storage information.
+  \param[out]  info  A caller-supplied buffer capable of being filled in with an \ref ARM_STORAGE_INFO.
+  \return      ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
+               metadata about the storage controller is filled into the supplied
+               buffer, else an appropriate error value.
+*/
+/**
+  \fn          uint32_t ARM_Storage_ResolveAddress(uint64_t addr)
+  \brief       Resolve an address relative to the storage controller into a memory address.
+  \param[in]   addr The address for which we want a resolution to the processor's physical address space. It is an offset from the
+               start of the storage map maintained by the owning storage
+               controller.
+  \return      The resolved address in the processor's address space, else ARM_STORAGE_INVALID_ADDRESS.
+*/
+/**
+  \fn          int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
+  \brief       Advance to the successor of the current block (iterator).
+  \param[in]   prev_block An existing block (iterator) within the same storage
+               controller. The memory buffer holding this block is owned
+               by the caller. This pointer may be NULL; if so, the
+               invocation fills in the first block into the out parameter:
+               'next_block'.
+  \param[out]  next_block A caller-owned buffer large enough to be filled in with
+               the following ARM_STORAGE_BLOCK. It is legal to provide the
+               same buffer using 'next_block' as was passed in with 'prev_block'. It
+               is also legal to pass a NULL into this parameter if the
+               caller isn't interested in populating a buffer with the next
+               block, i.e. if the caller only wishes to establish the
+               presence of a next block.
+  \return      ARM_DRIVER_OK if a valid next block is found (or first block, if
+               prev_block is passed as NULL); upon successful operation, the contents
+               of the next (or first) block are filled into the buffer pointed to by
+               the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
+               guaranteed to be true. Upon reaching the end of the sequence of blocks
+               (iterators), or in case the driver is unable to fetch information about
+               the next (or first) block, an error (negative) value is returned and an
+               invalid StorageBlock is populated into the supplied buffer. If
+               prev_block is NULL, the first block is returned.
+*/
+/**
+  \fn          int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block);
+  \brief       Find the storage block (iterator) encompassing a given storage address.
+  \param[in]   addr Storage address in bytes.
+  \param[out]  block A caller-owned buffer large enough to be filled in with the
+               ARM_STORAGE_BLOCK encapsulating the given address. This value
+               can also be passed in as NULL if the caller isn't interested
+               in populating a buffer with the block, if the caller only
+               wishes to establish the presence of a containing storage
+               block.
+  \return      ARM_DRIVER_OK if a containing storage-block is found. In this case,
+               if block is non-NULL, the buffer pointed to by it is populated with
+               the contents of the storage block, i.e. if block is valid and a block is
+               found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
+               call. If there is no storage block containing the given offset, or in
+               case the driver is unable to resolve an address to a storage-block, an
+               error (negative) value is returned and an invalid StorageBlock is
+               populated into the supplied buffer.
+*/
+
+/**
+ * Provides the typedef for the callback function \ref ARM_Storage_Callback_t.
+ */
+typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
+
+/**
+ * The set of operations constituting the Storage driver.
+ */
+typedef struct _ARM_DRIVER_STORAGE {
+  ARM_DRIVER_VERSION       (*GetVersion)     (void);                                           ///< Pointer to \ref ARM_Storage_GetVersion : Get driver version.
+  ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);                                           ///< Pointer to \ref ARM_Storage_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)     (ARM_Storage_Callback_t callback);                ///< Pointer to \ref ARM_Storage_Initialize : Initialize the Storage Interface.
+  int32_t                  (*Uninitialize)   (void);                                           ///< Pointer to \ref ARM_Storage_Uninitialize : De-initialize the Storage Interface.
+  int32_t                  (*PowerControl)   (ARM_POWER_STATE state);                          ///< Pointer to \ref ARM_Storage_PowerControl : Control the Storage interface power.
+  int32_t                  (*ReadData)       (uint64_t addr, void *data, uint32_t size);       ///< Pointer to \ref ARM_Storage_ReadData : Read data from Storage.
+  int32_t                  (*ProgramData)    (uint64_t addr, const void *data, uint32_t size); ///< Pointer to \ref ARM_Storage_ProgramData : Program data to Storage.
+  int32_t                  (*Erase)          (uint64_t addr, uint32_t size);                   ///< Pointer to \ref ARM_Storage_Erase : Erase Storage range.
+  int32_t                  (*EraseAll)       (void);                                           ///< Pointer to \ref ARM_Storage_EraseAll : Erase complete Storage.
+  ARM_STORAGE_STATUS       (*GetStatus)      (void);                                           ///< Pointer to \ref ARM_Storage_GetStatus : Get Storage status.
+  int32_t                  (*GetInfo)        (ARM_STORAGE_INFO *info);                         ///< Pointer to \ref ARM_Storage_GetInfo : Get Storage information.
+  uint32_t                 (*ResolveAddress) (uint64_t addr);                                  ///< Pointer to \ref ARM_Storage_ResolveAddress : Resolve a storage address.
+  int32_t                  (*GetNextBlock)   (const ARM_STORAGE_BLOCK* prev, ARM_STORAGE_BLOCK *next); ///< Pointer to \ref ARM_Storage_GetNextBlock : fetch successor for current block.
+  int32_t                  (*GetBlock)       (uint64_t addr, ARM_STORAGE_BLOCK *block);        ///< Pointer to \ref ARM_Storage_GetBlock :
+} const ARM_DRIVER_STORAGE;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_STORAGE_H_ */

CMSIS-DAP/Driver/Include/Driver_USART.h

@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.4
+ *
+ * Project:      USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ *               Driver definitions
+ */
+
+/* History:
+ *  Version 2.4
+ *    Removed volatile from ARM_USART_STATUS and ARM_USART_MODEM_STATUS
+ *  Version 2.3
+ *    ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
+ *  Version 2.2
+ *    Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions 
+ *  Version 2.1
+ *    Removed optional argument parameter from Signal Event
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *      renamed driver UART -> USART (Asynchronous & Synchronous)
+ *    Added modes:
+ *      Synchronous
+ *      Single-wire
+ *      IrDA
+ *      Smart Card  
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added events:
+ *      ARM_UART_EVENT_TX_EMPTY,     ARM_UART_EVENT_RX_TIMEOUT
+ *      ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ *    Added functions: SetTxThreshold, SetRxThreshold
+ *    Added "rx_timeout_event" to capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USART_H_
+#define DRIVER_USART_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */
+
+
+#define _ARM_Driver_USART_(n)      Driver_USART##n
+#define  ARM_Driver_USART_(n) _ARM_Driver_USART_(n)
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos                0
+#define ARM_USART_CONTROL_Msk               (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS         (0x01UL << ARM_USART_CONTROL_Pos)   ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER   (0x02UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE    (0x03UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE          (0x04UL << ARM_USART_CONTROL_Pos)   ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA                 (0x05UL << ARM_USART_CONTROL_Pos)   ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD           (0x06UL << ARM_USART_CONTROL_Pos)   ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos              8
+#define ARM_USART_DATA_BITS_Msk             (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5               (5UL << ARM_USART_DATA_BITS_Pos)    ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6               (6UL << ARM_USART_DATA_BITS_Pos)    ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7               (7UL << ARM_USART_DATA_BITS_Pos)    ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8               (0UL << ARM_USART_DATA_BITS_Pos)    ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9               (1UL << ARM_USART_DATA_BITS_Pos)    ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos                 12
+#define ARM_USART_PARITY_Msk                (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE               (0UL << ARM_USART_PARITY_Pos)       ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN               (1UL << ARM_USART_PARITY_Pos)       ///< Even Parity
+#define ARM_USART_PARITY_ODD                (2UL << ARM_USART_PARITY_Pos)       ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos              14
+#define ARM_USART_STOP_BITS_Msk             (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1               (0UL << ARM_USART_STOP_BITS_Pos)    ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2               (1UL << ARM_USART_STOP_BITS_Pos)    ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5             (2UL << ARM_USART_STOP_BITS_Pos)    ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5             (3UL << ARM_USART_STOP_BITS_Pos)    ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos           16
+#define ARM_USART_FLOW_CONTROL_Msk          (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE         (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS          (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS          (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS      (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos                   18
+#define ARM_USART_CPOL_Msk                  (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0                     (0UL << ARM_USART_CPOL_Pos)         ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1                     (1UL << ARM_USART_CPOL_Pos)         ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos                   19
+#define ARM_USART_CPHA_Msk                  (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0                     (0UL << ARM_USART_CPHA_Pos)         ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1                     (1UL << ARM_USART_CPHA_Pos)         ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls  -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE      (0x10UL << ARM_USART_CONTROL_Pos)   ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE            (0x11UL << ARM_USART_CONTROL_Pos)   ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period  
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK      (0x13UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK   (0x14UL << ARM_USART_CONTROL_Pos)   ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX                (0x15UL << ARM_USART_CONTROL_Pos)   ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX                (0x16UL << ARM_USART_CONTROL_Pos)   ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK             (0x17UL << ARM_USART_CONTROL_Pos)   ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND                (0x18UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE             (0x19UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER            (0x1AUL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE                (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE            (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY              (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL        (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL                (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA                (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Clock Phase not supported
+
+
+/**
+\brief USART Status
+*/
+typedef struct _ARM_USART_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+  uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+  uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+  uint32_t reserved         : 25;
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+  ARM_USART_RTS_CLEAR,                  ///< Deactivate RTS
+  ARM_USART_RTS_SET,                    ///< Activate RTS
+  ARM_USART_DTR_CLEAR,                  ///< Deactivate DTR
+  ARM_USART_DTR_SET                     ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef struct _ARM_USART_MODEM_STATUS {
+  uint32_t cts      : 1;                ///< CTS state: 1=Active, 0=Inactive
+  uint32_t dsr      : 1;                ///< DSR state: 1=Active, 0=Inactive
+  uint32_t dcd      : 1;                ///< DCD state: 1=Active, 0=Inactive
+  uint32_t ri       : 1;                ///< RI  state: 1=Active, 0=Inactive
+  uint32_t reserved : 28;
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE       (1UL << 0)  ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE    (1UL << 1)  ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE   (1UL << 2)  ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE         (1UL << 3)  ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW        (1UL << 4)  ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW         (1UL << 5)  ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT          (1UL << 6)  ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK            (1UL << 7)  ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR    (1UL << 8)  ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR     (1UL << 9)  ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS                 (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR                 (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD                 (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI                  (1UL << 13) ///< RI  state changed (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+  \brief       Get driver capabilities
+  \return      \ref ARM_USART_CAPABILITIES
+
+  \fn          int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+  \brief       Initialize USART Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_USART_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Uninitialize (void)
+  \brief       De-initialize USART Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USART Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Send (const void *data, uint32_t num)
+  \brief       Start sending data to USART transmitter.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from USART receiver.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Transfer (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num)
+  \brief       Start sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_USART_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_USART_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+  \brief       Control USART Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref usart_execution_status
+
+  \fn          ARM_USART_STATUS ARM_USART_GetStatus (void)
+  \brief       Get USART status.
+  \return      USART status \ref ARM_USART_STATUS
+
+  \fn          int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+  \brief       Set USART Modem Control line state.
+  \param[in]   control  \ref ARM_USART_MODEM_CONTROL
+  \return      \ref execution_status 
+
+  \fn          ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+  \brief       Get USART Modem Status lines state.
+  \return      modem status \ref ARM_USART_MODEM_STATUS
+
+  \fn          void ARM_USART_SignalEvent (uint32_t event)
+  \brief       Signal USART Events.
+  \param[in]   event  \ref USART_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+  uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode 
+  uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+  uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+  uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+  uint32_t irda               : 1;      ///< supports UART IrDA mode
+  uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+  uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+  uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+  uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+  uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+  uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+  uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+  uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+  uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+  uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+  uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+  uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+  uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+  uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+  uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+  uint32_t event_ri           : 1;      ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+  uint32_t reserved           : 11;     ///< Reserved (must be zero)
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+  ARM_DRIVER_VERSION     (*GetVersion)      (void);                              ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+  ARM_USART_CAPABILITIES (*GetCapabilities) (void);                              ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)      (ARM_USART_SignalEvent_t cb_event);  ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+  int32_t                (*Uninitialize)    (void);                              ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+  int32_t                (*PowerControl)    (ARM_POWER_STATE state);             ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+  int32_t                (*Send)            (const void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+  int32_t                (*Receive)         (      void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+  int32_t                (*Transfer)        (const void *data_out,
+                                                   void *data_in,
+                                             uint32_t    num);                   ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+  uint32_t               (*GetTxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+  uint32_t               (*GetRxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+  int32_t                (*Control)         (uint32_t control, uint32_t arg);    ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+  ARM_USART_STATUS       (*GetStatus)       (void);                              ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+  int32_t                (*SetModemControl) (ARM_USART_MODEM_CONTROL control);   ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+  ARM_USART_MODEM_STATUS (*GetModemStatus)  (void);                              ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USART_H_ */

CMSIS-DAP/Driver/Include/Driver_USB.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V2.0
+ *
+ * Project:      USB Driver common definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added PID Types
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USB_H_
+#define DRIVER_USB_H_
+
+#include "Driver_Common.h"
+
+/* USB Role */
+#define ARM_USB_ROLE_NONE               (0U)
+#define ARM_USB_ROLE_HOST               (1U)
+#define ARM_USB_ROLE_DEVICE             (2U)
+
+/* USB Pins */
+#define ARM_USB_PIN_DP                  (1U << 0) ///< USB D+ pin
+#define ARM_USB_PIN_DM                  (1U << 1) ///< USB D- pin
+#define ARM_USB_PIN_VBUS                (1U << 2) ///< USB VBUS pin
+#define ARM_USB_PIN_OC                  (1U << 3) ///< USB OverCurrent pin
+#define ARM_USB_PIN_ID                  (1U << 4) ///< USB ID pin
+
+/* USB Speed */
+#define ARM_USB_SPEED_LOW               (0U)      ///< Low-speed USB
+#define ARM_USB_SPEED_FULL              (1U)      ///< Full-speed USB
+#define ARM_USB_SPEED_HIGH              (2U)      ///< High-speed USB
+
+/* USB PID Types */
+#define ARM_USB_PID_OUT                 (1U)
+#define ARM_USB_PID_IN                  (9U)
+#define ARM_USB_PID_SOF                 (5U)
+#define ARM_USB_PID_SETUP               (13U)
+#define ARM_USB_PID_DATA0               (3U)
+#define ARM_USB_PID_DATA1               (11U)
+#define ARM_USB_PID_DATA2               (7U)
+#define ARM_USB_PID_MDATA               (15U)
+#define ARM_USB_PID_ACK                 (2U)
+#define ARM_USB_PID_NAK                 (10U)
+#define ARM_USB_PID_STALL               (14U)
+#define ARM_USB_PID_NYET                (6U)
+#define ARM_USB_PID_PRE                 (12U)
+#define ARM_USB_PID_ERR                 (12U)
+#define ARM_USB_PID_SPLIT               (8U)
+#define ARM_USB_PID_PING                (4U)
+#define ARM_USB_PID_RESERVED            (0U)
+
+/* USB Endpoint Address (bEndpointAddress) */
+#define ARM_USB_ENDPOINT_NUMBER_MASK    (0x0FU)
+#define ARM_USB_ENDPOINT_DIRECTION_MASK (0x80U)
+
+/* USB Endpoint Type */
+#define ARM_USB_ENDPOINT_CONTROL        (0U)     ///< Control Endpoint
+#define ARM_USB_ENDPOINT_ISOCHRONOUS    (1U)     ///< Isochronous Endpoint
+#define ARM_USB_ENDPOINT_BULK           (2U)     ///< Bulk Endpoint
+#define ARM_USB_ENDPOINT_INTERRUPT      (3U)     ///< Interrupt Endpoint
+
+/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */
+#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK           (0x07FFU)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK   (0x1800U)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1      (0x0000U)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2      (0x0800U)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3      (0x1000U)
+
+#endif /* DRIVER_USB_H_ */

CMSIS-DAP/Driver/Include/Driver_USBD.h

@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. March 2020
+ * $Revision:    V2.3
+ *
+ * Project:      USB Device Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Removed volatile from ARM_USBD_STATE
+ *  Version 2.2
+ *    ARM_USBD_STATE made volatile
+ *  Version 2.1
+ *    Added ARM_USBD_ReadSetupPacket function
+ *  Version 2.0
+ *    Removed ARM_USBD_DeviceConfigure function
+ *    Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function
+ *    Removed ARM_USBD_EndpointReadStart function
+ *    Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer
+ *    Added ARM_USBD_EndpointTransferGetResult function
+ *    Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBD_H_
+#define DRIVER_USBD_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_USBD_(n)      Driver_USBD##n
+#define  ARM_Driver_USBD_(n) _ARM_Driver_USBD_(n)
+
+
+/**
+\brief USB Device State
+*/
+typedef struct _ARM_USBD_STATE {
+  uint32_t vbus     : 1;                ///< USB Device VBUS flag
+  uint32_t speed    : 2;                ///< USB Device speed setting (ARM_USB_SPEED_xxx)
+  uint32_t active   : 1;                ///< USB Device active flag
+  uint32_t reserved : 28;
+} ARM_USBD_STATE;
+
+
+/****** USB Device Event *****/
+#define ARM_USBD_EVENT_VBUS_ON          (1UL << 0)      ///< USB Device VBUS On
+#define ARM_USBD_EVENT_VBUS_OFF         (1UL << 1)      ///< USB Device VBUS Off
+#define ARM_USBD_EVENT_RESET            (1UL << 2)      ///< USB Reset occurred
+#define ARM_USBD_EVENT_HIGH_SPEED       (1UL << 3)      ///< USB switch to High Speed occurred
+#define ARM_USBD_EVENT_SUSPEND          (1UL << 4)      ///< USB Suspend occurred
+#define ARM_USBD_EVENT_RESUME           (1UL << 5)      ///< USB Resume occurred
+
+/****** USB Endpoint Event *****/
+#define ARM_USBD_EVENT_SETUP            (1UL << 0)      ///< SETUP Packet
+#define ARM_USBD_EVENT_OUT              (1UL << 1)      ///< OUT Packet(s)
+#define ARM_USBD_EVENT_IN               (1UL << 2)      ///< IN Packet(s)
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBD_STATE ARM_USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointConfigure (uint8_t  ep_addr,
+                                                   uint8_t  ep_type,
+                                                   uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBD_SignalDeviceEvent (uint32_t event)
+  \brief       Signal USB Device Event.
+  \param[in]   event \ref USBD_dev_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)
+  \brief       Signal USB Endpoint Event.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   event \ref USBD_ep_events
+  \return      none
+*/
+
+typedef void (*ARM_USBD_SignalDeviceEvent_t)   (uint32_t event);                    ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event.
+typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event);   ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event.
+
+
+/**
+\brief USB Device Driver Capabilities.
+*/
+typedef struct _ARM_USBD_CAPABILITIES {
+  uint32_t vbus_detection  : 1;         ///< VBUS detection
+  uint32_t event_vbus_on   : 1;         ///< Signal VBUS On event
+  uint32_t event_vbus_off  : 1;         ///< Signal VBUS Off event
+  uint32_t reserved        : 29;        ///< Reserved (must be zero)
+} ARM_USBD_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USB Device Driver.
+*/
+typedef struct _ARM_DRIVER_USBD {
+  ARM_DRIVER_VERSION    (*GetVersion)                (void);                                              ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version.
+  ARM_USBD_CAPABILITIES (*GetCapabilities)           (void);                                              ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)                (ARM_USBD_SignalDeviceEvent_t   cb_device_event,                     
+                                                      ARM_USBD_SignalEndpointEvent_t cb_endpoint_event);  ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. 
+  int32_t               (*Uninitialize)              (void);                                              ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface.
+  int32_t               (*PowerControl)              (ARM_POWER_STATE state);                             ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power.
+  int32_t               (*DeviceConnect)             (void);                                              ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device.
+  int32_t               (*DeviceDisconnect)          (void);                                              ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device.
+  ARM_USBD_STATE        (*DeviceGetState)            (void);                                              ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State.
+  int32_t               (*DeviceRemoteWakeup)        (void);                                              ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup.
+  int32_t               (*DeviceSetAddress)          (uint8_t dev_addr);                                  ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address.
+  int32_t               (*ReadSetupPacket)           (uint8_t *setup);                                    ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint.
+  int32_t               (*EndpointConfigure)         (uint8_t ep_addr,
+                                                      uint8_t ep_type,
+                                                      uint16_t ep_max_packet_size);                       ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint.
+  int32_t               (*EndpointUnconfigure)       (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.
+  int32_t               (*EndpointStall)             (uint8_t ep_addr, bool stall);                       ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.
+  int32_t               (*EndpointTransfer)          (uint8_t ep_addr, uint8_t *data, uint32_t num);      ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint.
+  uint32_t              (*EndpointTransferGetResult) (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer.
+  int32_t               (*EndpointTransferAbort)     (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer.
+  uint16_t              (*GetFrameNumber)            (void);                                              ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number.
+} const ARM_DRIVER_USBD;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBD_H_ */

CMSIS-DAP/Driver/Include/Driver_USBH.h

@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+  *
+ * $Date:        31. March 2020
+ * $Revision:    V2.3
+ *
+ * Project:      USB Host Driver definitions
+*/
+
+/* History:
+ *  Version 2.3
+ *    Removed volatile from ARM_USBH_PORT_STATE
+ *  Version 2.2
+ *    ARM_USBH_PORT_STATE made volatile
+ *  Version 2.1
+ *    Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE
+ *    Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe...
+ *    Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent
+ *  Version 2.0
+ *    Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff
+ *    Changed function ARM_USBH_EndpointCreate parameters
+ *    Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify
+ *    Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset
+ *    Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer
+ *    Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort
+ *    Added function ARM_USBH_EndpointTransferGetResult
+ *    Added function ARM_USBH_GetFrameNumber
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.20
+ *    Added API for OHCI/EHCI Host Controller Interface (HCI)
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBH_H_
+#define DRIVER_USBH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+#define _ARM_Driver_USBH_(n)      Driver_USBH##n
+#define  ARM_Driver_USBH_(n) _ARM_Driver_USBH_(n)
+
+
+/**
+\brief USB Host Port State
+*/
+typedef struct _ARM_USBH_PORT_STATE {
+  uint32_t connected   : 1;             ///< USB Host Port connected flag
+  uint32_t overcurrent : 1;             ///< USB Host Port overcurrent flag
+  uint32_t speed       : 2;             ///< USB Host Port speed setting (ARM_USB_SPEED_xxx)
+  uint32_t reserved    : 28;
+} ARM_USBH_PORT_STATE;
+
+/**
+\brief USB Host Pipe Handle
+*/
+typedef uint32_t ARM_USBH_PIPE_HANDLE;
+#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE  /* Legacy name */
+
+
+/****** USB Host Packet Information *****/
+#define ARM_USBH_PACKET_TOKEN_Pos         0
+#define ARM_USBH_PACKET_TOKEN_Msk        (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos)
+#define ARM_USBH_PACKET_SETUP            (0x01UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< SETUP Packet
+#define ARM_USBH_PACKET_OUT              (0x02UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< OUT Packet
+#define ARM_USBH_PACKET_IN               (0x03UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< IN Packet
+#define ARM_USBH_PACKET_PING             (0x04UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< PING Packet
+
+#define ARM_USBH_PACKET_DATA_Pos          4
+#define ARM_USBH_PACKET_DATA_Msk         (0x0FUL << ARM_USBH_PACKET_DATA_Pos)
+#define ARM_USBH_PACKET_DATA0            (0x01UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA0 PID
+#define ARM_USBH_PACKET_DATA1            (0x02UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA1 PID
+
+#define ARM_USBH_PACKET_SPLIT_Pos         8
+#define ARM_USBH_PACKET_SPLIT_Msk        (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos)
+#define ARM_USBH_PACKET_SSPLIT           (0x08UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet
+#define ARM_USBH_PACKET_SSPLIT_S         (0x09UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data Start
+#define ARM_USBH_PACKET_SSPLIT_E         (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data End
+#define ARM_USBH_PACKET_SSPLIT_S_E       (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data All
+#define ARM_USBH_PACKET_CSPLIT           (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< CSPLIT Packet
+
+#define ARM_USBH_PACKET_PRE              (1UL << 12)                            ///< PRE Token
+
+
+/****** USB Host Port Event *****/
+#define ARM_USBH_EVENT_CONNECT           (1UL << 0)     ///< USB Device Connected to Port
+#define ARM_USBH_EVENT_DISCONNECT        (1UL << 1)     ///< USB Device Disconnected from Port
+#define ARM_USBH_EVENT_OVERCURRENT       (1UL << 2)     ///< USB Device caused Overcurrent
+#define ARM_USBH_EVENT_RESET             (1UL << 3)     ///< USB Reset completed
+#define ARM_USBH_EVENT_SUSPEND           (1UL << 4)     ///< USB Suspend occurred
+#define ARM_USBH_EVENT_RESUME            (1UL << 5)     ///< USB Resume occurred
+#define ARM_USBH_EVENT_REMOTE_WAKEUP     (1UL << 6)     ///< USB Device activated Remote Wakeup
+
+/****** USB Host Pipe Event *****/
+#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0)     ///< Transfer completed
+#define ARM_USBH_EVENT_HANDSHAKE_NAK     (1UL << 1)     ///< NAK Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_NYET    (1UL << 2)     ///< NYET Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_MDATA   (1UL << 3)     ///< MDATA Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_STALL   (1UL << 4)     ///< STALL Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_ERR     (1UL << 5)     ///< ERR Handshake received
+#define ARM_USBH_EVENT_BUS_ERROR         (1UL << 6)     ///< Bus Error detected
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,
+                                            ARM_USBH_SignalPipeEvent_t cb_pipe_event)
+  \brief       Initialize USB Host Interface.
+  \param[in]   cb_port_event  Pointer to \ref ARM_USBH_SignalPortEvent
+  \param[in]   cb_pipe_event  Pointer to \ref ARM_USBH_SignalPipeEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_Uninitialize (void)
+  \brief       De-initialize USB Host Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortReset (uint8_t port)
+  \brief       Do Root HUB Port Reset.
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortSuspend (uint8_t port)
+  \brief       Suspend Root HUB Port (stop generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortResume (uint8_t port)
+  \brief       Resume Root HUB Port (start generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)
+  \brief       Get current Root HUB Port State.
+  \param[in]   port  Root HUB Port Number
+  \return      Port State \ref ARM_USBH_PORT_STATE
+*/
+/**
+  \fn          ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t  dev_addr,
+                                                         uint8_t  dev_speed,
+                                                         uint8_t  hub_addr,
+                                                         uint8_t  hub_port,
+                                                         uint8_t  ep_addr,
+                                                         uint8_t  ep_type,
+                                                         uint16_t ep_max_packet_size,
+                                                         uint8_t  ep_interval)
+  \brief       Create Pipe in System.
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_addr    Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type    Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \param[in]   ep_interval        Endpoint Polling Interval
+  \return      Pipe Handle \ref ARM_USBH_PIPE_HANDLE
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                            uint8_t              dev_addr,
+                                            uint8_t              dev_speed,
+                                            uint8_t              hub_addr,
+                                            uint8_t              hub_port,
+                                            uint16_t             ep_max_packet_size)
+  \brief       Modify Pipe in System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Delete Pipe from System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Reset Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                              uint32_t             packet,
+                                              uint8_t             *data,
+                                              uint32_t             num)
+  \brief       Transfer packets through USB Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   packet     Packet information
+  \param[in]   data       Pointer to buffer with data to send or for data to receive
+  \param[in]   num        Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Get result of USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Abort current USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBH_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)
+  \brief       Signal Root HUB Port Event.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   event \ref USBH_port_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)
+  \brief       Signal Pipe Event.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   event  \ref USBH_pipe_events
+  \return      none
+*/
+
+typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event);                    ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event.
+typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event);  ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event.
+#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t  /* Legacy name */
+
+
+/**
+\brief USB Host Driver Capabilities.
+*/
+typedef struct _ARM_USBH_CAPABILITIES {
+  uint32_t port_mask          : 15;     ///< Root HUB available Ports Mask
+  uint32_t auto_split         :  1;     ///< Automatic SPLIT packet handling
+  uint32_t event_connect      :  1;     ///< Signal Connect event
+  uint32_t event_disconnect   :  1;     ///< Signal Disconnect event
+  uint32_t event_overcurrent  :  1;     ///< Signal Overcurrent event
+  uint32_t reserved           : 13;     ///< Reserved (must be zero)
+} ARM_USBH_CAPABILITIES;
+
+
+/**
+\brief Access structure of USB Host Driver.
+*/
+typedef struct _ARM_DRIVER_USBH {
+  ARM_DRIVER_VERSION    (*GetVersion)            (void);                                     ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version.
+  ARM_USBH_CAPABILITIES (*GetCapabilities)       (void);                                     ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)            (ARM_USBH_SignalPortEvent_t cb_port_event,            
+                                                  ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface.
+  int32_t               (*Uninitialize)          (void);                                     ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface.
+  int32_t               (*PowerControl)          (ARM_POWER_STATE state);                    ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power.
+  int32_t               (*PortVbusOnOff)         (uint8_t port, bool vbus);                  ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off.
+  int32_t               (*PortReset)             (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset.
+  int32_t               (*PortSuspend)           (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs).
+  int32_t               (*PortResume)            (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs).
+  ARM_USBH_PORT_STATE   (*PortGetState)          (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State.
+  ARM_USBH_PIPE_HANDLE  (*PipeCreate)            (uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint8_t ep_addr,
+                                                  uint8_t ep_type,
+                                                  uint16_t ep_max_packet_size,
+                                                  uint8_t ep_interval);                      ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System.
+  int32_t               (*PipeModify)            (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                                  uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint16_t ep_max_packet_size);              ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System.
+  int32_t               (*PipeDelete)            (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System.
+  int32_t               (*PipeReset)             (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe.
+  int32_t               (*PipeTransfer)          (ARM_USBH_PIPE_HANDLE pipe_hndl, 
+                                                  uint32_t packet,
+                                                  uint8_t *data,
+                                                  uint32_t num);                             ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe.
+  uint32_t              (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer.
+  int32_t               (*PipeTransferAbort)     (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer.
+  uint16_t              (*GetFrameNumber)        (void);                                     ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number.                    
+} const ARM_DRIVER_USBH;
+
+
+// HCI (OHCI/EHCI)
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)
+  \brief       Get USB Host HCI (OHCI/EHCI) driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_HCI_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+  \brief       Initialize USB Host HCI (OHCI/EHCI) Interface.
+  \param[in]   cb_interrupt Pointer to Interrupt Handler Routine
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Uninitialize (void)
+  \brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host HCI (OHCI/EHCI) Interface Power.
+  \param[in]   state Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_USBH_HCI_Interrupt (void)
+  \brief       USB Host HCI Interrupt Handler.
+  \return      none
+*/
+
+typedef void (*ARM_USBH_HCI_Interrupt_t) (void);  ///< Pointer to Interrupt Handler Routine.
+
+
+/**
+\brief USB Host HCI (OHCI/EHCI) Driver Capabilities.
+*/
+typedef struct _ARM_USBH_HCI_CAPABILITIES {
+  uint32_t port_mask : 15;              ///< Root HUB available Ports Mask
+  uint32_t reserved  : 17;              ///< Reserved (must be zero)
+} ARM_USBH_HCI_CAPABILITIES;
+
+
+/**
+  \brief Access structure of USB Host HCI (OHCI/EHCI) Driver.
+*/
+typedef struct _ARM_DRIVER_USBH_HCI {
+  ARM_DRIVER_VERSION        (*GetVersion)      (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version.
+  ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities.
+  int32_t                   (*Initialize)      (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*Uninitialize)    (void);                                  ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*PowerControl)    (ARM_POWER_STATE state);                 ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power.
+  int32_t                   (*PortVbusOnOff)   (uint8_t port, bool vbus);               ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+} const ARM_DRIVER_USBH_HCI;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBH_H_ */

CMSIS-DAP/Driver/Include/Driver_WiFi.h

@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        24. January 2020
+ * $Revision:    V1.1
+ *
+ * Project:      WiFi (Wireless Fidelity Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 1.1
+ *    Extended Socket Receive/Send (support for polling)
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_WIFI_H_
+#define DRIVER_WIFI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_WIFI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1)  /* API version */
+
+
+#define _ARM_Driver_WiFi_(n)      Driver_WiFi##n
+#define  ARM_Driver_WiFi_(n) _ARM_Driver_WiFi_(n)
+
+
+/****** WiFi SetOption/GetOption Function Option Codes *****/
+#define ARM_WIFI_BSSID                      1U          ///< Station/AP Set/Get BSSID of AP to connect or of AP;        data = &bssid,    len =  6, uint8_t[6]
+#define ARM_WIFI_TX_POWER                   2U          ///< Station/AP Set/Get transmit power;                         data = &power,    len =  4, uint32_t: 0 .. 20 [dBm]
+#define ARM_WIFI_LP_TIMER                   3U          ///< Station    Set/Get low-power deep-sleep time;              data = &time,     len =  4, uint32_t [seconds]: 0 = disable (default)
+#define ARM_WIFI_DTIM                       4U          ///< Station/AP Set/Get DTIM interval;                          data = &dtim,     len =  4, uint32_t [beacons]
+#define ARM_WIFI_BEACON                     5U          ///<         AP Set/Get beacon interval;                        data = &interval, len =  4, uint32_t [ms]
+#define ARM_WIFI_MAC                        6U          ///< Station/AP Set/Get MAC;                                    data = &mac,      len =  6, uint8_t[6]
+#define ARM_WIFI_IP                         7U          ///< Station/AP Set/Get IPv4 static/assigned address;           data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_SUBNET_MASK             8U          ///< Station/AP Set/Get IPv4 subnet mask;                       data = &mask,     len =  4, uint8_t[4]
+#define ARM_WIFI_IP_GATEWAY                 9U          ///< Station/AP Set/Get IPv4 gateway address;                   data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DNS1                    10U         ///< Station/AP Set/Get IPv4 primary   DNS address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DNS2                    11U         ///< Station/AP Set/Get IPv4 secondary DNS address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP                    12U         ///< Station/AP Set/Get IPv4 DHCP client/server enable/disable; data = &dhcp,     len =  4, uint32_t: 0 = disable, non-zero = enable (default)
+#define ARM_WIFI_IP_DHCP_POOL_BEGIN         13U         ///<         AP Set/Get IPv4 DHCP pool begin address;           data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP_POOL_END           14U         ///<         AP Set/Get IPv4 DHCP pool end address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP_LEASE_TIME         15U         ///<         AP Set/Get IPv4 DHCP lease time;                   data = &time,     len =  4, uint32_t [seconds]
+#define ARM_WIFI_IP6_GLOBAL                 16U         ///< Station/AP Set/Get IPv6 global address;                    data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_LINK_LOCAL             17U         ///< Station/AP Set/Get IPv6 link local address;                data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_SUBNET_PREFIX_LEN      18U         ///< Station/AP Set/Get IPv6 subnet prefix length;              data = &len,      len =  4, uint32_t: 1 .. 127
+#define ARM_WIFI_IP6_GATEWAY                19U         ///< Station/AP Set/Get IPv6 gateway address;                   data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DNS1                   20U         ///< Station/AP Set/Get IPv6 primary   DNS address;             data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DNS2                   21U         ///< Station/AP Set/Get IPv6 secondary DNS address;             data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DHCP_MODE              22U         ///< Station/AP Set/Get IPv6 DHCPv6 client mode;                data = &mode,     len =  4, uint32_t: ARM_WIFI_IP6_DHCP_xxx (default Off)
+
+/****** WiFi Security Type *****/
+#define ARM_WIFI_SECURITY_OPEN              0U          ///< Open
+#define ARM_WIFI_SECURITY_WEP               1U          ///< Wired Equivalent Privacy (WEP) with Pre-Sheared Key (PSK)
+#define ARM_WIFI_SECURITY_WPA               2U          ///< WiFi Protected Access (WPA) with PSK
+#define ARM_WIFI_SECURITY_WPA2              3U          ///< WiFi Protected Access II (WPA2) with PSK
+#define ARM_WIFI_SECURITY_UNKNOWN           255U        ///< Unknown
+
+/****** WiFi Protected Setup (WPS) Method *****/
+#define ARM_WIFI_WPS_METHOD_NONE            0U          ///< Not used
+#define ARM_WIFI_WPS_METHOD_PBC             1U          ///< Push Button Configuration
+#define ARM_WIFI_WPS_METHOD_PIN             2U          ///< PIN
+
+/****** WiFi IPv6 Dynamic Host Configuration Protocol (DHCP) Mode *****/
+#define ARM_WIFI_IP6_DHCP_OFF               0U          ///< Static Host Configuration (default)
+#define ARM_WIFI_IP6_DHCP_STATELESS         1U          ///< Dynamic Host Configuration stateless DHCPv6
+#define ARM_WIFI_IP6_DHCP_STATEFULL         2U          ///< Dynamic Host Configuration statefull DHCPv6
+
+/****** WiFi Event *****/
+#define ARM_WIFI_EVENT_AP_CONNECT          (1UL << 0)   ///< Access Point: Station has connected;           arg = &mac, mac (uint8_t[6])
+#define ARM_WIFI_EVENT_AP_DISCONNECT       (1UL << 1)   ///< Access Point: Station has disconnected;        arg = &mac, mac (uint8_t[6])
+#define ARM_WIFI_EVENT_ETH_RX_FRAME        (1UL << 4)   ///< Ethernet Frame Received (in bypass mode only); arg = interface (0 = Station, 1 = Access Point)
+
+
+/**
+\brief WiFi Configuration
+*/
+typedef struct ARM_WIFI_CONFIG_s {
+  const char   *ssid;                                   ///< Pointer to Service Set Identifier (SSID) null-terminated string
+  const char   *pass;                                   ///< Pointer to Password null-terminated string
+        uint8_t security;                               ///< Security type (ARM_WIFI_SECURITY_xxx)
+        uint8_t ch;                                     ///< WiFi Channel (0 = auto, otherwise = exact channel)
+        uint8_t reserved;                               ///< Reserved
+        uint8_t wps_method;                             ///< WiFi Protected Setup (WPS) method (ARM_WIFI_WPS_METHOD_xxx)
+  const char   *wps_pin;                                ///< Pointer to WiFi Protected Setup (WPS) PIN null-terminated string
+} ARM_WIFI_CONFIG_t;
+
+/**
+\brief WiFi Scan Information
+*/
+typedef struct ARM_WIFI_SCAN_INFO_s {
+  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string
+  uint8_t bssid[6];                                     ///< Basic Service Set Identifier (BSSID)
+  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)
+  uint8_t ch;                                           ///< WiFi Channel
+  uint8_t rssi;                                         ///< Received Signal Strength Indicator
+} ARM_WIFI_SCAN_INFO_t;
+
+/**
+\brief WiFi Network Information
+*/
+typedef struct ARM_WIFI_NET_INFO_s {
+  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string
+  char    pass[64+1];                                   ///< Password null-terminated string
+  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)
+  uint8_t ch;                                           ///< WiFi Channel
+  uint8_t rssi;                                         ///< Received Signal Strength Indicator
+} ARM_WIFI_NET_INFO_t;
+
+/****** Socket Address Family definitions *****/
+#define ARM_SOCKET_AF_INET                  1           ///< IPv4
+#define ARM_SOCKET_AF_INET6                 2           ///< IPv6
+
+/****** Socket Type definitions *****/
+#define ARM_SOCKET_SOCK_STREAM              1           ///< Stream socket
+#define ARM_SOCKET_SOCK_DGRAM               2           ///< Datagram socket
+
+/****** Socket Protocol definitions *****/
+#define ARM_SOCKET_IPPROTO_TCP              1           ///< TCP
+#define ARM_SOCKET_IPPROTO_UDP              2           ///< UDP
+
+/****** Socket Option definitions *****/
+#define ARM_SOCKET_IO_FIONBIO               1           ///< Non-blocking I/O (Set only, default = 0); opt_val = &nbio, opt_len = sizeof(nbio), nbio (integer): 0=blocking, non-blocking otherwise
+#define ARM_SOCKET_SO_RCVTIMEO              2           ///< Receive timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)
+#define ARM_SOCKET_SO_SNDTIMEO              3           ///< Send timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)
+#define ARM_SOCKET_SO_KEEPALIVE             4           ///< Keep-alive messages (default = 0); opt_val = &keepalive, opt_len = sizeof(keepalive), keepalive (integer): 0=disabled, enabled otherwise
+#define ARM_SOCKET_SO_TYPE                  5           ///< Socket Type (Get only); opt_val = &socket_type, opt_len = sizeof(socket_type), socket_type (integer): ARM_SOCKET_SOCK_xxx
+
+/****** Socket Function return codes *****/
+#define ARM_SOCKET_ERROR                   (-1)         ///< Unspecified error
+#define ARM_SOCKET_ESOCK                   (-2)         ///< Invalid socket
+#define ARM_SOCKET_EINVAL                  (-3)         ///< Invalid argument
+#define ARM_SOCKET_ENOTSUP                 (-4)         ///< Operation not supported
+#define ARM_SOCKET_ENOMEM                  (-5)         ///< Not enough memory
+#define ARM_SOCKET_EAGAIN                  (-6)         ///< Operation would block or timed out
+#define ARM_SOCKET_EINPROGRESS             (-7)         ///< Operation in progress
+#define ARM_SOCKET_ETIMEDOUT               (-8)         ///< Operation timed out
+#define ARM_SOCKET_EISCONN                 (-9)         ///< Socket is connected
+#define ARM_SOCKET_ENOTCONN                (-10)        ///< Socket is not connected
+#define ARM_SOCKET_ECONNREFUSED            (-11)        ///< Connection rejected by the peer
+#define ARM_SOCKET_ECONNRESET              (-12)        ///< Connection reset by the peer
+#define ARM_SOCKET_ECONNABORTED            (-13)        ///< Connection aborted locally
+#define ARM_SOCKET_EALREADY                (-14)        ///< Connection already in progress
+#define ARM_SOCKET_EADDRINUSE              (-15)        ///< Address in use
+#define ARM_SOCKET_EHOSTNOTFOUND           (-16)        ///< Host not found
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_WIFI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_WIFI_CAPABILITIES ARM_WIFI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_WIFI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_WIFI_Initialize (ARM_WIFI_SignalEvent_t cb_event)
+  \brief         Initialize WiFi Module.
+  \param[in]     cb_event Pointer to \ref ARM_WIFI_SignalEvent_t
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+*/
+/**
+  \fn            int32_t ARM_WIFI_Uninitialize (void)
+  \brief         De-initialize WiFi Module.
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+*/
+/**
+  \fn            int32_t ARM_WIFI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control WiFi Module Power.
+  \param[in]     state     Power state
+                   - \ref ARM_POWER_OFF                : Power off: no operation possible
+                   - \ref ARM_POWER_LOW                : Low-power mode: sleep or deep-sleep depending on \ref ARM_WIFI_LP_TIMER option set
+                   - \ref ARM_POWER_FULL               : Power on: full operation at maximum performance
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid state)
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetModuleInfo (char *module_info, uint32_t max_len)
+  \brief         Get Module information.
+  \param[out]    module_info Pointer to character buffer were info string will be returned
+  \param[in]     max_len     Maximum length of string to return (including null terminator)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL module_info pointer or max_len equals to 0)
+*/
+/**
+  \fn            int32_t ARM_WIFI_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len)
+  \brief         Set WiFi Module Options.
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     option    Option to set
+  \param[in]     data      Pointer to data relevant to selected option
+  \param[in]     len       Length of data (in bytes)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data pointer or len less than option specifies)
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len)
+  \brief         Get WiFi Module Options.
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     option    Option to get
+  \param[out]    data      Pointer to memory where data for selected option will be returned
+  \param[in,out] len       Pointer to length of data (input/output)
+                   - input: maximum length of data that can be returned (in bytes)
+                   - output: length of returned data (in bytes)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data or len pointer, or *len less than option specifies)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num)
+  \brief         Scan for available networks in range.
+  \param[out]    scan_info Pointer to array of ARM_WIFI_SCAN_INFO_t structures where available Scan Information will be returned
+  \param[in]     max_num   Maximum number of Network Information structures to return
+  \return        number of ARM_WIFI_SCAN_INFO_t structures returned or error code
+                   - value >= 0                        : Number of ARM_WIFI_SCAN_INFO_t structures returned
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL scan_info pointer or max_num equal to 0)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Activate (uint32_t interface, ARM_WIFI_CONFIG_t *config)
+  \brief         Activate interface (Connect to a wireless network or activate an access point).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     config    Pointer to ARM_WIFI_CONFIG_t structure where Configuration parameters are located
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported (security type, channel autodetect or WPS not supported)
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL config pointer or invalid configuration)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Deactivate (uint32_t interface)
+  \brief         Deactivate interface (Disconnect from a wireless network or deactivate an access point).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface)
+*/
+/**
+  \fn            uint32_t ARM_WIFI_IsConnected (void)
+  \brief         Get station connection status.
+  \return        station connection status
+                   - value != 0: Station connected
+                   - value = 0: Station not connected
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info)
+  \brief         Get station Network Information.
+  \param[out]    net_info  Pointer to ARM_WIFI_NET_INFO_t structure where station Network Information will be returned
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed (station not connected)
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL net_info pointer)
+*/
+/**
+  \fn            int32_t ARM_WIFI_BypassControl (uint32_t interface, uint32_t mode)
+  \brief         Enable or disable bypass (pass-through) mode. Transmit and receive Ethernet frames (IP layer bypassed and WiFi/Ethernet translation).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     mode
+                   - value = 1: all packets bypass internal IP stack
+                   - value = 0: all packets processed by internal IP stack
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or mode)
+*/
+/**
+  \fn            int32_t ARM_WIFI_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len)
+  \brief         Send Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     frame    Pointer to frame buffer with data to send
+  \param[in]     len      Frame buffer length in bytes
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_BUSY        : Driver is busy
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)
+*/
+/**
+  \fn            int32_t ARM_WIFI_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len)
+  \brief         Read data of received Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     frame    Pointer to frame buffer for data to read into
+  \param[in]     len      Frame buffer length in bytes
+  \return        number of data bytes read or error code
+                   - value >= 0                        : Number of data bytes read
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)
+*/
+/**
+  \fn            uint32_t ARM_WIFI_EthGetRxFrameSize (uint32_t interface)
+  \brief         Get size of received Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \return        number of bytes in received frame
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketCreate (int32_t af, int32_t type, int32_t protocol)
+  \brief         Create a communication socket.
+  \param[in]     af       Address family
+  \param[in]     type     Socket type
+  \param[in]     protocol Socket protocol
+  \return        status information
+                   - Socket identification number (>=0)
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ENOMEM            : Not enough memory
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Assign a local address to a socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     ip       Pointer to local IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Local port number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (address or socket already bound)
+                   - \ref ARM_SOCKET_EADDRINUSE        : Address already in use
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketListen (int32_t socket, int32_t backlog)
+  \brief         Listen for socket connections.
+  \param[in]     socket   Socket identification number
+  \param[in]     backlog  Number of connection requests that can be queued
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (socket not bound)
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_EISCONN           : Socket is already connected
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Accept a new connection on a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where address of connecting socket shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where port of connecting socket shall be returned (NULL for none)
+  \return        status information
+                   - socket identification number of accepted socket (>=0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (socket not in listen mode)
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported (socket type does not support accepting connections)
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Connect a socket to a remote host.
+  \param[in]     socket   Socket identification number
+  \param[in]     ip       Pointer to remote IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Remote port number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_EALREADY          : Connection already in progress
+                   - \ref ARM_SOCKET_EINPROGRESS       : Operation in progress
+                   - \ref ARM_SOCKET_EISCONN           : Socket is connected
+                   - \ref ARM_SOCKET_ECONNREFUSED      : Connection rejected by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EADDRINUSE        : Address already in use
+                   - \ref ARM_SOCKET_ETIMEDOUT         : Operation timed out
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketRecv (int32_t socket, void *buf, uint32_t len)
+  \brief         Receive data on a connected socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    buf      Pointer to buffer where data should be stored
+  \param[in]     len      Length of buffer (in bytes)
+  \return        status information
+                   - number of bytes received (>=0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Receive data on a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    buf      Pointer to buffer where data should be stored
+  \param[in]     len      Length of buffer (in bytes)
+  \param[out]    ip       Pointer to buffer where remote source address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where remote source port shall be returned (NULL for none)
+  \return        status information
+                   - number of bytes received (>=0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSend (int32_t socket, const void *buf, uint32_t len)
+  \brief         Send data on a connected socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     buf      Pointer to buffer containing data to send
+  \param[in]     len      Length of data (in bytes)
+  \return        status information
+                   - number of bytes sent (>=0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Send data on a socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     buf      Pointer to buffer containing data to send
+  \param[in]     len      Length of data (in bytes)
+  \param[in]     ip       Pointer to remote destination IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Remote destination port number
+  \return        status information
+                   - number of bytes sent (>=0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Retrieve local IP address and port of a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where local address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where local port shall be returned (NULL for none)
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Retrieve remote IP address and port of a socket
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where remote address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where remote port shall be returned (NULL for none)
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len)
+  \brief         Get socket option.
+  \param[in]     socket   Socket identification number
+  \param[in]     opt_id   Option identifier
+  \param[out]    opt_val  Pointer to the buffer that will receive the option value
+  \param[in,out] opt_len  Pointer to length of the option value
+                   - length of buffer on input
+                   - length of data on output
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len)
+  \brief         Set socket option.
+  \param[in]     socket   Socket identification number
+  \param[in]     opt_id   Option identifier
+  \param[in]     opt_val  Pointer to the option value
+  \param[in]     opt_len  Length of the option value in bytes
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketClose (int32_t socket)
+  \brief         Close and release a socket.
+  \param[in]     socket   Socket identification number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len)
+  \brief         Retrieve host IP address from host name.
+  \param[in]     name     Host name
+  \param[in]     af       Address family
+  \param[out]    ip       Pointer to buffer where resolved IP address shall be returned
+  \param[in,out] ip_len   Pointer to length of 'ip'
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ETIMEDOUT         : Operation timed out
+                   - \ref ARM_SOCKET_EHOSTNOTFOUND     : Host not found
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_Ping (const uint8_t *ip, uint32_t ip_len)
+  \brief         Probe remote host with Ping command.
+  \param[in]     ip       Pointer to remote host IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL ip pointer or ip_len different than 4 or 16)
+*/
+/**
+  \fn            void ARM_WIFI_SignalEvent (uint32_t event, void *arg)
+  \brief         Signal WiFi Events.
+  \param[in]     event    \ref wifi_event notification mask
+  \param[in]     arg      Pointer to argument of signaled event
+  \return        none
+*/
+
+typedef void (*ARM_WIFI_SignalEvent_t) (uint32_t event, void *arg); ///< Pointer to \ref ARM_WIFI_SignalEvent : Signal WiFi Event.
+
+
+/**
+\brief WiFi Driver Capabilities.
+*/
+typedef struct _ARM_WIFI_CAPABILITIES {
+  uint32_t station               : 1;   ///< Station
+  uint32_t ap                    : 1;   ///< Access Point
+  uint32_t station_ap            : 1;   ///< Concurrent Station and Access Point
+  uint32_t wps_station           : 1;   ///< WiFi Protected Setup (WPS) for Station
+  uint32_t wps_ap                : 1;   ///< WiFi Protected Setup (WPS) for Access Point
+  uint32_t event_ap_connect      : 1;   ///< Access Point: event generated on Station connect
+  uint32_t event_ap_disconnect   : 1;   ///< Access Point: event generated on Station disconnect
+  uint32_t event_eth_rx_frame    : 1;   ///< Event generated on Ethernet frame reception in bypass mode
+  uint32_t bypass_mode           : 1;   ///< Bypass or pass-through mode (Ethernet interface)
+  uint32_t ip                    : 1;   ///< IP (UDP/TCP) (Socket interface)
+  uint32_t ip6                   : 1;   ///< IPv6 (Socket interface)
+  uint32_t ping                  : 1;   ///< Ping (ICMP)
+  uint32_t reserved              : 20;  ///< Reserved (must be zero)
+} ARM_WIFI_CAPABILITIES;
+
+/**
+\brief Access structure of the WiFi Driver.
+*/
+typedef struct _ARM_DRIVER_WIFI {
+  ARM_DRIVER_VERSION    (*GetVersion)                  (void);
+  ARM_WIFI_CAPABILITIES (*GetCapabilities)             (void);
+  int32_t               (*Initialize)                  (ARM_WIFI_SignalEvent_t cb_event);
+  int32_t               (*Uninitialize)                (void);
+  int32_t               (*PowerControl)                (ARM_POWER_STATE state);
+  int32_t               (*GetModuleInfo)               (char *module_info, uint32_t max_len);
+  int32_t               (*SetOption)                   (uint32_t interface, uint32_t option, const void *data, uint32_t  len);
+  int32_t               (*GetOption)                   (uint32_t interface, uint32_t option,       void *data, uint32_t *len);
+  int32_t               (*Scan)                        (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num);
+  int32_t               (*Activate)                    (uint32_t interface, const ARM_WIFI_CONFIG_t *config);
+  int32_t               (*Deactivate)                  (uint32_t interface);
+  uint32_t              (*IsConnected)                 (void);
+  int32_t               (*GetNetInfo)                  (ARM_WIFI_NET_INFO_t *net_info);
+  int32_t               (*BypassControl)               (uint32_t interface, uint32_t mode);
+  int32_t               (*EthSendFrame)                (uint32_t interface, const uint8_t *frame, uint32_t len);
+  int32_t               (*EthReadFrame)                (uint32_t interface,       uint8_t *frame, uint32_t len);
+  uint32_t              (*EthGetRxFrameSize)           (uint32_t interface);
+  int32_t               (*SocketCreate)                (int32_t af, int32_t type, int32_t protocol);
+  int32_t               (*SocketBind)                  (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);
+  int32_t               (*SocketListen)                (int32_t socket, int32_t backlog);
+  int32_t               (*SocketAccept)                (int32_t socket,       uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketConnect)               (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);
+  int32_t               (*SocketRecv)                  (int32_t socket, void *buf, uint32_t len);
+  int32_t               (*SocketRecvFrom)              (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketSend)                  (int32_t socket, const void *buf, uint32_t len);
+  int32_t               (*SocketSendTo)                (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port);
+  int32_t               (*SocketGetSockName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketGetPeerName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketGetOpt)                (int32_t socket, int32_t opt_id,       void *opt_val, uint32_t *opt_len);
+  int32_t               (*SocketSetOpt)                (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t  opt_len);
+  int32_t               (*SocketClose)                 (int32_t socket);
+  int32_t               (*SocketGetHostByName)         (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len);
+  int32_t               (*Ping)                        (const uint8_t *ip, uint32_t ip_len);
+} const ARM_DRIVER_WIFI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_WIFI_H_ */

CMSIS-DAP/Firmware/Config/DAP_config.h

@@ -1,35 +1,34 @@
-// vim: set et:
 /*
- * The MIT License (MIT)
+ * Copyright (c) 2013-2021 ARM Limited. All rights reserved.
  *
- * Copyright (c) 2021 Peter Lawrence
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
+ * www.apache.org/licenses/LICENSE-2.0
  *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/*
-This DAP_config provides a CMSIS-DAP alternative to picoprobe and raspberrypi-swd.cfg
-*/
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        16. June 2021
+ * $Revision:    V2.1.0
+ *
+ * Project:      CMSIS-DAP Configuration
+ * Title:        DAP_config.h CMSIS-DAP Configuration File (Template)
+ *
+ *---------------------------------------------------------------------------*/
 
 #ifndef __DAP_CONFIG_H__
 #define __DAP_CONFIG_H__
 
+
 //**************************************************************************************************
 /** 
 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
@@ -45,12 +44,16 @@ This information includes:
  - Optional information about a connected Target Device (for Evaluation Boards).
 */
 
-#include "cmsis_compiler.h"
-#include "util.h"
+#ifdef _RTE_
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#else
+#include "device.h"                             // Debug Unit Cortex-M Processor Header File
+#endif
 
 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
 /// This value is used to calculate the SWD/JTAG clock speed.
-#define CPU_CLOCK 48000000U  ///< Specifies the CPU Clock in Hz.
+#define CPU_CLOCK               100000000U      ///< Specifies the CPU Clock in Hz.
 
 /// Number of processor cycles for I/O Port write operations.
 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
@@ -58,164 +61,207 @@ This information includes:
 /// require 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be 
 /// required.
-#define IO_PORT_WRITE_CYCLES 2U  ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
+#define IO_PORT_WRITE_CYCLES    2U              ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
 
 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_SWD 1  ///< SWD Mode:  1 = available, 0 = not available.
+#define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available.
 
 /// Indicate that JTAG communication mode is available at the Debug Port.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_JTAG 1  ///< JTAG Mode: 1 = available, 0 = not available.
+#define DAP_JTAG                1               ///< JTAG Mode: 1 = available, 0 = not available.
 
 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
-#define DAP_JTAG_DEV_CNT 8U  ///< Maximum number of JTAG devices on scan chain.
+#define DAP_JTAG_DEV_CNT        8U              ///< Maximum number of JTAG devices on scan chain.
 
 /// Default communication mode on the Debug Access Port.
 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
-#define DAP_DEFAULT_PORT 2U  ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+#define DAP_DEFAULT_PORT        1U              ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
 
 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
 /// Used to initialize the default SWD/JTAG clock frequency.
 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
-#define DAP_DEFAULT_SWJ_CLOCK 1000000U  ///< Default SWD/JTAG clock frequency in Hz.
+#define DAP_DEFAULT_SWJ_CLOCK   1000000U        ///< Default SWD/JTAG clock frequency in Hz.
 
 /// Maximum Package Size for Command and Response data.
 /// This configuration settings is used to optimize the communication performance with the
-/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or
-/// WinUSB, 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
-#define DAP_PACKET_SIZE CFG_TUD_HID_EP_BUFSIZE  ///< Specifies Packet Size in bytes.
+/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
+/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
+#define DAP_PACKET_SIZE         512U            ///< Specifies Packet Size in bytes.
 
 /// Maximum Package Buffers for Command and Response data.
 /// This configuration settings is used to optimize the communication performance with the
 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
 /// setting can be reduced (valid range is 1 .. 255).
-#define DAP_PACKET_COUNT 1U  ///< Specifies number of packets buffered.
+#define DAP_PACKET_COUNT        8U              ///< Specifies number of packets buffered.
 
 /// Indicate that UART Serial Wire Output (SWO) trace is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define SWO_UART 0  ///< SWO UART:  1 = available, 0 = not available.
+#define SWO_UART                1               ///< SWO UART:  1 = available, 0 = not available.
+
+/// USART Driver instance number for the UART SWO.
+#define SWO_UART_DRIVER         0               ///< USART Driver instance number (Driver_USART#).
 
 /// Maximum SWO UART Baudrate.
-#define SWO_UART_MAX_BAUDRATE 10000000U  ///< SWO UART Maximum Baudrate in Hz.
+#define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz.
 
 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define SWO_MANCHESTER 0  ///< SWO Manchester:  1 = available, 0 = not available.
+#define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available.
 
 /// SWO Trace Buffer Size.
-#define SWO_BUFFER_SIZE 4096U  ///< SWO Trace Buffer Size in bytes (must be 2^n).
+#define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n).
 
 /// SWO Streaming Trace.
-#define SWO_STREAM 0  ///< SWO Streaming Trace: 1 = available, 0 = not available.
+#define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK         100000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
 
 /// Indicate that UART Communication Port is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_UART 0  ///< DAP UART:  1 = available, 0 = not available.
+#define DAP_UART                1               ///< DAP UART:  1 = available, 0 = not available.
 
 /// USART Driver instance number for the UART Communication Port.
-#define DAP_UART_DRIVER 1  ///< USART Driver instance number (Driver_USART#).
+#define DAP_UART_DRIVER         1               ///< USART Driver instance number (Driver_USART#).
 
 /// UART Receive Buffer Size.
-#define DAP_UART_RX_BUFFER_SIZE 64U  ///< Uart Receive Buffer Size in bytes (must be 2^n).
+#define DAP_UART_RX_BUFFER_SIZE 1024U           ///< Uart Receive Buffer Size in bytes (must be 2^n).
 
 /// UART Transmit Buffer Size.
-#define DAP_UART_TX_BUFFER_SIZE 64U  ///< Uart Transmit Buffer Size in bytes (must be 2^n).
+#define DAP_UART_TX_BUFFER_SIZE 1024U           ///< Uart Transmit Buffer Size in bytes (must be 2^n).
 
 /// Indicate that UART Communication via USB COM Port is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#ifdef USE_USBCDC_FOR_STDIO
-#define DAP_UART_USB_COM_PORT 1  ///< USB COM Port:  1 = available, 0 = not available.
-#else
-#define DAP_UART_USB_COM_PORT 0
-#endif
-
-/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
-#define TIMESTAMP_CLOCK 0U  ///< Timestamp clock in Hz (0 = timestamps not supported).
+#define DAP_UART_USB_COM_PORT   1               ///< USB COM Port:  1 = available, 0 = not available.
 
 /// Debug Unit is connected to fixed Target Device.
 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
-/// known device.  In this case a Device Vendor and Device Name string is stored which
-/// may be used by the debugger or IDE to configure device parameters.
-#define TARGET_DEVICE_FIXED 0  ///< Target Device: 1 = known, 0 = unknown;
+/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings
+/// are stored and may be used by the debugger or IDE to configure device parameters.
+#define TARGET_FIXED            0               ///< Target: 1 = known, 0 = unknown;
 
-#include "DAP.h"
+#define TARGET_DEVICE_VENDOR    "Arm"           ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME      "Cortex-M"      ///< String indicating the Target Device
+#define TARGET_BOARD_VENDOR     "Arm"           ///< String indicating the Board Vendor
+#define TARGET_BOARD_NAME       "Arm board"     ///< String indicating the Board Name
 
-/** Get Vendor ID string.
-\param str Pointer to buffer to store the string.
-\return String length.
+#if TARGET_FIXED != 0
+#include <string.h>
+static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;
+static const char TargetDeviceName   [] = TARGET_DEVICE_NAME;
+static const char TargetBoardVendor  [] = TARGET_BOARD_VENDOR;
+static const char TargetBoardName    [] = TARGET_BOARD_NAME;
+#endif
+
+/** Get Vendor Name string.
+\param str Pointer to buffer to store the string (max 60 characters).
+\return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetVendorString(char* str) {
-    static const char vnd[] = INFO_MANUFACTURER;
-    for (size_t i = 0; i < sizeof(vnd); ++i) str[i] = vnd[i];
-    return sizeof(vnd) - 1;
+__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
+  (void)str;
+  return (0U);
 }
 
-/** Get Product ID string.
-\param str Pointer to buffer to store the string.
-\return String length.
+/** Get Product Name string.
+\param str Pointer to buffer to store the string (max 60 characters).
+\return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetProductString(char* str) {
-    static const char prd[] = INFO_PRODUCT(INFO_BOARDNAME);
-    for (size_t i = 0; i < sizeof(prd); ++i) str[i] = prd[i];
-    return sizeof(prd) - 1;
+__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
+  (void)str;
+  return (0U);
 }
 
 /** Get Serial Number string.
-\param str Pointer to buffer to store the string.
-\return String length.
+\param str Pointer to buffer to store the string (max 60 characters).
+\return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetSerNumString(char* str) { return get_unique_id_u8((uint8_t*)str); }
+__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
+  (void)str;
+  return (0U);
+}
 
 /** Get Target Device Vendor string.
 \param str Pointer to buffer to store the string (max 60 characters).
 \return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString(char* str) {
-    (void)str;
-    return 0;
+__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) {
+#if TARGET_FIXED != 0
+  uint8_t len;
+
+  strcpy(str, TargetDeviceVendor);
+  len = (uint8_t)(strlen(TargetDeviceVendor) + 1U);
+  return (len);
+#else
+  (void)str;
+  return (0U);
+#endif
 }
 
 /** Get Target Device Name string.
 \param str Pointer to buffer to store the string (max 60 characters).
 \return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString(char* str) {
-    (void)str;
-    return 0;
+__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) {
+#if TARGET_FIXED != 0
+  uint8_t len;
+
+  strcpy(str, TargetDeviceName);
+  len = (uint8_t)(strlen(TargetDeviceName) + 1U);
+  return (len);
+#else
+  (void)str;
+  return (0U);
+#endif
 }
 
 /** Get Target Board Vendor string.
 \param str Pointer to buffer to store the string (max 60 characters).
 \return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString(char* str) {
-    (void)str;
-    return 0;
+__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) {
+#if TARGET_FIXED != 0
+  uint8_t len;
+
+  strcpy(str, TargetBoardVendor);
+  len = (uint8_t)(strlen(TargetBoardVendor) + 1U);
+  return (len);
+#else
+  (void)str;
+  return (0U);
+#endif
 }
 
 /** Get Target Board Name string.
 \param str Pointer to buffer to store the string (max 60 characters).
 \return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString(char* str) {
-    (void)str;
-    return 0;
+__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) {
+#if TARGET_FIXED != 0
+  uint8_t len;
+
+  strcpy(str, TargetBoardName);
+  len = (uint8_t)(strlen(TargetBoardName) + 1U);
+  return (len);
+#else
+  (void)str;
+  return (0U);
+#endif
 }
 
-/* TODO! */
 /** Get Product Firmware Version string.
 \param str Pointer to buffer to store the string (max 60 characters).
 \return String length (including terminating NULL character) or 0 (no string).
 */
-__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString(char* str) {
-    (void)str;
-    return 0;
+__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
+  (void)str;
+  return (0U);
 }
 
 ///@}
 
+
 //**************************************************************************************************
 /** 
 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
@@ -251,6 +297,7 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided:
  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
 */
 
+
 // Configure DAP I/O pins ------------------------------
 
 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
@@ -258,128 +305,172 @@ Configures the DAP Hardware I/O pins for JTAG mode:
  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
  - TDO to input mode.
 */ 
-__STATIC_INLINE void PORT_JTAG_SETUP(void) { }
+__STATIC_INLINE void PORT_JTAG_SETUP (void) {
+  ;
+}
  
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
 */ 
-__STATIC_INLINE void PORT_SWD_SETUP(void) { }
+__STATIC_INLINE void PORT_SWD_SETUP (void) {
+  ;
+}
 
 /** Disable JTAG/SWD I/O Pins.
 Disables the DAP Hardware I/O pins which configures:
  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
 */
-__STATIC_INLINE void PORT_OFF(void) { }
+__STATIC_INLINE void PORT_OFF (void) {
+  ;
+}
+
 
 // SWCLK/TCK I/O pin -------------------------------------
 
 /** SWCLK/TCK I/O pin: Get Input.
 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void) { return 0; }
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
+  return (0U);
+}
 
 /** SWCLK/TCK I/O pin: Set Output to High.
 Set the SWCLK/TCK DAP hardware I/O pin to high level.
 */
-__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void) { }
+__STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void) {
+  ;
+}
 
 /** SWCLK/TCK I/O pin: Set Output to Low.
 Set the SWCLK/TCK DAP hardware I/O pin to low level.
 */
-__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) { }
+__STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
+  ;
+}
+
 
 // SWDIO/TMS Pin I/O --------------------------------------
 
 /** SWDIO/TMS I/O pin: Get Input.
 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void) { return 0; }
-
-/* PIN_SWDIO_TMS_SET and PIN_SWDIO_TMS_CLR are used by SWJ_Sequence */
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
+  return (0U);
+}
 
 /** SWDIO/TMS I/O pin: Set Output to High.
 Set the SWDIO/TMS DAP hardware I/O pin to high level.
 */
-__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void) { }
+__STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void) {
+  ;
+}
 
 /** SWDIO/TMS I/O pin: Set Output to Low.
 Set the SWDIO/TMS DAP hardware I/O pin to low level.
 */
-__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) { }
+__STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void) {
+  ;
+}
 
 /** SWDIO I/O pin: Get Input (used in SWD mode only).
 \return Current status of the SWDIO DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) { return 0; }
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
+  return (0U);
+}
 
 /** SWDIO I/O pin: Set Output (used in SWD mode only).
 \param bit Output value for the SWDIO DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) { (void)bit; }
+__STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit) {
+  ;
+}
 
 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
 called prior \ref PIN_SWDIO_OUT function calls.
 */
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { }
+__STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void) {
+  ; 
+}
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
 called prior \ref PIN_SWDIO_IN function calls.
 */
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { }
+__STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
+  ;
+}
+
 
 // TDI Pin I/O ---------------------------------------------
 
 /** TDI I/O pin: Get Input.
 \return Current status of the TDI DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void) { return 0; }
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void) {
+  return (0U);
+}
 
 /** TDI I/O pin: Set Output.
 \param bit Output value for the TDI DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit) { (void)bit; }
+__STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
+  ;
+}
+
 
 // TDO Pin I/O ---------------------------------------------
 
 /** TDO I/O pin: Get Input.
 \return Current status of the TDO DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void) { return 0; }
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
+  return (0U);
+}
+
 
 // nTRST Pin I/O -------------------------------------------
 
 /** nTRST I/O pin: Get Input.
 \return Current status of the nTRST DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void) { return 0; }
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
+  return (0U);
+}
 
 /** nTRST I/O pin: Set Output.
 \param bit JTAG TRST Test Reset pin status:
            - 0: issue a JTAG TRST Test Reset.
            - 1: release JTAG TRST Test Reset.
 */
-__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) { (void)bit; }
+__STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
+  ; 
+}
 
 // nRESET Pin I/O------------------------------------------
 
 /** nRESET I/O pin: Get Input.
 \return Current status of the nRESET DAP hardware I/O pin.
 */
-__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) { return 0; }
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
+  return (0U);
+}
 
 /** nRESET I/O pin: Set Output.
 \param bit target device hardware reset pin status:
            - 0: issue a device hardware reset.
            - 1: release device hardware reset.
 */
-__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) { (void)bit; }
+__STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
+  ;
+}
 
 ///@}
 
+
 //**************************************************************************************************
 /** 
 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
@@ -398,17 +489,18 @@ It is recommended to provide the following LEDs for status indication:
            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
 */
-__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit) { (void)bit; }
+__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {}
 
 /** Debug Unit: Set status Target Running LED.
 \param bit status of the Target Running LED.
            - 1: Target Running LED ON: program execution in target started.
            - 0: Target Running LED OFF: program execution in target stopped.
 */
-__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit) { (void)bit; }
+__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {}
 
 ///@}
 
+
 //**************************************************************************************************
 /** 
 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
@@ -416,25 +508,21 @@ __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit) { (void)bit; }
 @{
 Access function for Test Domain Timer.
 
-The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET.
-By default, the DWT timer is used.  The frequency of this timer is configured with \ref
-TIMESTAMP_CLOCK.
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By 
+default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
 
 */
 
 /** Get timestamp of Test Domain Timer.
 \return Current timestamp value.
 */
-__STATIC_INLINE uint32_t TIMESTAMP_GET(void) {
-#if TIMESTAMP_CLOCK > 0
-    return (DWT->CYCCNT);
-#else
-    return 0;
-#endif
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+  return (DWT->CYCCNT);
 }
 
 ///@}
 
+
 //**************************************************************************************************
 /** 
 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
@@ -452,7 +540,9 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an
  - for nTRST, nRESET a weak pull-up (if available) is enabled.
  - LED output pins are enabled and LEDs are turned off.
 */
-__STATIC_INLINE void DAP_SETUP(void) { }
+__STATIC_INLINE void DAP_SETUP (void) {
+  ;
+}
 
 /** Reset Target Device with custom specific I/O pin or command sequence.
 This function allows the optional implementation of a device specific reset sequence.
@@ -461,10 +551,11 @@ when a device needs a time-critical unlock sequence that enables the debug port.
 \return 0 = no device specific reset sequence is implemented.\n
         1 = a device specific reset sequence is implemented.
 */
-__STATIC_INLINE uint8_t RESET_TARGET(void) {
-    return (0U);  // change to '1' when a device reset sequence is implemented
+__STATIC_INLINE uint8_t RESET_TARGET (void) {
+  return (0U);             // change to '1' when a device reset sequence is implemented
 }
 
 ///@}
 
+
 #endif /* __DAP_CONFIG_H__ */

CMSIS-DAP/Firmware/Include/DAP.h

@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2013-2021 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        26. May 2021
+ * $Revision:    V2.1.0
+ *
+ * Project:      CMSIS-DAP Include
+ * Title:        DAP.h Definitions
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef __DAP_H__
+#define __DAP_H__
+
+
+// DAP Firmware Version
+#ifdef  DAP_FW_V1
+#define DAP_FW_VER                      "1.3.0"
+#else
+#define DAP_FW_VER                      "2.1.0"
+#endif
+
+// DAP Command IDs
+#define ID_DAP_Info                     0x00U
+#define ID_DAP_HostStatus               0x01U
+#define ID_DAP_Connect                  0x02U
+#define ID_DAP_Disconnect               0x03U
+#define ID_DAP_TransferConfigure        0x04U
+#define ID_DAP_Transfer                 0x05U
+#define ID_DAP_TransferBlock            0x06U
+#define ID_DAP_TransferAbort            0x07U
+#define ID_DAP_WriteABORT               0x08U
+#define ID_DAP_Delay                    0x09U
+#define ID_DAP_ResetTarget              0x0AU
+#define ID_DAP_SWJ_Pins                 0x10U
+#define ID_DAP_SWJ_Clock                0x11U
+#define ID_DAP_SWJ_Sequence             0x12U
+#define ID_DAP_SWD_Configure            0x13U
+#define ID_DAP_SWD_Sequence             0x1DU
+#define ID_DAP_JTAG_Sequence            0x14U
+#define ID_DAP_JTAG_Configure           0x15U
+#define ID_DAP_JTAG_IDCODE              0x16U
+#define ID_DAP_SWO_Transport            0x17U
+#define ID_DAP_SWO_Mode                 0x18U
+#define ID_DAP_SWO_Baudrate             0x19U
+#define ID_DAP_SWO_Control              0x1AU
+#define ID_DAP_SWO_Status               0x1BU
+#define ID_DAP_SWO_ExtendedStatus       0x1EU
+#define ID_DAP_SWO_Data                 0x1CU
+#define ID_DAP_UART_Transport           0x1FU
+#define ID_DAP_UART_Configure           0x20U
+#define ID_DAP_UART_Control             0x22U
+#define ID_DAP_UART_Status              0x23U
+#define ID_DAP_UART_Transfer            0x21U
+
+#define ID_DAP_QueueCommands            0x7EU
+#define ID_DAP_ExecuteCommands          0x7FU
+
+// DAP Vendor Command IDs
+#define ID_DAP_Vendor0                  0x80U
+#define ID_DAP_Vendor1                  0x81U
+#define ID_DAP_Vendor2                  0x82U
+#define ID_DAP_Vendor3                  0x83U
+#define ID_DAP_Vendor4                  0x84U
+#define ID_DAP_Vendor5                  0x85U
+#define ID_DAP_Vendor6                  0x86U
+#define ID_DAP_Vendor7                  0x87U
+#define ID_DAP_Vendor8                  0x88U
+#define ID_DAP_Vendor9                  0x89U
+#define ID_DAP_Vendor10                 0x8AU
+#define ID_DAP_Vendor11                 0x8BU
+#define ID_DAP_Vendor12                 0x8CU
+#define ID_DAP_Vendor13                 0x8DU
+#define ID_DAP_Vendor14                 0x8EU
+#define ID_DAP_Vendor15                 0x8FU
+#define ID_DAP_Vendor16                 0x90U
+#define ID_DAP_Vendor17                 0x91U
+#define ID_DAP_Vendor18                 0x92U
+#define ID_DAP_Vendor19                 0x93U
+#define ID_DAP_Vendor20                 0x94U
+#define ID_DAP_Vendor21                 0x95U
+#define ID_DAP_Vendor22                 0x96U
+#define ID_DAP_Vendor23                 0x97U
+#define ID_DAP_Vendor24                 0x98U
+#define ID_DAP_Vendor25                 0x99U
+#define ID_DAP_Vendor26                 0x9AU
+#define ID_DAP_Vendor27                 0x9BU
+#define ID_DAP_Vendor28                 0x9CU
+#define ID_DAP_Vendor29                 0x9DU
+#define ID_DAP_Vendor30                 0x9EU
+#define ID_DAP_Vendor31                 0x9FU
+
+#define ID_DAP_Invalid                  0xFFU
+
+// DAP Status Code
+#define DAP_OK                          0U
+#define DAP_ERROR                       0xFFU
+
+// DAP ID
+#define DAP_ID_VENDOR                   1U
+#define DAP_ID_PRODUCT                  2U
+#define DAP_ID_SER_NUM                  3U
+#define DAP_ID_DAP_FW_VER               4U
+#define DAP_ID_DEVICE_VENDOR            5U
+#define DAP_ID_DEVICE_NAME              6U
+#define DAP_ID_BOARD_VENDOR             7U
+#define DAP_ID_BOARD_NAME               8U
+#define DAP_ID_PRODUCT_FW_VER           9U
+#define DAP_ID_CAPABILITIES             0xF0U
+#define DAP_ID_TIMESTAMP_CLOCK          0xF1U
+#define DAP_ID_UART_RX_BUFFER_SIZE      0xFBU
+#define DAP_ID_UART_TX_BUFFER_SIZE      0xFCU
+#define DAP_ID_SWO_BUFFER_SIZE          0xFDU
+#define DAP_ID_PACKET_COUNT             0xFEU
+#define DAP_ID_PACKET_SIZE              0xFFU
+
+// DAP Host Status
+#define DAP_DEBUGGER_CONNECTED          0U
+#define DAP_TARGET_RUNNING              1U
+
+// DAP Port
+#define DAP_PORT_AUTODETECT             0U      // Autodetect Port
+#define DAP_PORT_DISABLED               0U      // Port Disabled (I/O pins in High-Z)
+#define DAP_PORT_SWD                    1U      // SWD Port (SWCLK, SWDIO) + nRESET
+#define DAP_PORT_JTAG                   2U      // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET
+
+// DAP SWJ Pins
+#define DAP_SWJ_SWCLK_TCK               0       // SWCLK/TCK
+#define DAP_SWJ_SWDIO_TMS               1       // SWDIO/TMS
+#define DAP_SWJ_TDI                     2       // TDI
+#define DAP_SWJ_TDO                     3       // TDO
+#define DAP_SWJ_nTRST                   5       // nTRST
+#define DAP_SWJ_nRESET                  7       // nRESET
+
+// DAP Transfer Request
+#define DAP_TRANSFER_APnDP              (1U<<0)
+#define DAP_TRANSFER_RnW                (1U<<1)
+#define DAP_TRANSFER_A2                 (1U<<2)
+#define DAP_TRANSFER_A3                 (1U<<3)
+#define DAP_TRANSFER_MATCH_VALUE        (1U<<4)
+#define DAP_TRANSFER_MATCH_MASK         (1U<<5)
+#define DAP_TRANSFER_TIMESTAMP          (1U<<7)
+
+// DAP Transfer Response
+#define DAP_TRANSFER_OK                 (1U<<0)
+#define DAP_TRANSFER_WAIT               (1U<<1)
+#define DAP_TRANSFER_FAULT              (1U<<2)
+#define DAP_TRANSFER_ERROR              (1U<<3)
+#define DAP_TRANSFER_MISMATCH           (1U<<4)
+
+// DAP SWO Trace Mode
+#define DAP_SWO_OFF                     0U
+#define DAP_SWO_UART                    1U
+#define DAP_SWO_MANCHESTER              2U
+
+// DAP SWO Trace Status
+#define DAP_SWO_CAPTURE_ACTIVE          (1U<<0)
+#define DAP_SWO_CAPTURE_PAUSED          (1U<<1)
+#define DAP_SWO_STREAM_ERROR            (1U<<6)
+#define DAP_SWO_BUFFER_OVERRUN          (1U<<7)
+
+// DAP UART Transport
+#define DAP_UART_TRANSPORT_NONE         0U
+#define DAP_UART_TRANSPORT_USB_COM_PORT 1U
+#define DAP_UART_TRANSPORT_DAP_COMMAND  2U
+
+// DAP UART Control
+#define DAP_UART_CONTROL_RX_ENABLE      (1U<<0)
+#define DAP_UART_CONTROL_RX_DISABLE     (1U<<1)
+#define DAP_UART_CONTROL_RX_BUF_FLUSH   (1U<<2)
+#define DAP_UART_CONTROL_TX_ENABLE      (1U<<4)
+#define DAP_UART_CONTROL_TX_DISABLE     (1U<<5)
+#define DAP_UART_CONTROL_TX_BUF_FLUSH   (1U<<6)
+
+// DAP UART Status
+#define DAP_UART_STATUS_RX_ENABLED      (1U<<0)
+#define DAP_UART_STATUS_RX_DATA_LOST    (1U<<1)
+#define DAP_UART_STATUS_FRAMING_ERROR   (1U<<2)
+#define DAP_UART_STATUS_PARITY_ERROR    (1U<<3)
+#define DAP_UART_STATUS_TX_ENABLED      (1U<<4)
+
+// DAP UART Configure Error
+#define DAP_UART_CFG_ERROR_DATA_BITS    (1U<<0)
+#define DAP_UART_CFG_ERROR_PARITY       (1U<<1)
+#define DAP_UART_CFG_ERROR_STOP_BITS    (1U<<2)
+
+// Debug Port Register Addresses
+#define DP_IDCODE                       0x00U   // IDCODE Register (SW Read only)
+#define DP_ABORT                        0x00U   // Abort Register (SW Write only)
+#define DP_CTRL_STAT                    0x04U   // Control & Status
+#define DP_WCR                          0x04U   // Wire Control Register (SW Only)
+#define DP_SELECT                       0x08U   // Select Register (JTAG R/W & SW W)
+#define DP_RESEND                       0x08U   // Resend (SW Read Only)
+#define DP_RDBUFF                       0x0CU   // Read Buffer (Read Only)
+
+// JTAG IR Codes
+#define JTAG_ABORT                      0x08U
+#define JTAG_DPACC                      0x0AU
+#define JTAG_APACC                      0x0BU
+#define JTAG_IDCODE                     0x0EU
+#define JTAG_BYPASS                     0x0FU
+
+// JTAG Sequence Info
+#define JTAG_SEQUENCE_TCK               0x3FU   // TCK count
+#define JTAG_SEQUENCE_TMS               0x40U   // TMS value
+#define JTAG_SEQUENCE_TDO               0x80U   // TDO capture
+
+// SWD Sequence Info
+#define SWD_SEQUENCE_CLK                0x3FU   // SWCLK count
+#define SWD_SEQUENCE_DIN                0x80U   // SWDIO capture
+
+
+#include <stddef.h>
+#include <stdint.h>
+#include "cmsis_compiler.h"
+
+// DAP Data structure
+typedef struct {
+  uint8_t     debug_port;                       // Debug Port
+  uint8_t     fast_clock;                       // Fast Clock Flag
+  uint8_t     padding[2];
+  uint32_t   clock_delay;                       // Clock Delay
+  uint32_t   clock_freq;                        // Clock Frequency
+  uint32_t     timestamp;                       // Last captured Timestamp
+  struct {                                      // Transfer Configuration
+    uint8_t   idle_cycles;                      // Idle cycles after transfer
+    uint8_t    padding[3];
+    uint16_t  retry_count;                      // Number of retries after WAIT response
+    uint16_t  match_retry;                      // Number of retries if read value does not match
+    uint32_t  match_mask;                       // Match Mask
+  } transfer;
+#if (DAP_SWD != 0)
+  struct {                                      // SWD Configuration
+    uint8_t    turnaround;                      // Turnaround period
+    uint8_t    data_phase;                      // Always generate Data Phase
+  } swd_conf;
+#endif
+#if (DAP_JTAG != 0)
+  struct {                                      // JTAG Device Chain
+    uint8_t   count;                            // Number of devices
+    uint8_t   index;                            // Device index (device at TDO has index 0)
+#if (DAP_JTAG_DEV_CNT != 0)
+    uint8_t   ir_length[DAP_JTAG_DEV_CNT];      // IR Length in bits
+    uint16_t  ir_before[DAP_JTAG_DEV_CNT];      // Bits before IR
+    uint16_t  ir_after [DAP_JTAG_DEV_CNT];      // Bits after IR
+#endif
+  } jtag_dev;
+#endif
+} DAP_Data_t;
+
+extern          DAP_Data_t DAP_Data;            // DAP Data
+extern volatile uint8_t    DAP_TransferAbort;   // Transfer Abort Flag
+
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+// Functions
+extern void     SWJ_Sequence    (uint32_t count, const uint8_t *data);
+extern void     SWD_Sequence    (uint32_t info,  const uint8_t *swdo, uint8_t *swdi);
+extern void     JTAG_Sequence   (uint32_t info,  const uint8_t *tdi,  uint8_t *tdo);
+extern void     JTAG_IR         (uint32_t ir);
+extern uint32_t JTAG_ReadIDCode (void);
+extern void     JTAG_WriteAbort (uint32_t data);
+extern uint8_t  JTAG_Transfer   (uint32_t request, uint32_t *data);
+extern uint8_t  SWD_Transfer    (uint32_t request, uint32_t *data);
+
+extern void     Delayms         (uint32_t delay);
+
+extern uint32_t SWO_Transport      (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Mode           (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Baudrate       (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Control        (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Status                                 (uint8_t *response);
+extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Data           (const uint8_t *request, uint8_t *response);
+
+extern void     SWO_QueueTransfer    (uint8_t *buf, uint32_t num);
+extern void     SWO_AbortTransfer    (void);
+extern void     SWO_TransferComplete (void);
+
+extern uint32_t SWO_Mode_UART     (uint32_t enable);
+extern uint32_t SWO_Baudrate_UART (uint32_t baudrate);
+extern uint32_t SWO_Control_UART  (uint32_t active);
+extern void     SWO_Capture_UART  (uint8_t *buf, uint32_t num);
+extern uint32_t SWO_GetCount_UART (void);
+
+extern uint32_t SWO_Mode_Manchester     (uint32_t enable);
+extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate);
+extern uint32_t SWO_Control_Manchester  (uint32_t active);
+extern void     SWO_Capture_Manchester  (uint8_t *buf, uint32_t num);
+extern uint32_t SWO_GetCount_Manchester (void);
+
+extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response);
+extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response);
+extern uint32_t UART_Control   (const uint8_t *request, uint8_t *response);
+extern uint32_t UART_Status                            (uint8_t *response);
+extern uint32_t UART_Transfer  (const uint8_t *request, uint8_t *response);
+
+extern uint8_t  USB_COM_PORT_Activate (uint32_t cmd);
+
+extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response);
+extern uint32_t DAP_ProcessCommand       (const uint8_t *request, uint8_t *response);
+extern uint32_t DAP_ExecuteCommand       (const uint8_t *request, uint8_t *response);
+
+extern void     DAP_Setup (void);
+
+// Configurable delay for clock generation
+#ifndef DELAY_SLOW_CYCLES
+#define DELAY_SLOW_CYCLES       3U      // Number of cycles for one iteration
+#endif
+#if defined(__CC_ARM)
+__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
+  uint32_t count = delay;
+  while (--count);
+}
+#else
+__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
+  __ASM volatile (
+  ".syntax unified\n"
+  "0:\n\t"
+    "subs %0,%0,#1\n\t"
+    "bne  0b\n"
+  : "+l" (delay) : : "cc"
+  );
+}
+#endif
+
+// Fixed delay for fast clock generation
+#ifndef DELAY_FAST_CYCLES
+#define DELAY_FAST_CYCLES       0U      // Number of cycles: 0..3
+#endif
+__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) {
+#if (DELAY_FAST_CYCLES >= 1U)
+  __NOP();
+#endif
+#if (DELAY_FAST_CYCLES >= 2U)
+  __NOP();
+#endif
+#if (DELAY_FAST_CYCLES >= 3U)
+  __NOP();
+#endif
+}
+
+#ifdef  __cplusplus
+}
+#endif
+
+
+#endif  /* __DAP_H__ */

CMSIS-DAP/Firmware/Source/DAP_vendor.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. December 2017
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        DAP_vendor.c CMSIS-DAP Vendor Commands
+ *
+ *---------------------------------------------------------------------------*/
+ 
+#include "DAP_config.h"
+#include "DAP.h"
+
+//**************************************************************************************************
+/** 
+\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands
+\ingroup DAP_Vendor_gr 
+@{
+
+The file DAP_vendor.c provides template source code for extension of a Debug Unit with 
+Vendor Commands. Copy this file to the project folder of the Debug Unit and add the 
+file to the MDK-ARM project under the file group Configuration.
+*/
+
+/** Process DAP Vendor Command and prepare Response Data
+\param request   pointer to request data
+\param response  pointer to response data
+\return          number of bytes in response (lower 16 bits)
+                 number of bytes in request (upper 16 bits)
+*/
+__WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
+  uint32_t num = (1U << 16) | 1U;
+
+  *response++ = *request;        // copy Command ID
+
+  switch (*request++) {          // first byte in request is Command ID
+    case ID_DAP_Vendor0:
+#if 0                            // example user command
+      num += 1U << 16;           // increment request count
+      if (*request == 1U) {      // when first command data byte is 1
+        *response++ = 'X';       // send 'X' as response
+        num++;                   // increment response count
+      }
+#endif
+      break;
+
+    case ID_DAP_Vendor1:  break;
+    case ID_DAP_Vendor2:  break;
+    case ID_DAP_Vendor3:  break;
+    case ID_DAP_Vendor4:  break;
+    case ID_DAP_Vendor5:  break;
+    case ID_DAP_Vendor6:  break;
+    case ID_DAP_Vendor7:  break;
+    case ID_DAP_Vendor8:  break;
+    case ID_DAP_Vendor9:  break;
+    case ID_DAP_Vendor10: break;
+    case ID_DAP_Vendor11: break;
+    case ID_DAP_Vendor12: break;
+    case ID_DAP_Vendor13: break;
+    case ID_DAP_Vendor14: break;
+    case ID_DAP_Vendor15: break;
+    case ID_DAP_Vendor16: break;
+    case ID_DAP_Vendor17: break;
+    case ID_DAP_Vendor18: break;
+    case ID_DAP_Vendor19: break;
+    case ID_DAP_Vendor20: break;
+    case ID_DAP_Vendor21: break;
+    case ID_DAP_Vendor22: break;
+    case ID_DAP_Vendor23: break;
+    case ID_DAP_Vendor24: break;
+    case ID_DAP_Vendor25: break;
+    case ID_DAP_Vendor26: break;
+    case ID_DAP_Vendor27: break;
+    case ID_DAP_Vendor28: break;
+    case ID_DAP_Vendor29: break;
+    case ID_DAP_Vendor30: break;
+    case ID_DAP_Vendor31: break;
+  }
+
+  return (num);
+}
+
+///@}

CMSIS-DAP/Firmware/Source/JTAG_DP.c

@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. December 2017
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        JTAG_DP.c CMSIS-DAP JTAG DP I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+
+// JTAG Macros
+
+#define PIN_TCK_SET PIN_SWCLK_TCK_SET
+#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR
+#define PIN_TMS_SET PIN_SWDIO_TMS_SET
+#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR
+
+#define JTAG_CYCLE_TCK()                \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define JTAG_CYCLE_TDI(tdi)             \
+  PIN_TDI_OUT(tdi);                     \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define JTAG_CYCLE_TDO(tdo)             \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  tdo = PIN_TDO_IN();                   \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define JTAG_CYCLE_TDIO(tdi,tdo)        \
+  PIN_TDI_OUT(tdi);                     \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  tdo = PIN_TDO_IN();                   \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+
+
+#if (DAP_JTAG != 0)
+
+
+// Generate JTAG Sequence
+//   info:   sequence information
+//   tdi:    pointer to TDI generated data
+//   tdo:    pointer to TDO captured data
+//   return: none
+__WEAK void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) {
+  uint32_t i_val;
+  uint32_t o_val;
+  uint32_t bit;
+  uint32_t n, k;
+
+  n = info & JTAG_SEQUENCE_TCK;
+  if (n == 0U) {
+    n = 64U;
+  }
+
+  if (info & JTAG_SEQUENCE_TMS) {
+    PIN_TMS_SET();
+  } else {
+    PIN_TMS_CLR();
+  }
+
+  while (n) {
+    i_val = *tdi++;
+    o_val = 0U;
+    for (k = 8U; k && n; k--, n--) {
+      JTAG_CYCLE_TDIO(i_val, bit);
+      i_val >>= 1;
+      o_val >>= 1;
+      o_val  |= bit << 7;
+    }
+    o_val >>= k;
+    if (info & JTAG_SEQUENCE_TDO) {
+      *tdo++ = (uint8_t)o_val;
+    }
+  }
+}
+
+
+// JTAG Set IR
+//   ir:     IR value
+//   return: none
+#define JTAG_IR_Function(speed) /**/                                            \
+static void JTAG_IR_##speed (uint32_t ir) {                                     \
+  uint32_t n;                                                                   \
+                                                                                \
+  PIN_TMS_SET();                                                                \
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */                \
+  JTAG_CYCLE_TCK();                         /* Select-IR-Scan */                \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Capture-IR */                    \
+  JTAG_CYCLE_TCK();                         /* Shift-IR */                      \
+                                                                                \
+  PIN_TDI_OUT(1U);                                                              \
+  for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) {      \
+    JTAG_CYCLE_TCK();                       /* Bypass before data */            \
+  }                                                                             \
+  for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \
+    JTAG_CYCLE_TDI(ir);                     /* Set IR bits (except last) */     \
+    ir >>= 1;                                                                   \
+  }                                                                             \
+  n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index];                      \
+  if (n) {                                                                      \
+    JTAG_CYCLE_TDI(ir);                     /* Set last IR bit */               \
+    PIN_TDI_OUT(1U);                                                            \
+    for (--n; n; n--) {                                                         \
+      JTAG_CYCLE_TCK();                     /* Bypass after data */             \
+    }                                                                           \
+    PIN_TMS_SET();                                                              \
+    JTAG_CYCLE_TCK();                       /* Bypass & Exit1-IR */             \
+  } else {                                                                      \
+    PIN_TMS_SET();                                                              \
+    JTAG_CYCLE_TDI(ir);                     /* Set last IR bit & Exit1-IR */    \
+  }                                                                             \
+                                                                                \
+  JTAG_CYCLE_TCK();                         /* Update-IR */                     \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Idle */                          \
+  PIN_TDI_OUT(1U);                                                              \
+}
+
+
+// JTAG Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+#define JTAG_TransferFunction(speed)        /**/                                \
+static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) {        \
+  uint32_t ack;                                                                 \
+  uint32_t bit;                                                                 \
+  uint32_t val;                                                                 \
+  uint32_t n;                                                                   \
+                                                                                \
+  PIN_TMS_SET();                                                                \
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */                \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Capture-DR */                    \
+  JTAG_CYCLE_TCK();                         /* Shift-DR */                      \
+                                                                                \
+  for (n = DAP_Data.jtag_dev.index; n; n--) {                                   \
+    JTAG_CYCLE_TCK();                       /* Bypass before data */            \
+  }                                                                             \
+                                                                                \
+  JTAG_CYCLE_TDIO(request >> 1, bit);       /* Set RnW, Get ACK.0 */            \
+  ack  = bit << 1;                                                              \
+  JTAG_CYCLE_TDIO(request >> 2, bit);       /* Set A2,  Get ACK.1 */            \
+  ack |= bit << 0;                                                              \
+  JTAG_CYCLE_TDIO(request >> 3, bit);       /* Set A3,  Get ACK.2 */            \
+  ack |= bit << 2;                                                              \
+                                                                                \
+  if (ack != DAP_TRANSFER_OK) {                                                 \
+    /* Exit on error */                                                         \
+    PIN_TMS_SET();                                                              \
+    JTAG_CYCLE_TCK();                       /* Exit1-DR */                      \
+    goto exit;                                                                  \
+  }                                                                             \
+                                                                                \
+  if (request & DAP_TRANSFER_RnW) {                                             \
+    /* Read Transfer */                                                         \
+    val = 0U;                                                                   \
+    for (n = 31U; n; n--) {                                                     \
+      JTAG_CYCLE_TDO(bit);                  /* Get D0..D30 */                   \
+      val  |= bit << 31;                                                        \
+      val >>= 1;                                                                \
+    }                                                                           \
+    n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;                 \
+    if (n) {                                                                    \
+      JTAG_CYCLE_TDO(bit);                  /* Get D31 */                       \
+      for (--n; n; n--) {                                                       \
+        JTAG_CYCLE_TCK();                   /* Bypass after data */             \
+      }                                                                         \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TCK();                     /* Bypass & Exit1-DR */             \
+    } else {                                                                    \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TDO(bit);                  /* Get D31 & Exit1-DR */            \
+    }                                                                           \
+    val |= bit << 31;                                                           \
+    if (data) { *data = val; }                                                  \
+  } else {                                                                      \
+    /* Write Transfer */                                                        \
+    val = *data;                                                                \
+    for (n = 31U; n; n--) {                                                     \
+      JTAG_CYCLE_TDI(val);                  /* Set D0..D30 */                   \
+      val >>= 1;                                                                \
+    }                                                                           \
+    n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;                 \
+    if (n) {                                                                    \
+      JTAG_CYCLE_TDI(val);                  /* Set D31 */                       \
+      for (--n; n; n--) {                                                       \
+        JTAG_CYCLE_TCK();                   /* Bypass after data */             \
+      }                                                                         \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TCK();                     /* Bypass & Exit1-DR */             \
+    } else {                                                                    \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TDI(val);                  /* Set D31 & Exit1-DR */            \
+    }                                                                           \
+  }                                                                             \
+                                                                                \
+exit:                                                                           \
+  JTAG_CYCLE_TCK();                         /* Update-DR */                     \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Idle */                          \
+  PIN_TDI_OUT(1U);                                                              \
+                                                                                \
+  /* Capture Timestamp */                                                       \
+  if (request & DAP_TRANSFER_TIMESTAMP) {                                       \
+    DAP_Data.timestamp = TIMESTAMP_GET();                                       \
+  }                                                                             \
+                                                                                \
+  /* Idle cycles */                                                             \
+  n = DAP_Data.transfer.idle_cycles;                                            \
+  while (n--) {                                                                 \
+    JTAG_CYCLE_TCK();                       /* Idle */                          \
+  }                                                                             \
+                                                                                \
+  return ((uint8_t)ack);                                                        \
+}
+
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_FAST()
+JTAG_IR_Function(Fast)
+JTAG_TransferFunction(Fast)
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+JTAG_IR_Function(Slow)
+JTAG_TransferFunction(Slow)
+
+
+// JTAG Read IDCODE register
+//   return: value read
+__WEAK uint32_t JTAG_ReadIDCode (void) {
+  uint32_t bit;
+  uint32_t val;
+  uint32_t n;
+
+  PIN_TMS_SET();
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Capture-DR */
+  JTAG_CYCLE_TCK();                         /* Shift-DR */
+
+  for (n = DAP_Data.jtag_dev.index; n; n--) {
+    JTAG_CYCLE_TCK();                       /* Bypass before data */
+  }
+
+  val = 0U;
+  for (n = 31U; n; n--) {
+    JTAG_CYCLE_TDO(bit);                    /* Get D0..D30 */
+    val  |= bit << 31;
+    val >>= 1;
+  }
+  PIN_TMS_SET();
+  JTAG_CYCLE_TDO(bit);                      /* Get D31 & Exit1-DR */
+  val |= bit << 31;
+
+  JTAG_CYCLE_TCK();                         /* Update-DR */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Idle */
+
+  return (val);
+}
+
+
+// JTAG Write ABORT register
+//   data:   value to write
+//   return: none
+__WEAK void JTAG_WriteAbort (uint32_t data) {
+  uint32_t n;
+
+  PIN_TMS_SET();
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Capture-DR */
+  JTAG_CYCLE_TCK();                         /* Shift-DR */
+
+  for (n = DAP_Data.jtag_dev.index; n; n--) {
+    JTAG_CYCLE_TCK();                       /* Bypass before data */
+  }
+
+  PIN_TDI_OUT(0U);
+  JTAG_CYCLE_TCK();                         /* Set RnW=0 (Write) */
+  JTAG_CYCLE_TCK();                         /* Set A2=0 */
+  JTAG_CYCLE_TCK();                         /* Set A3=0 */
+
+  for (n = 31U; n; n--) {
+    JTAG_CYCLE_TDI(data);                   /* Set D0..D30 */
+    data >>= 1;
+  }
+  n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;
+  if (n) {
+    JTAG_CYCLE_TDI(data);                   /* Set D31 */
+    for (--n; n; n--) {
+      JTAG_CYCLE_TCK();                     /* Bypass after data */
+    }
+    PIN_TMS_SET();
+    JTAG_CYCLE_TCK();                       /* Bypass & Exit1-DR */
+  } else {
+    PIN_TMS_SET();
+    JTAG_CYCLE_TDI(data);                   /* Set D31 & Exit1-DR */
+  }
+
+  JTAG_CYCLE_TCK();                         /* Update-DR */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Idle */
+  PIN_TDI_OUT(1U);
+}
+
+
+// JTAG Set IR
+//   ir:     IR value
+//   return: none
+__WEAK void JTAG_IR (uint32_t ir) {
+  if (DAP_Data.fast_clock) {
+    JTAG_IR_Fast(ir);
+  } else {
+    JTAG_IR_Slow(ir);
+  }
+}
+
+
+// JTAG Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+__WEAK uint8_t  JTAG_Transfer(uint32_t request, uint32_t *data) {
+  if (DAP_Data.fast_clock) {
+    return JTAG_TransferFast(request, data);
+  } else {
+    return JTAG_TransferSlow(request, data);
+  }
+}
+
+
+#endif  /* (DAP_JTAG != 0) */

CMSIS-DAP/Firmware/Source/SWO.c

@@ -0,0 +1,804 @@
+/*
+ * Copyright (c) 2013-2021 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        29. March 2021
+ * $Revision:    V2.0.1
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        SWO.c CMSIS-DAP SWO I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+#if (SWO_UART != 0)
+#include "Driver_USART.h"
+#endif
+#if (SWO_STREAM != 0)
+#include "cmsis_os2.h"
+#define   osObjectsExternal
+#include "osObjects.h"
+#endif
+
+#if (SWO_STREAM != 0)
+#ifdef DAP_FW_V1
+#error "SWO Streaming Trace not supported in DAP V1!"
+#endif
+#endif
+
+#if (SWO_UART != 0)
+
+// USART Driver
+#define _USART_Driver_(n)  Driver_USART##n
+#define  USART_Driver_(n) _USART_Driver_(n)
+extern ARM_DRIVER_USART    USART_Driver_(SWO_UART_DRIVER);
+#define pUSART           (&USART_Driver_(SWO_UART_DRIVER))
+
+static uint8_t USART_Ready = 0U;
+
+#endif  /* (SWO_UART != 0) */
+
+
+#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
+
+
+#define SWO_STREAM_TIMEOUT      50U     /* Stream timeout in ms */
+
+#define USB_BLOCK_SIZE          512U    /* USB Block Size */
+#define TRACE_BLOCK_SIZE        64U     /* Trace Block Size (2^n: 32...512) */
+
+// Trace State
+static uint8_t  TraceTransport =  0U;       /* Trace Transport */
+static uint8_t  TraceMode      =  0U;       /* Trace Mode */
+static uint8_t  TraceStatus    =  0U;       /* Trace Status without Errors */
+static uint8_t  TraceError[2]  = {0U, 0U};  /* Trace Error flags (banked) */
+static uint8_t  TraceError_n   =  0U;       /* Active Trace Error bank */
+
+// Trace Buffer
+static uint8_t  TraceBuf[SWO_BUFFER_SIZE];  /* Trace Buffer (must be 2^n) */
+static volatile uint32_t TraceIndexI  = 0U; /* Incoming Trace Index */
+static volatile uint32_t TraceIndexO  = 0U; /* Outgoing Trace Index */
+static volatile uint8_t  TraceUpdate;       /* Trace Update Flag */
+static          uint32_t TraceBlockSize;    /* Current Trace Block Size */
+
+#if (TIMESTAMP_CLOCK != 0U) 
+// Trace Timestamp
+static volatile struct {
+  uint32_t index;
+  uint32_t tick;
+} TraceTimestamp;
+#endif
+
+// Trace Helper functions
+static void     ClearTrace     (void);
+static void     ResumeTrace    (void);
+static uint32_t GetTraceCount  (void);
+static uint8_t  GetTraceStatus (void);
+static void     SetTraceError  (uint8_t flag);
+
+#if (SWO_STREAM != 0)
+extern osThreadId_t      SWO_ThreadId;
+static volatile uint8_t  TransferBusy = 0U; /* Transfer Busy Flag */
+static          uint32_t TransferSize;      /* Current Transfer Size */
+#endif
+
+
+#if (SWO_UART != 0)
+
+// USART Driver Callback function
+//   event: event mask
+static void USART_Callback (uint32_t event) {
+  uint32_t index_i;
+  uint32_t index_o;
+  uint32_t count;
+  uint32_t num;
+
+  if (event &  ARM_USART_EVENT_RECEIVE_COMPLETE) {
+#if (TIMESTAMP_CLOCK != 0U) 
+    TraceTimestamp.tick = TIMESTAMP_GET();
+#endif
+    index_o  = TraceIndexO;
+    index_i  = TraceIndexI;
+    index_i += TraceBlockSize;
+    TraceIndexI = index_i;
+#if (TIMESTAMP_CLOCK != 0U) 
+    TraceTimestamp.index = index_i;
+#endif
+    num   = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U));
+    count = index_i - index_o;
+    if (count <= (SWO_BUFFER_SIZE - num)) {
+      index_i &= SWO_BUFFER_SIZE - 1U;
+      TraceBlockSize = num;
+      pUSART->Receive(&TraceBuf[index_i], num);
+    } else {
+      TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
+    }
+    TraceUpdate = 1U;
+#if (SWO_STREAM != 0)
+    if (TraceTransport == 2U) {
+      if (count >= (USB_BLOCK_SIZE - (index_o & (USB_BLOCK_SIZE - 1U)))) {
+        osThreadFlagsSet(SWO_ThreadId, 1U);
+      }
+    }
+#endif
+  }
+  if (event &  ARM_USART_EVENT_RX_OVERFLOW) {
+    SetTraceError(DAP_SWO_BUFFER_OVERRUN);
+  }
+  if (event & (ARM_USART_EVENT_RX_BREAK         |
+               ARM_USART_EVENT_RX_FRAMING_ERROR |
+               ARM_USART_EVENT_RX_PARITY_ERROR)) {
+    SetTraceError(DAP_SWO_STREAM_ERROR);
+  }
+}
+
+// Enable or disable SWO Mode (UART)
+//   enable: enable flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t SWO_Mode_UART (uint32_t enable) {
+  int32_t status;
+
+  USART_Ready = 0U;
+
+  if (enable != 0U) {
+    status = pUSART->Initialize(USART_Callback);
+    if (status != ARM_DRIVER_OK) {
+      return (0U);
+    }
+    status = pUSART->PowerControl(ARM_POWER_FULL);
+    if (status != ARM_DRIVER_OK) {
+      pUSART->Uninitialize();
+      return (0U);
+    }
+  } else {
+    pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+    pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+    pUSART->PowerControl(ARM_POWER_OFF);
+    pUSART->Uninitialize();
+  }
+  return (1U);
+}
+
+// Configure SWO Baudrate (UART)
+//   baudrate: requested baudrate
+//   return:   actual baudrate or 0 when not configured
+__WEAK uint32_t SWO_Baudrate_UART (uint32_t baudrate) {
+  int32_t  status;
+  uint32_t index;
+  uint32_t num;
+
+  if (baudrate > SWO_UART_MAX_BAUDRATE) {
+    baudrate = SWO_UART_MAX_BAUDRATE;
+  }
+
+  if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+    pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+    if (pUSART->GetStatus().rx_busy) {
+      TraceIndexI += pUSART->GetRxCount();
+      pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+    }
+  }
+
+  status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS |
+                           ARM_USART_DATA_BITS_8       |
+                           ARM_USART_PARITY_NONE       |
+                           ARM_USART_STOP_BITS_1,
+                           baudrate);
+
+  if (status == ARM_DRIVER_OK) {
+    USART_Ready = 1U;
+  } else {
+    USART_Ready = 0U;
+    return (0U);
+  }
+
+  if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+    if ((TraceStatus & DAP_SWO_CAPTURE_PAUSED) == 0U) {
+      index = TraceIndexI & (SWO_BUFFER_SIZE - 1U);
+      num = TRACE_BLOCK_SIZE - (index & (TRACE_BLOCK_SIZE - 1U));
+      TraceBlockSize = num;
+      pUSART->Receive(&TraceBuf[index], num);
+    }
+    pUSART->Control(ARM_USART_CONTROL_RX, 1U);
+  }
+
+  return (baudrate);
+}
+
+// Control SWO Capture (UART)
+//   active: active flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t SWO_Control_UART (uint32_t active) {
+  int32_t status;
+
+  if (active) {
+    if (!USART_Ready) { 
+      return (0U);
+    }
+    TraceBlockSize = 1U;
+    status = pUSART->Receive(&TraceBuf[0], 1U);
+    if (status != ARM_DRIVER_OK) {
+      return (0U);
+    }
+    status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
+    if (status != ARM_DRIVER_OK) {
+      return (0U);
+    }
+  } else {
+    pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+    if (pUSART->GetStatus().rx_busy) {
+      TraceIndexI += pUSART->GetRxCount();
+      pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+    }
+  }
+  return (1U);
+}
+
+// Start SWO Capture (UART)
+//   buf: pointer to buffer for capturing
+//   num: number of bytes to capture
+__WEAK void SWO_Capture_UART (uint8_t *buf, uint32_t num) {
+  TraceBlockSize = num;
+  pUSART->Receive(buf, num);
+}
+
+// Get SWO Pending Trace Count (UART)
+//   return: number of pending trace data bytes
+__WEAK uint32_t SWO_GetCount_UART (void) {
+  uint32_t count;
+
+  if (pUSART->GetStatus().rx_busy) {
+    count = pUSART->GetRxCount();
+  } else {
+    count = 0U;
+  }
+  return (count);
+}
+
+#endif  /* (SWO_UART != 0) */
+
+
+#if (SWO_MANCHESTER != 0)
+
+// Enable or disable SWO Mode (Manchester)
+//   enable: enable flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t SWO_Mode_Manchester (uint32_t enable) {
+  (void) enable;
+  return (0U);
+}
+
+// Configure SWO Baudrate (Manchester)
+//   baudrate: requested baudrate
+//   return:   actual baudrate or 0 when not configured
+__WEAK uint32_t SWO_Baudrate_Manchester (uint32_t baudrate) {
+  (void) baudrate;
+  return (0U);
+}
+
+// Control SWO Capture (Manchester)
+//   active: active flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t SWO_Control_Manchester (uint32_t active) {
+  (void) active;
+  return (0U);
+}
+
+// Start SWO Capture (Manchester)
+//   buf: pointer to buffer for capturing
+//   num: number of bytes to capture
+__WEAK void SWO_Capture_Manchester (uint8_t *buf, uint32_t num) {
+  (void) buf;
+  (void) num;
+}
+
+// Get SWO Pending Trace Count (Manchester)
+//   return: number of pending trace data bytes
+__WEAK uint32_t SWO_GetCount_Manchester (void) {
+  return (0U);
+}
+
+#endif  /* (SWO_MANCHESTER != 0) */
+
+
+// Clear Trace Errors and Data
+static void ClearTrace (void) {
+
+#if (SWO_STREAM != 0)
+  if (TraceTransport == 2U) {
+    if (TransferBusy != 0U) {
+      SWO_AbortTransfer();
+      TransferBusy = 0U;
+    }
+  }
+#endif
+
+  TraceError[0] = 0U;
+  TraceError[1] = 0U;
+  TraceError_n  = 0U;
+  TraceIndexI   = 0U;
+  TraceIndexO   = 0U;
+
+#if (TIMESTAMP_CLOCK != 0U) 
+  TraceTimestamp.index = 0U;
+  TraceTimestamp.tick  = 0U;
+#endif
+}
+
+// Resume Trace Capture
+static void ResumeTrace (void) {
+  uint32_t index_i;
+  uint32_t index_o;
+
+  if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) {
+    index_i = TraceIndexI;
+    index_o = TraceIndexO;
+    if ((index_i - index_o) < SWO_BUFFER_SIZE) {
+      index_i &= SWO_BUFFER_SIZE - 1U;
+      switch (TraceMode) {
+#if (SWO_UART != 0)
+        case DAP_SWO_UART:
+          TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
+          SWO_Capture_UART(&TraceBuf[index_i], 1U);
+          break;
+#endif
+#if (SWO_MANCHESTER != 0)
+        case DAP_SWO_MANCHESTER:
+          TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
+          SWO_Capture_Manchester(&TraceBuf[index_i], 1U);
+          break;
+#endif
+        default:
+          break;
+      }
+    }
+  }
+}
+
+// Get Trace Count
+//   return: number of available data bytes in trace buffer
+static uint32_t GetTraceCount (void) {
+  uint32_t count;
+
+  if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
+    do {
+      TraceUpdate = 0U;
+      count = TraceIndexI - TraceIndexO;
+      switch (TraceMode) {
+#if (SWO_UART != 0)
+        case DAP_SWO_UART:
+          count += SWO_GetCount_UART();
+          break;
+#endif
+#if (SWO_MANCHESTER != 0)
+        case DAP_SWO_MANCHESTER:
+          count += SWO_GetCount_Manchester();
+          break;
+#endif
+        default:
+          break;
+      }
+    } while (TraceUpdate != 0U);
+  } else {
+    count = TraceIndexI - TraceIndexO;
+  }
+
+  return (count);
+}
+
+// Get Trace Status (clear Error flags)
+//   return: Trace Status (Active flag and Error flags)
+static uint8_t GetTraceStatus (void) {
+  uint8_t  status;
+  uint32_t n;
+
+  n = TraceError_n;
+  TraceError_n ^= 1U;
+  status = TraceStatus | TraceError[n];
+  TraceError[n] = 0U;
+
+  return (status);
+}
+
+// Set Trace Error flag(s)
+//   flag:  error flag(s) to set
+static void SetTraceError (uint8_t flag) {
+  TraceError[TraceError_n] |= flag;
+}
+
+
+// Process SWO Transport command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) {
+  uint8_t  transport;
+  uint32_t result;
+
+  if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) == 0U) {
+    transport = *request;
+    switch (transport) {
+      case 0U:
+      case 1U:
+#if (SWO_STREAM != 0)
+      case 2U:
+#endif
+        TraceTransport = transport;
+        result = 1U;
+        break;
+      default:
+        result = 0U;
+        break;
+    }
+  } else {
+    result = 0U;
+  }
+
+  if (result != 0U) {
+    *response = DAP_OK;
+  } else {
+    *response = DAP_ERROR;
+  }
+
+  return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Mode command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
+  uint8_t  mode;
+  uint32_t result;
+
+  mode = *request;
+
+  switch (TraceMode) {
+#if (SWO_UART != 0)
+    case DAP_SWO_UART:
+      SWO_Mode_UART(0U);
+      break;
+#endif
+#if (SWO_MANCHESTER != 0)
+    case DAP_SWO_MANCHESTER:
+      SWO_Mode_Manchester(0U);
+      break;
+#endif
+    default:
+      break;
+  }
+
+  switch (mode) {
+    case DAP_SWO_OFF:
+      result = 1U;
+      break;
+#if (SWO_UART != 0)
+    case DAP_SWO_UART:
+      result = SWO_Mode_UART(1U);
+      break;
+#endif
+#if (SWO_MANCHESTER != 0)
+    case DAP_SWO_MANCHESTER:
+      result = SWO_Mode_Manchester(1U);
+      break;
+#endif
+    default:
+      result = 0U;
+      break;
+  }
+  if (result != 0U) {
+    TraceMode = mode;
+  } else {
+    TraceMode = DAP_SWO_OFF;
+  }
+
+  TraceStatus = 0U;
+
+  if (result != 0U) {
+    *response = DAP_OK;
+  } else {
+    *response = DAP_ERROR;
+  }
+
+  return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Baudrate command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) {
+  uint32_t baudrate;
+
+  baudrate = (uint32_t)(*(request+0) <<  0) |
+             (uint32_t)(*(request+1) <<  8) |
+             (uint32_t)(*(request+2) << 16) |
+             (uint32_t)(*(request+3) << 24);
+
+  switch (TraceMode) {
+#if (SWO_UART != 0)
+    case DAP_SWO_UART:
+      baudrate = SWO_Baudrate_UART(baudrate);
+      break;
+#endif
+#if (SWO_MANCHESTER != 0)
+    case DAP_SWO_MANCHESTER:
+      baudrate = SWO_Baudrate_Manchester(baudrate);
+      break;
+#endif
+    default:
+      baudrate = 0U;
+      break;
+  }
+
+  if (baudrate == 0U) {
+    TraceStatus = 0U;
+  }
+
+  *response++ = (uint8_t)(baudrate >>  0);
+  *response++ = (uint8_t)(baudrate >>  8);
+  *response++ = (uint8_t)(baudrate >> 16);
+  *response   = (uint8_t)(baudrate >> 24);
+
+  return ((4U << 16) | 4U);
+}
+
+
+// Process SWO Control command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Control (const uint8_t *request, uint8_t *response) {
+  uint8_t  active;
+  uint32_t result;
+
+  active = *request & DAP_SWO_CAPTURE_ACTIVE;
+
+  if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
+    if (active) {
+      ClearTrace();
+    }
+    switch (TraceMode) {
+#if (SWO_UART != 0)
+      case DAP_SWO_UART:
+        result = SWO_Control_UART(active);
+        break;
+#endif
+#if (SWO_MANCHESTER != 0)
+      case DAP_SWO_MANCHESTER:
+        result = SWO_Control_Manchester(active);
+        break;
+#endif
+      default:
+        result = 0U;
+        break;
+    }
+    if (result != 0U) {
+      TraceStatus = active;
+#if (SWO_STREAM != 0)
+      if (TraceTransport == 2U) {
+        osThreadFlagsSet(SWO_ThreadId, 1U);
+      }
+#endif
+    }
+  } else {
+    result = 1U;
+  }
+
+  if (result != 0U) {
+    *response = DAP_OK;
+  } else {
+    *response = DAP_ERROR;
+  }
+
+  return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Status command and prepare response
+//   response: pointer to response data
+//   return:   number of bytes in response
+uint32_t SWO_Status (uint8_t *response) {
+  uint8_t  status;
+  uint32_t count;
+
+  status = GetTraceStatus();
+  count  = GetTraceCount();
+
+  *response++ = status;
+  *response++ = (uint8_t)(count >>  0);
+  *response++ = (uint8_t)(count >>  8);
+  *response++ = (uint8_t)(count >> 16);
+  *response   = (uint8_t)(count >> 24);
+
+  return (5U);
+}
+
+
+// Process SWO Extended Status command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) {
+  uint8_t  cmd;
+  uint8_t  status;
+  uint32_t count;
+#if (TIMESTAMP_CLOCK != 0U) 
+  uint32_t index;
+  uint32_t tick;
+#endif
+  uint32_t num;
+
+  num = 0U;
+  cmd = *request;
+
+  if (cmd & 0x01U) {
+    status = GetTraceStatus();
+    *response++ = status;
+    num += 1U;
+  }
+
+  if (cmd & 0x02U) {
+    count = GetTraceCount();
+    *response++ = (uint8_t)(count >>  0);
+    *response++ = (uint8_t)(count >>  8);
+    *response++ = (uint8_t)(count >> 16);
+    *response++ = (uint8_t)(count >> 24);
+    num += 4U;
+  }
+
+#if (TIMESTAMP_CLOCK != 0U) 
+  if (cmd & 0x04U) {
+    do {
+      TraceUpdate = 0U;
+      index = TraceTimestamp.index;
+      tick  = TraceTimestamp.tick;
+    } while (TraceUpdate != 0U);
+    *response++ = (uint8_t)(index >>  0);
+    *response++ = (uint8_t)(index >>  8);
+    *response++ = (uint8_t)(index >> 16);
+    *response++ = (uint8_t)(index >> 24);
+    *response++ = (uint8_t)(tick  >>  0);
+    *response++ = (uint8_t)(tick  >>  8);
+    *response++ = (uint8_t)(tick  >> 16);
+    *response++ = (uint8_t)(tick  >> 24);
+    num += 4U;
+  }
+#endif
+
+  return ((1U << 16) | num);
+}
+
+
+// Process SWO Data command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Data (const uint8_t *request, uint8_t *response) {
+  uint8_t  status;
+  uint32_t count;
+  uint32_t index;
+  uint32_t n, i;
+
+  status = GetTraceStatus();
+  count  = GetTraceCount();
+
+  if (TraceTransport == 1U) {
+    n = (uint32_t)(*(request+0) << 0) |
+        (uint32_t)(*(request+1) << 8);
+    if (n > (DAP_PACKET_SIZE - 4U)) {
+      n = DAP_PACKET_SIZE - 4U;
+    }
+    if (count > n) {
+      count = n;
+    }
+  } else {
+    count = 0U;
+  }
+
+  *response++ = status;
+  *response++ = (uint8_t)(count >> 0);
+  *response++ = (uint8_t)(count >> 8);
+
+  if (TraceTransport == 1U) {
+    index = TraceIndexO;
+    for (i = index, n = count; n; n--) {
+      i &= SWO_BUFFER_SIZE - 1U;
+      *response++ = TraceBuf[i++];
+    }
+    TraceIndexO = index + count;
+    ResumeTrace();
+  }
+
+  return ((2U << 16) | (3U + count));
+}
+
+
+#if (SWO_STREAM != 0)
+
+// SWO Data Transfer complete callback
+void SWO_TransferComplete (void) {
+  TraceIndexO += TransferSize;
+  TransferBusy = 0U;
+  ResumeTrace();
+  osThreadFlagsSet(SWO_ThreadId, 1U);
+}
+
+// SWO Thread
+__NO_RETURN void SWO_Thread (void *argument) {
+  uint32_t timeout;
+  uint32_t flags;
+  uint32_t count;
+  uint32_t index;
+  uint32_t i, n;
+  (void)   argument;
+
+  timeout = osWaitForever;
+
+  for (;;) {
+    flags = osThreadFlagsWait(1U, osFlagsWaitAny, timeout);
+    if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+      timeout = SWO_STREAM_TIMEOUT;
+    } else {
+      timeout = osWaitForever;
+      flags   = osFlagsErrorTimeout;
+    }
+    if (TransferBusy == 0U) {
+      count = GetTraceCount();
+      if (count != 0U) {
+        index = TraceIndexO & (SWO_BUFFER_SIZE - 1U);
+        n = SWO_BUFFER_SIZE - index;
+        if (count > n) {
+          count = n;
+        }
+        if (flags != osFlagsErrorTimeout) {
+          i = index & (USB_BLOCK_SIZE - 1U);
+          if (i == 0U) {
+            count &= ~(USB_BLOCK_SIZE - 1U);
+          } else {
+            n = USB_BLOCK_SIZE - i;
+            if (count >= n) {
+              count = n;
+            } else {
+              count = 0U;
+            }
+          }
+        }
+        if (count != 0U) {
+          TransferSize = count;
+          TransferBusy = 1U;
+          SWO_QueueTransfer(&TraceBuf[index], count);
+        }
+      }
+    }
+  }
+}
+
+#endif  /* (SWO_STREAM != 0) */
+
+
+#endif  /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */

CMSIS-DAP/Firmware/Source/SW_DP.c

@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. December 2017
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        SW_DP.c CMSIS-DAP SW DP I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+
+// SW Macros
+
+#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET
+#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR
+
+#define SW_CLOCK_CYCLE()                \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define SW_WRITE_BIT(bit)               \
+  PIN_SWDIO_OUT(bit);                   \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define SW_READ_BIT(bit)                \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  bit = PIN_SWDIO_IN();                 \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+
+
+// Generate SWJ Sequence
+//   count:  sequence bit count
+//   data:   pointer to sequence bit data
+//   return: none
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
+__WEAK void SWJ_Sequence (uint32_t count, const uint8_t *data) {
+  uint32_t val;
+  uint32_t n;
+
+  val = 0U;
+  n = 0U;
+  while (count--) {
+    if (n == 0U) {
+      val = *data++;
+      n = 8U;
+    }
+    if (val & 1U) {
+      PIN_SWDIO_TMS_SET();
+    } else {
+      PIN_SWDIO_TMS_CLR();
+    }
+    SW_CLOCK_CYCLE();
+    val >>= 1;
+    n--;
+  }
+}
+#endif
+
+
+// Generate SWD Sequence
+//   info:   sequence information
+//   swdo:   pointer to SWDIO generated data
+//   swdi:   pointer to SWDIO captured data
+//   return: none
+#if (DAP_SWD != 0)
+__WEAK void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) {
+  uint32_t val;
+  uint32_t bit;
+  uint32_t n, k;
+
+  n = info & SWD_SEQUENCE_CLK;
+  if (n == 0U) {
+    n = 64U;
+  }
+
+  if (info & SWD_SEQUENCE_DIN) {
+    while (n) {
+      val = 0U;
+      for (k = 8U; k && n; k--, n--) {
+        SW_READ_BIT(bit);
+        val >>= 1;
+        val  |= bit << 7;
+      }
+      val >>= k;
+      *swdi++ = (uint8_t)val;
+    }
+  } else {
+    while (n) {
+      val = *swdo++;
+      for (k = 8U; k && n; k--, n--) {
+        SW_WRITE_BIT(val);
+        val >>= 1;
+      }
+    }
+  }
+}
+#endif
+
+
+#if (DAP_SWD != 0)
+
+
+// SWD Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+#define SWD_TransferFunction(speed)     /**/                                    \
+static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) {         \
+  uint32_t ack;                                                                 \
+  uint32_t bit;                                                                 \
+  uint32_t val;                                                                 \
+  uint32_t parity;                                                              \
+                                                                                \
+  uint32_t n;                                                                   \
+                                                                                \
+  /* Packet Request */                                                          \
+  parity = 0U;                                                                  \
+  SW_WRITE_BIT(1U);                     /* Start Bit */                         \
+  bit = request >> 0;                                                           \
+  SW_WRITE_BIT(bit);                    /* APnDP Bit */                         \
+  parity += bit;                                                                \
+  bit = request >> 1;                                                           \
+  SW_WRITE_BIT(bit);                    /* RnW Bit */                           \
+  parity += bit;                                                                \
+  bit = request >> 2;                                                           \
+  SW_WRITE_BIT(bit);                    /* A2 Bit */                            \
+  parity += bit;                                                                \
+  bit = request >> 3;                                                           \
+  SW_WRITE_BIT(bit);                    /* A3 Bit */                            \
+  parity += bit;                                                                \
+  SW_WRITE_BIT(parity);                 /* Parity Bit */                        \
+  SW_WRITE_BIT(0U);                     /* Stop Bit */                          \
+  SW_WRITE_BIT(1U);                     /* Park Bit */                          \
+                                                                                \
+  /* Turnaround */                                                              \
+  PIN_SWDIO_OUT_DISABLE();                                                      \
+  for (n = DAP_Data.swd_conf.turnaround; n; n--) {                              \
+    SW_CLOCK_CYCLE();                                                           \
+  }                                                                             \
+                                                                                \
+  /* Acknowledge response */                                                    \
+  SW_READ_BIT(bit);                                                             \
+  ack  = bit << 0;                                                              \
+  SW_READ_BIT(bit);                                                             \
+  ack |= bit << 1;                                                              \
+  SW_READ_BIT(bit);                                                             \
+  ack |= bit << 2;                                                              \
+                                                                                \
+  if (ack == DAP_TRANSFER_OK) {         /* OK response */                       \
+    /* Data transfer */                                                         \
+    if (request & DAP_TRANSFER_RnW) {                                           \
+      /* Read data */                                                           \
+      val = 0U;                                                                 \
+      parity = 0U;                                                              \
+      for (n = 32U; n; n--) {                                                   \
+        SW_READ_BIT(bit);               /* Read RDATA[0:31] */                  \
+        parity += bit;                                                          \
+        val >>= 1;                                                              \
+        val  |= bit << 31;                                                      \
+      }                                                                         \
+      SW_READ_BIT(bit);                 /* Read Parity */                       \
+      if ((parity ^ bit) & 1U) {                                                \
+        ack = DAP_TRANSFER_ERROR;                                               \
+      }                                                                         \
+      if (data) { *data = val; }                                                \
+      /* Turnaround */                                                          \
+      for (n = DAP_Data.swd_conf.turnaround; n; n--) {                          \
+        SW_CLOCK_CYCLE();                                                       \
+      }                                                                         \
+      PIN_SWDIO_OUT_ENABLE();                                                   \
+    } else {                                                                    \
+      /* Turnaround */                                                          \
+      for (n = DAP_Data.swd_conf.turnaround; n; n--) {                          \
+        SW_CLOCK_CYCLE();                                                       \
+      }                                                                         \
+      PIN_SWDIO_OUT_ENABLE();                                                   \
+      /* Write data */                                                          \
+      val = *data;                                                              \
+      parity = 0U;                                                              \
+      for (n = 32U; n; n--) {                                                   \
+        SW_WRITE_BIT(val);              /* Write WDATA[0:31] */                 \
+        parity += val;                                                          \
+        val >>= 1;                                                              \
+      }                                                                         \
+      SW_WRITE_BIT(parity);             /* Write Parity Bit */                  \
+    }                                                                           \
+    /* Capture Timestamp */                                                     \
+    if (request & DAP_TRANSFER_TIMESTAMP) {                                     \
+      DAP_Data.timestamp = TIMESTAMP_GET();                                     \
+    }                                                                           \
+    /* Idle cycles */                                                           \
+    n = DAP_Data.transfer.idle_cycles;                                          \
+    if (n) {                                                                    \
+      PIN_SWDIO_OUT(0U);                                                        \
+      for (; n; n--) {                                                          \
+        SW_CLOCK_CYCLE();                                                       \
+      }                                                                         \
+    }                                                                           \
+    PIN_SWDIO_OUT(1U);                                                          \
+    return ((uint8_t)ack);                                                      \
+  }                                                                             \
+                                                                                \
+  if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) {              \
+    /* WAIT or FAULT response */                                                \
+    if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \
+      for (n = 32U+1U; n; n--) {                                                \
+        SW_CLOCK_CYCLE();               /* Dummy Read RDATA[0:31] + Parity */   \
+      }                                                                         \
+    }                                                                           \
+    /* Turnaround */                                                            \
+    for (n = DAP_Data.swd_conf.turnaround; n; n--) {                            \
+      SW_CLOCK_CYCLE();                                                         \
+    }                                                                           \
+    PIN_SWDIO_OUT_ENABLE();                                                     \
+    if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \
+      PIN_SWDIO_OUT(0U);                                                        \
+      for (n = 32U+1U; n; n--) {                                                \
+        SW_CLOCK_CYCLE();               /* Dummy Write WDATA[0:31] + Parity */  \
+      }                                                                         \
+    }                                                                           \
+    PIN_SWDIO_OUT(1U);                                                          \
+    return ((uint8_t)ack);                                                      \
+  }                                                                             \
+                                                                                \
+  /* Protocol error */                                                          \
+  for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) {                   \
+    SW_CLOCK_CYCLE();                   /* Back off data phase */               \
+  }                                                                             \
+  PIN_SWDIO_OUT_ENABLE();                                                       \
+  PIN_SWDIO_OUT(1U);                                                            \
+  return ((uint8_t)ack);                                                        \
+}
+
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_FAST()
+SWD_TransferFunction(Fast)
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+SWD_TransferFunction(Slow)
+
+
+// SWD Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+__WEAK uint8_t  SWD_Transfer(uint32_t request, uint32_t *data) {
+  if (DAP_Data.fast_clock) {
+    return SWD_TransferFast(request, data);
+  } else {
+    return SWD_TransferSlow(request, data);
+  }
+}
+
+
+#endif  /* (DAP_SWD != 0) */

CMSIS-DAP/Firmware/Source/UART.c

@@ -0,0 +1,652 @@
+/*
+ * Copyright (c) 2021 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. March 2021
+ * $Revision:    V1.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        UART.c CMSIS-DAP UART
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+#if (DAP_UART != 0)
+
+#ifdef DAP_FW_V1
+#error "UART Communication Port not supported in DAP V1!"
+#endif
+
+#include "Driver_USART.h"
+
+#include "cmsis_os2.h"
+#include <string.h>
+
+#define UART_RX_BLOCK_SIZE    32U   /* Uart Rx Block Size (must be 2^n) */
+
+// USART Driver
+#define _USART_Driver_(n)  Driver_USART##n
+#define  USART_Driver_(n) _USART_Driver_(n)
+extern ARM_DRIVER_USART    USART_Driver_(DAP_UART_DRIVER);
+#define pUSART           (&USART_Driver_(DAP_UART_DRIVER))
+
+// UART Configuration
+#if (DAP_UART_USB_COM_PORT != 0)
+static uint8_t  UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
+#else
+static uint8_t  UartTransport = DAP_UART_TRANSPORT_NONE;
+#endif
+
+// UART Flags
+static uint8_t  UartConfigured = 0U;
+static uint8_t  UartReceiveEnabled = 0U;
+static uint8_t  UartTransmitEnabled = 0U;
+static uint8_t  UartTransmitActive = 0U;
+
+// UART TX Buffer
+static uint8_t  UartTxBuf[DAP_UART_TX_BUFFER_SIZE];
+static volatile uint32_t UartTxIndexI = 0U;
+static volatile uint32_t UartTxIndexO = 0U;
+
+// UART RX Buffer
+static uint8_t  UartRxBuf[DAP_UART_RX_BUFFER_SIZE];
+static volatile uint32_t UartRxIndexI = 0U;
+static volatile uint32_t UartRxIndexO = 0U;
+
+// Uart Errors
+static volatile uint8_t  UartErrorRxDataLost = 0U;
+static volatile uint8_t  UartErrorFraming = 0U;
+static volatile uint8_t  UartErrorParity = 0U;
+
+// UART Transmit
+static uint32_t UartTxNum = 0U;
+
+// Function prototypes
+static uint8_t  UART_Init (void);
+static void     UART_Uninit (void);
+static uint8_t  UART_Get_Status (void);
+static uint8_t  UART_Receive_Enable (void);
+static uint8_t  UART_Transmit_Enable (void);
+static void     UART_Receive_Disable (void);
+static void     UART_Transmit_Disable (void);
+static void     UART_Receive_Flush (void);
+static void     UART_Transmit_Flush (void);
+static void     UART_Receive (void);
+static void     UART_Transmit (void);
+
+
+// USART Driver Callback function
+//   event: event mask
+static void USART_Callback (uint32_t event) {
+  if (event &  ARM_USART_EVENT_SEND_COMPLETE) {
+    UartTxIndexO += UartTxNum;
+    UartTransmitActive = 0U;
+    UART_Transmit();
+  }
+  if (event &  ARM_USART_EVENT_RECEIVE_COMPLETE) {
+    UartRxIndexI += UART_RX_BLOCK_SIZE;
+    UART_Receive();
+  }
+  if (event &  ARM_USART_EVENT_RX_OVERFLOW) {
+    UartErrorRxDataLost = 1U;
+  }
+  if (event &  ARM_USART_EVENT_RX_FRAMING_ERROR) {
+    UartErrorFraming = 1U;
+  }
+  if (event &  ARM_USART_EVENT_RX_PARITY_ERROR) {
+    UartErrorParity = 1U;
+  }
+}
+
+// Init UART
+//   return: DAP_OK or DAP_ERROR
+static uint8_t UART_Init (void) {
+  int32_t status;
+  uint8_t ret = DAP_ERROR;
+
+  UartConfigured = 0U;
+  UartReceiveEnabled = 0U;
+  UartTransmitEnabled = 0U;
+  UartTransmitActive = 0U;
+  UartErrorRxDataLost = 0U;
+  UartErrorFraming = 0U;
+  UartErrorParity = 0U;
+  UartTxIndexI = 0U;
+  UartTxIndexO = 0U;
+  UartRxIndexI = 0U;
+  UartRxIndexO = 0U;
+  UartTxNum = 0U;
+
+  status = pUSART->Initialize(USART_Callback);
+  if (status == ARM_DRIVER_OK) {
+    status = pUSART->PowerControl(ARM_POWER_FULL);
+  }
+  if (status == ARM_DRIVER_OK) {
+    ret = DAP_OK;
+  }
+
+  return (ret);
+}
+
+// Un-Init UART
+static void UART_Uninit (void) {
+  UartConfigured = 0U;
+
+  pUSART->PowerControl(ARM_POWER_OFF);
+  pUSART->Uninitialize();
+}
+
+// Get UART Status
+//   return: status
+static uint8_t UART_Get_Status (void) {
+  uint8_t status = 0U;
+
+  if (UartReceiveEnabled != 0U) {
+    status |= DAP_UART_STATUS_RX_ENABLED;
+  }
+  if (UartErrorRxDataLost != 0U) {
+    UartErrorRxDataLost = 0U;
+    status |= DAP_UART_STATUS_RX_DATA_LOST;
+  }
+  if (UartErrorFraming != 0U) {
+    UartErrorFraming = 0U;
+    status |= DAP_UART_STATUS_FRAMING_ERROR;
+  }
+  if (UartErrorParity != 0U) {
+    UartErrorParity = 0U;
+    status |= DAP_UART_STATUS_PARITY_ERROR;
+  }
+  if (UartTransmitEnabled != 0U) {
+    status |= DAP_UART_STATUS_TX_ENABLED;
+  }
+
+  return (status);
+}
+
+// Enable UART Receive
+//   return: DAP_OK or DAP_ERROR
+static uint8_t UART_Receive_Enable (void) {
+  int32_t status;
+  uint8_t ret = DAP_ERROR;
+
+  if (UartReceiveEnabled == 0U) {
+    // Flush Buffers
+    UartRxIndexI = 0U;
+    UartRxIndexO = 0U;
+
+    UART_Receive();
+    status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
+    if (status == ARM_DRIVER_OK) {
+      UartReceiveEnabled = 1U;
+      ret = DAP_OK;
+    }
+  } else {
+    ret = DAP_OK;
+  }
+
+  return (ret);
+}
+
+// Enable UART Transmit
+//   return: DAP_OK or DAP_ERROR
+static uint8_t UART_Transmit_Enable (void) {
+  int32_t status;
+  uint8_t ret = DAP_ERROR;
+
+  if (UartTransmitEnabled == 0U) {
+    // Flush Buffers
+    UartTransmitActive = 0U;
+    UartTxIndexI = 0U;
+    UartTxIndexO = 0U;
+    UartTxNum = 0U;
+
+    status = pUSART->Control(ARM_USART_CONTROL_TX, 1U);
+    if (status == ARM_DRIVER_OK) {
+      UartTransmitEnabled = 1U;
+      ret = DAP_OK;
+    }
+  } else {
+    ret = DAP_OK;
+  }
+
+  return (ret);
+}
+
+// Disable UART Receive
+static void UART_Receive_Disable (void) {
+  if (UartReceiveEnabled != 0U) {
+    pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+    pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+    UartReceiveEnabled = 0U;
+  }
+}
+
+// Disable UART Transmit
+static void UART_Transmit_Disable (void) {
+  if (UartTransmitEnabled != 0U) {
+    pUSART->Control(ARM_USART_ABORT_SEND, 0U);
+    pUSART->Control(ARM_USART_CONTROL_TX, 0U);
+    UartTransmitActive = 0U;
+    UartTransmitEnabled = 0U;
+  }
+}
+
+// Flush UART Receive buffer
+static void UART_Receive_Flush (void) {
+  pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+  UartRxIndexI = 0U;
+  UartRxIndexO = 0U;
+  if (UartReceiveEnabled != 0U) {
+    UART_Receive();
+  }
+}
+
+// Flush UART Transmit buffer
+static void UART_Transmit_Flush (void) {
+  pUSART->Control(ARM_USART_ABORT_SEND, 0U);
+  UartTransmitActive = 0U;
+  UartTxIndexI = 0U;
+  UartTxIndexO = 0U;
+  UartTxNum = 0U;
+}
+
+// Receive data from target via UART
+static void UART_Receive (void) {
+  uint32_t index;
+
+  index = UartRxIndexI & (DAP_UART_RX_BUFFER_SIZE - 1U);
+  pUSART->Receive(&UartRxBuf[index], UART_RX_BLOCK_SIZE);
+}
+
+// Transmit available data to target via UART
+static void UART_Transmit (void) {
+  uint32_t count;
+  uint32_t index;
+
+  count = UartTxIndexI - UartTxIndexO;
+  index = UartTxIndexO & (DAP_UART_TX_BUFFER_SIZE - 1U);
+
+  if (count != 0U) {
+    if ((index + count) <= DAP_UART_TX_BUFFER_SIZE) {
+      UartTxNum = count;
+    } else {
+      UartTxNum = DAP_UART_TX_BUFFER_SIZE - index;
+    }
+    UartTransmitActive = 1U;
+    pUSART->Send(&UartTxBuf[index], UartTxNum);
+  }
+}
+
+// Process UART Transport command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t UART_Transport (const uint8_t *request, uint8_t *response) {
+  uint8_t  transport;
+  uint8_t  ret = DAP_ERROR;
+
+  transport = *request;
+  switch (transport) {
+    case DAP_UART_TRANSPORT_NONE:
+      switch (UartTransport) {
+        case DAP_UART_TRANSPORT_NONE:
+          ret = DAP_OK;
+          break;
+        case DAP_UART_TRANSPORT_USB_COM_PORT:
+#if (DAP_UART_USB_COM_PORT != 0)
+          USB_COM_PORT_Activate(0U);
+          UartTransport = DAP_UART_TRANSPORT_NONE;
+          ret = DAP_OK;
+#endif
+          break;
+        case DAP_UART_TRANSPORT_DAP_COMMAND:
+          UART_Receive_Disable();
+          UART_Transmit_Disable();
+          UART_Uninit();
+          UartTransport = DAP_UART_TRANSPORT_NONE;
+          ret= DAP_OK;
+          break;
+      }
+      break;
+    case DAP_UART_TRANSPORT_USB_COM_PORT:
+      switch (UartTransport) {
+        case DAP_UART_TRANSPORT_NONE:
+#if (DAP_UART_USB_COM_PORT != 0)
+          if (USB_COM_PORT_Activate(1U) == 0U) {
+            UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
+            ret = DAP_OK;
+          }
+#endif
+          break;
+        case DAP_UART_TRANSPORT_USB_COM_PORT:
+          ret = DAP_OK;
+          break;
+        case DAP_UART_TRANSPORT_DAP_COMMAND:
+          UART_Receive_Disable();
+          UART_Transmit_Disable();
+          UART_Uninit();
+          UartTransport = DAP_UART_TRANSPORT_NONE;
+#if (DAP_UART_USB_COM_PORT != 0)
+          if (USB_COM_PORT_Activate(1U) == 0U) {
+            UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
+            ret = DAP_OK;
+          }
+#endif
+          break;
+      }
+      break;
+    case DAP_UART_TRANSPORT_DAP_COMMAND:
+      switch (UartTransport) {
+        case DAP_UART_TRANSPORT_NONE:
+          ret = UART_Init();
+          if (ret == DAP_OK) {
+            UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND;
+          }
+          break;
+        case DAP_UART_TRANSPORT_USB_COM_PORT:
+#if (DAP_UART_USB_COM_PORT != 0)
+          USB_COM_PORT_Activate(0U);
+          UartTransport = DAP_UART_TRANSPORT_NONE;
+#endif
+          ret = UART_Init();
+          if (ret == DAP_OK) {
+            UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND;
+          }
+          break;
+        case DAP_UART_TRANSPORT_DAP_COMMAND:
+          ret = DAP_OK;
+          break;
+      }
+      break;
+    default:
+      break;
+  }
+
+  *response = ret;
+
+  return ((1U << 16) | 1U);
+}
+
+// Process UART Configure command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t UART_Configure (const uint8_t *request, uint8_t *response) {
+  uint8_t  control, status;
+  uint32_t baudrate;
+  int32_t  result;
+
+  if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
+    status = DAP_UART_CFG_ERROR_DATA_BITS |
+             DAP_UART_CFG_ERROR_PARITY    |
+             DAP_UART_CFG_ERROR_STOP_BITS;
+    baudrate = 0U;  // baudrate error
+  } else {
+
+    status   = 0U;
+    control  = *request;
+    baudrate = (uint32_t)(*(request+1) <<  0) |
+               (uint32_t)(*(request+2) <<  8) |
+               (uint32_t)(*(request+3) << 16) |
+               (uint32_t)(*(request+4) << 24);
+
+    result = pUSART->Control(control |
+                             ARM_USART_MODE_ASYNCHRONOUS |
+                             ARM_USART_FLOW_CONTROL_NONE,
+                             baudrate);
+    if (result == ARM_DRIVER_OK) {
+      UartConfigured = 1U;
+    } else {
+      UartConfigured = 0U;
+      switch (result) {
+        case ARM_USART_ERROR_BAUDRATE:
+          status = 0U;
+          baudrate = 0U;
+          break;
+        case ARM_USART_ERROR_DATA_BITS:
+          status = DAP_UART_CFG_ERROR_DATA_BITS;
+          break;
+        case ARM_USART_ERROR_PARITY:
+          status = DAP_UART_CFG_ERROR_PARITY;
+          break;
+        case ARM_USART_ERROR_STOP_BITS:
+          status = DAP_UART_CFG_ERROR_STOP_BITS;
+          break;
+        default:
+          status = DAP_UART_CFG_ERROR_DATA_BITS |
+                   DAP_UART_CFG_ERROR_PARITY    |
+                   DAP_UART_CFG_ERROR_STOP_BITS;
+          baudrate = 0U;
+          break;
+      }
+    }
+  }
+
+  *response++ = status;
+  *response++ = (uint8_t)(baudrate >>  0);
+  *response++ = (uint8_t)(baudrate >>  8);
+  *response++ = (uint8_t)(baudrate >> 16);
+  *response   = (uint8_t)(baudrate >> 24);
+
+  return ((5U << 16) | 5U);
+}
+
+// Process UART Control command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t UART_Control (const uint8_t *request, uint8_t *response) {
+  uint8_t control;
+  uint8_t result;
+  uint8_t ret = DAP_OK;
+
+  if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
+    ret = DAP_ERROR;
+  } else {
+ 
+    control = *request;
+
+    if ((control & DAP_UART_CONTROL_RX_DISABLE) != 0U) {
+      // Receive disable
+      UART_Receive_Disable();
+    } else if ((control & DAP_UART_CONTROL_RX_ENABLE) != 0U) {
+      // Receive enable
+      if (UartConfigured != 0U) {
+        result = UART_Receive_Enable();
+        if (result != DAP_OK) {
+          ret = DAP_ERROR;
+        }
+      } else {
+        ret = DAP_ERROR;
+      }
+    }
+    if ((control & DAP_UART_CONTROL_RX_BUF_FLUSH) != 0U) {
+      UART_Receive_Flush();
+    }
+
+    if ((control & DAP_UART_CONTROL_TX_DISABLE) != 0U) {
+      // Transmit disable
+      UART_Transmit_Disable();
+    } else if ((control & DAP_UART_CONTROL_TX_ENABLE) != 0U) {
+      // Transmit enable
+      if (UartConfigured != 0U) {
+        result = UART_Transmit_Enable();
+        if (result != DAP_OK) {
+          ret = DAP_ERROR;
+        }
+      } else {
+        ret = DAP_ERROR;
+      }
+    } 
+    if ((control & DAP_UART_CONTROL_TX_BUF_FLUSH) != 0U) {
+      UART_Transmit_Flush();
+    }
+  }
+
+  *response = ret;
+
+  return ((1U << 16) | 1U);
+}
+
+// Process UART Status command and prepare response
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t UART_Status (uint8_t *response) {
+  uint32_t rx_cnt, tx_cnt;
+  uint32_t cnt;
+  uint8_t  status;
+
+  if ((UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) ||
+      (UartConfigured == 0U)) {
+    rx_cnt = 0U;
+    tx_cnt = 0U;
+    status = 0U;
+  } else {
+
+    rx_cnt  = UartRxIndexI - UartRxIndexO;
+    rx_cnt += pUSART->GetRxCount();
+    if (rx_cnt > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) {
+      // Overflow
+      UartErrorRxDataLost = 1U;
+      rx_cnt = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2));
+      UartRxIndexO = UartRxIndexI - rx_cnt;
+    }
+
+    tx_cnt = UartTxIndexI - UartTxIndexO;
+    cnt = pUSART->GetTxCount();
+    if (UartTransmitActive != 0U) {
+      tx_cnt -= cnt;
+    }
+
+    status = UART_Get_Status();
+  }
+
+  *response++ = status;
+  *response++ = (uint8_t)(rx_cnt >>  0);
+  *response++ = (uint8_t)(rx_cnt >>  8);
+  *response++ = (uint8_t)(rx_cnt >> 16);
+  *response++ = (uint8_t)(rx_cnt >> 24);
+  *response++ = (uint8_t)(tx_cnt >>  0);
+  *response++ = (uint8_t)(tx_cnt >>  8);
+  *response++ = (uint8_t)(tx_cnt >> 16);
+  *response   = (uint8_t)(tx_cnt >> 24);
+
+  return ((0U << 16) | 9U);
+}
+
+// Process UART Transfer command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t UART_Transfer (const uint8_t *request, uint8_t *response) {
+  uint32_t rx_cnt, tx_cnt;
+  uint32_t rx_num, tx_num;
+  uint8_t *rx_data;
+  const
+  uint8_t *tx_data;
+  uint32_t num;
+  uint32_t index;
+  uint8_t  status;
+
+  if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
+    status = 0U;
+    rx_cnt = 0U;
+    tx_cnt = 0U;
+  } else {
+
+    // RX Data
+    rx_cnt = ((uint32_t)(*(request+0) << 0)  |
+              (uint32_t)(*(request+1) << 8));
+
+    if (rx_cnt > (DAP_PACKET_SIZE - 6U)) {
+      rx_cnt = (DAP_PACKET_SIZE - 6U);
+    }
+    rx_num  = UartRxIndexI - UartRxIndexO;
+    rx_num += pUSART->GetRxCount();
+    if (rx_num > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) {
+      // Overflow
+      UartErrorRxDataLost = 1U;
+      rx_num = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2));
+      UartRxIndexO = UartRxIndexI - rx_num;
+    }
+    if (rx_cnt > rx_num) {
+      rx_cnt = rx_num;
+    }
+
+    rx_data = (response+5);
+    index = UartRxIndexO & (DAP_UART_RX_BUFFER_SIZE - 1U);
+    if ((index + rx_cnt) <= DAP_UART_RX_BUFFER_SIZE) {
+      memcpy( rx_data,      &UartRxBuf[index], rx_cnt);
+    } else {
+      num = DAP_UART_RX_BUFFER_SIZE - index;
+      memcpy( rx_data,      &UartRxBuf[index], num);
+      memcpy(&rx_data[num], &UartRxBuf[0],     rx_cnt - num);
+    }
+    UartRxIndexO += rx_cnt;
+
+    // TX Data
+    tx_cnt  = ((uint32_t)(*(request+2) << 0) |
+               (uint32_t)(*(request+3) << 8));
+    tx_data =              (request+4);
+
+    if (tx_cnt > (DAP_PACKET_SIZE - 5U)) {
+      tx_cnt = (DAP_PACKET_SIZE - 5U);
+    }
+    tx_num = UartTxIndexI - UartTxIndexO;
+    num = pUSART->GetTxCount();
+    if (UartTransmitActive != 0U) {
+      tx_num -= num;
+    }
+    if (tx_cnt > (DAP_UART_TX_BUFFER_SIZE - tx_num)) {
+      tx_cnt = (DAP_UART_TX_BUFFER_SIZE - tx_num);
+    }
+
+    index = UartTxIndexI & (DAP_UART_TX_BUFFER_SIZE - 1U);
+    if ((index + tx_cnt) <= DAP_UART_TX_BUFFER_SIZE) {
+      memcpy(&UartTxBuf[index],  tx_data,      tx_cnt);
+    } else {
+      num = DAP_UART_TX_BUFFER_SIZE - index;
+      memcpy(&UartTxBuf[index],  tx_data,      num);
+      memcpy(&UartTxBuf[0],     &tx_data[num], tx_cnt - num);
+    }
+    UartTxIndexI += tx_cnt;
+
+    if (UartTransmitActive == 0U) {
+      UART_Transmit();
+    }
+
+    status = UART_Get_Status();
+  }
+
+  *response++ = status;
+  *response++ = (uint8_t)(tx_cnt >> 0);
+  *response++ = (uint8_t)(tx_cnt >> 8);
+  *response++ = (uint8_t)(rx_cnt >> 0);
+  *response   = (uint8_t)(rx_cnt >> 8);
+
+  return (((4U + tx_cnt) << 16) | (5U + rx_cnt));
+}
+
+#endif /* DAP_UART */

CMSIS-DAP/LICENSE.txt

@@ -0,0 +1,201 @@
+                                 Apache License
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CMSIS-DAP/RTOS2/Include/cmsis_os2.h

@@ -0,0 +1,756 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        12. June 2020
+ * $Revision:    V2.1.3
+ *
+ * Project:      CMSIS-RTOS2 API
+ * Title:        cmsis_os2.h header file
+ *
+ * Version 2.1.3
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osThreadGetId
+ * Version 2.1.2
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osKernelGetInfo, osKernelGetState
+ * Version 2.1.1
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osKernelGetTickCount, osKernelGetTickFreq
+ *    Changed Kernel Tick type to uint32_t:
+ *    - updated: osKernelGetTickCount, osDelayUntil
+ * Version 2.1.0
+ *    Support for critical and uncritical sections (nesting safe):
+ *    - updated: osKernelLock, osKernelUnlock
+ *    - added: osKernelRestoreLock
+ *    Updated Thread and Event Flags:
+ *    - changed flags parameter and return type from int32_t to uint32_t
+ * Version 2.0.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+ 
+#ifndef CMSIS_OS2_H_
+#define CMSIS_OS2_H_
+ 
+#ifndef __NO_RETURN
+#if   defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+#endif
+ 
+#include <stdint.h>
+#include <stddef.h>
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+//  ==== Enumerations, structures, defines ====
+ 
+/// Version information.
+typedef struct {
+  uint32_t                       api;   ///< API version (major.minor.rev: mmnnnrrrr dec).
+  uint32_t                    kernel;   ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
+} osVersion_t;
+ 
+/// Kernel state.
+typedef enum {
+  osKernelInactive        =  0,         ///< Inactive.
+  osKernelReady           =  1,         ///< Ready.
+  osKernelRunning         =  2,         ///< Running.
+  osKernelLocked          =  3,         ///< Locked.
+  osKernelSuspended       =  4,         ///< Suspended.
+  osKernelError           = -1,         ///< Error.
+  osKernelReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osKernelState_t;
+ 
+/// Thread state.
+typedef enum {
+  osThreadInactive        =  0,         ///< Inactive.
+  osThreadReady           =  1,         ///< Ready.
+  osThreadRunning         =  2,         ///< Running.
+  osThreadBlocked         =  3,         ///< Blocked.
+  osThreadTerminated      =  4,         ///< Terminated.
+  osThreadError           = -1,         ///< Error.
+  osThreadReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osThreadState_t;
+ 
+/// Priority values.
+typedef enum {
+  osPriorityNone          =  0,         ///< No priority (not initialized).
+  osPriorityIdle          =  1,         ///< Reserved for Idle thread.
+  osPriorityLow           =  8,         ///< Priority: low
+  osPriorityLow1          =  8+1,       ///< Priority: low + 1
+  osPriorityLow2          =  8+2,       ///< Priority: low + 2
+  osPriorityLow3          =  8+3,       ///< Priority: low + 3
+  osPriorityLow4          =  8+4,       ///< Priority: low + 4
+  osPriorityLow5          =  8+5,       ///< Priority: low + 5
+  osPriorityLow6          =  8+6,       ///< Priority: low + 6
+  osPriorityLow7          =  8+7,       ///< Priority: low + 7
+  osPriorityBelowNormal   = 16,         ///< Priority: below normal
+  osPriorityBelowNormal1  = 16+1,       ///< Priority: below normal + 1
+  osPriorityBelowNormal2  = 16+2,       ///< Priority: below normal + 2
+  osPriorityBelowNormal3  = 16+3,       ///< Priority: below normal + 3
+  osPriorityBelowNormal4  = 16+4,       ///< Priority: below normal + 4
+  osPriorityBelowNormal5  = 16+5,       ///< Priority: below normal + 5
+  osPriorityBelowNormal6  = 16+6,       ///< Priority: below normal + 6
+  osPriorityBelowNormal7  = 16+7,       ///< Priority: below normal + 7
+  osPriorityNormal        = 24,         ///< Priority: normal
+  osPriorityNormal1       = 24+1,       ///< Priority: normal + 1
+  osPriorityNormal2       = 24+2,       ///< Priority: normal + 2
+  osPriorityNormal3       = 24+3,       ///< Priority: normal + 3
+  osPriorityNormal4       = 24+4,       ///< Priority: normal + 4
+  osPriorityNormal5       = 24+5,       ///< Priority: normal + 5
+  osPriorityNormal6       = 24+6,       ///< Priority: normal + 6
+  osPriorityNormal7       = 24+7,       ///< Priority: normal + 7
+  osPriorityAboveNormal   = 32,         ///< Priority: above normal
+  osPriorityAboveNormal1  = 32+1,       ///< Priority: above normal + 1
+  osPriorityAboveNormal2  = 32+2,       ///< Priority: above normal + 2
+  osPriorityAboveNormal3  = 32+3,       ///< Priority: above normal + 3
+  osPriorityAboveNormal4  = 32+4,       ///< Priority: above normal + 4
+  osPriorityAboveNormal5  = 32+5,       ///< Priority: above normal + 5
+  osPriorityAboveNormal6  = 32+6,       ///< Priority: above normal + 6
+  osPriorityAboveNormal7  = 32+7,       ///< Priority: above normal + 7
+  osPriorityHigh          = 40,         ///< Priority: high
+  osPriorityHigh1         = 40+1,       ///< Priority: high + 1
+  osPriorityHigh2         = 40+2,       ///< Priority: high + 2
+  osPriorityHigh3         = 40+3,       ///< Priority: high + 3
+  osPriorityHigh4         = 40+4,       ///< Priority: high + 4
+  osPriorityHigh5         = 40+5,       ///< Priority: high + 5
+  osPriorityHigh6         = 40+6,       ///< Priority: high + 6
+  osPriorityHigh7         = 40+7,       ///< Priority: high + 7
+  osPriorityRealtime      = 48,         ///< Priority: realtime
+  osPriorityRealtime1     = 48+1,       ///< Priority: realtime + 1
+  osPriorityRealtime2     = 48+2,       ///< Priority: realtime + 2
+  osPriorityRealtime3     = 48+3,       ///< Priority: realtime + 3
+  osPriorityRealtime4     = 48+4,       ///< Priority: realtime + 4
+  osPriorityRealtime5     = 48+5,       ///< Priority: realtime + 5
+  osPriorityRealtime6     = 48+6,       ///< Priority: realtime + 6
+  osPriorityRealtime7     = 48+7,       ///< Priority: realtime + 7
+  osPriorityISR           = 56,         ///< Reserved for ISR deferred thread.
+  osPriorityError         = -1,         ///< System cannot determine priority or illegal priority.
+  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osPriority_t;
+ 
+/// Entry point of a thread.
+typedef void (*osThreadFunc_t) (void *argument);
+ 
+/// Timer callback function.
+typedef void (*osTimerFunc_t) (void *argument);
+ 
+/// Timer type.
+typedef enum {
+  osTimerOnce               = 0,          ///< One-shot timer.
+  osTimerPeriodic           = 1           ///< Repeating timer.
+} osTimerType_t;
+ 
+// Timeout value.
+#define osWaitForever         0xFFFFFFFFU ///< Wait forever timeout value.
+ 
+// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
+#define osFlagsWaitAny        0x00000000U ///< Wait for any flag (default).
+#define osFlagsWaitAll        0x00000001U ///< Wait for all flags.
+#define osFlagsNoClear        0x00000002U ///< Do not clear flags which have been specified to wait for.
+ 
+// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
+#define osFlagsError          0x80000000U ///< Error indicator.
+#define osFlagsErrorUnknown   0xFFFFFFFFU ///< osError (-1).
+#define osFlagsErrorTimeout   0xFFFFFFFEU ///< osErrorTimeout (-2).
+#define osFlagsErrorResource  0xFFFFFFFDU ///< osErrorResource (-3).
+#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
+#define osFlagsErrorISR       0xFFFFFFFAU ///< osErrorISR (-6).
+ 
+// Thread attributes (attr_bits in \ref osThreadAttr_t).
+#define osThreadDetached      0x00000000U ///< Thread created in detached mode (default)
+#define osThreadJoinable      0x00000001U ///< Thread created in joinable mode
+ 
+// Mutex attributes (attr_bits in \ref osMutexAttr_t).
+#define osMutexRecursive      0x00000001U ///< Recursive mutex.
+#define osMutexPrioInherit    0x00000002U ///< Priority inherit protocol.
+#define osMutexRobust         0x00000008U ///< Robust mutex.
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+  osOK                      =  0,         ///< Operation completed successfully.
+  osError                   = -1,         ///< Unspecified RTOS error: run-time error but no other error message fits.
+  osErrorTimeout            = -2,         ///< Operation not completed within the timeout period.
+  osErrorResource           = -3,         ///< Resource not available.
+  osErrorParameter          = -4,         ///< Parameter error.
+  osErrorNoMemory           = -5,         ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorISR                = -6,         ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osStatusReserved          = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osStatus_t;
+ 
+ 
+/// \details Thread ID identifies the thread.
+typedef void *osThreadId_t;
+ 
+/// \details Timer ID identifies the timer.
+typedef void *osTimerId_t;
+ 
+/// \details Event Flags ID identifies the event flags.
+typedef void *osEventFlagsId_t;
+ 
+/// \details Mutex ID identifies the mutex.
+typedef void *osMutexId_t;
+ 
+/// \details Semaphore ID identifies the semaphore.
+typedef void *osSemaphoreId_t;
+ 
+/// \details Memory Pool ID identifies the memory pool.
+typedef void *osMemoryPoolId_t;
+ 
+/// \details Message Queue ID identifies the message queue.
+typedef void *osMessageQueueId_t;
+ 
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+ 
+/// Attributes structure for thread.
+typedef struct {
+  const char                   *name;   ///< name of the thread
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                   *stack_mem;    ///< memory for stack
+  uint32_t                stack_size;   ///< size of stack
+  osPriority_t              priority;   ///< initial thread priority (default: osPriorityNormal)
+  TZ_ModuleId_t            tz_module;   ///< TrustZone module identifier
+  uint32_t                  reserved;   ///< reserved (must be 0)
+} osThreadAttr_t;
+ 
+/// Attributes structure for timer.
+typedef struct {
+  const char                   *name;   ///< name of the timer
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osTimerAttr_t;
+ 
+/// Attributes structure for event flags.
+typedef struct {
+  const char                   *name;   ///< name of the event flags
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osEventFlagsAttr_t;
+ 
+/// Attributes structure for mutex.
+typedef struct {
+  const char                   *name;   ///< name of the mutex
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osMutexAttr_t;
+ 
+/// Attributes structure for semaphore.
+typedef struct {
+  const char                   *name;   ///< name of the semaphore
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osSemaphoreAttr_t;
+ 
+/// Attributes structure for memory pool.
+typedef struct {
+  const char                   *name;   ///< name of the memory pool
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mp_mem;    ///< memory for data storage
+  uint32_t                   mp_size;   ///< size of provided memory for data storage 
+} osMemoryPoolAttr_t;
+ 
+/// Attributes structure for message queue.
+typedef struct {
+  const char                   *name;   ///< name of the message queue
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mq_mem;    ///< memory for data storage
+  uint32_t                   mq_size;   ///< size of provided memory for data storage 
+} osMessageQueueAttr_t;
+ 
+ 
+//  ==== Kernel Management Functions ====
+ 
+/// Initialize the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelInitialize (void);
+ 
+///  Get RTOS Kernel Information.
+/// \param[out]    version       pointer to buffer for retrieving version information.
+/// \param[out]    id_buf        pointer to buffer for retrieving kernel identification string.
+/// \param[in]     id_size       size of buffer for kernel identification string.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+ 
+/// Get the current RTOS Kernel state.
+/// \return current RTOS Kernel state.
+osKernelState_t osKernelGetState (void);
+ 
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelStart (void);
+ 
+/// Lock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelLock (void);
+ 
+/// Unlock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelUnlock (void);
+ 
+/// Restore the RTOS Kernel scheduler lock state.
+/// \param[in]     lock          lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelRestoreLock (int32_t lock);
+ 
+/// Suspend the RTOS Kernel scheduler.
+/// \return time in ticks, for how long the system can sleep or power-down.
+uint32_t osKernelSuspend (void);
+ 
+/// Resume the RTOS Kernel scheduler.
+/// \param[in]     sleep_ticks   time in ticks for how long the system was in sleep or power-down mode.
+void osKernelResume (uint32_t sleep_ticks);
+ 
+/// Get the RTOS kernel tick count.
+/// \return RTOS kernel current tick count.
+uint32_t osKernelGetTickCount (void);
+ 
+/// Get the RTOS kernel tick frequency.
+/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
+uint32_t osKernelGetTickFreq (void);
+ 
+/// Get the RTOS kernel system timer count.
+/// \return RTOS kernel current system timer count as 32-bit value.
+uint32_t osKernelGetSysTimerCount (void);
+ 
+/// Get the RTOS kernel system timer frequency.
+/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
+uint32_t osKernelGetSysTimerFreq (void);
+ 
+ 
+//  ==== Thread Management Functions ====
+ 
+/// Create a thread and add it to Active Threads.
+/// \param[in]     func          thread function.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \param[in]     attr          thread attributes; NULL: default values.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+ 
+/// Get name of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return name as null-terminated string.
+const char *osThreadGetName (osThreadId_t thread_id);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadGetId (void);
+ 
+/// Get current thread state of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current thread state of the specified thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id);
+ 
+/// Get stack size of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return stack size in bytes.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id);
+ 
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return remaining stack space in bytes.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
+ 
+/// Change priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+ 
+/// Get current priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id);
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadYield (void);
+ 
+/// Suspend execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSuspend (osThreadId_t thread_id);
+ 
+/// Resume execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadResume (osThreadId_t thread_id);
+ 
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadDetach (osThreadId_t thread_id);
+ 
+/// Wait for specified thread to terminate.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadJoin (osThreadId_t thread_id);
+ 
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void);
+ 
+/// Terminate execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadTerminate (osThreadId_t thread_id);
+ 
+/// Get number of active threads.
+/// \return number of active threads.
+uint32_t osThreadGetCount (void);
+ 
+/// Enumerate active threads.
+/// \param[out]    thread_array  pointer to array for retrieving thread IDs.
+/// \param[in]     array_items   maximum number of items in array for retrieving thread IDs.
+/// \return number of enumerated threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
+ 
+ 
+//  ==== Thread Flags Functions ====
+ 
+/// Set the specified Thread Flags of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     flags         specifies the flags of the thread that shall be set.
+/// \return thread flags after setting or error code if highest bit set.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+ 
+/// Clear the specified Thread Flags of current running thread.
+/// \param[in]     flags         specifies the flags of the thread that shall be cleared.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsClear (uint32_t flags);
+ 
+/// Get the current Thread Flags of current running thread.
+/// \return current thread flags.
+uint32_t osThreadFlagsGet (void);
+ 
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelay (uint32_t ticks);
+ 
+/// Wait until specified time.
+/// \param[in]     ticks         absolute time in ticks
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelayUntil (uint32_t ticks);
+ 
+ 
+//  ==== Timer Management Functions ====
+ 
+/// Create and Initialize a timer.
+/// \param[in]     func          function pointer to callback function.
+/// \param[in]     type          \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer callback function.
+/// \param[in]     attr          timer attributes; NULL: default values.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+ 
+/// Get name of a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return name as null-terminated string.
+const char *osTimerGetName (osTimerId_t timer_id);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
+ 
+/// Stop a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStop (osTimerId_t timer_id);
+ 
+/// Check if a timer is running.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return 0 not running, 1 running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id);
+ 
+/// Delete a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerDelete (osTimerId_t timer_id);
+ 
+ 
+//  ==== Event Flags Management Functions ====
+ 
+/// Create and Initialize an Event Flags object.
+/// \param[in]     attr          event flags attributes; NULL: default values.
+/// \return event flags ID for reference by other functions or NULL in case of error.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
+ 
+/// Get name of an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return name as null-terminated string.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
+ 
+/// Set the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be set.
+/// \return event flags after setting or error code if highest bit set.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+ 
+/// Clear the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be cleared.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+ 
+/// Get the current Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return current event flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
+ 
+/// Wait for one or more Event Flags to become signaled.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+ 
+/// Delete an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
+ 
+ 
+//  ==== Mutex Management Functions ====
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     attr          mutex attributes; NULL: default values.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr);
+ 
+/// Get name of a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return name as null-terminated string.
+const char *osMutexGetName (osMutexId_t mutex_id);
+ 
+/// Acquire a Mutex or timeout if it is locked.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+ 
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexRelease (osMutexId_t mutex_id);
+ 
+/// Get Thread which owns a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return thread ID of owner thread or NULL when mutex was not acquired.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
+ 
+/// Delete a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexDelete (osMutexId_t mutex_id);
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+/// Create and Initialize a Semaphore object.
+/// \param[in]     max_count     maximum number of available tokens.
+/// \param[in]     initial_count initial number of available tokens.
+/// \param[in]     attr          semaphore attributes; NULL: default values.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+ 
+/// Get name of a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return name as null-terminated string.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
+ 
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+ 
+/// Release a Semaphore token up to the initial maximum count.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
+ 
+/// Get current Semaphore token count.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return number of tokens available.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
+ 
+/// Delete a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+ 
+/// Create and Initialize a Memory Pool object.
+/// \param[in]     block_count   maximum number of memory blocks in memory pool.
+/// \param[in]     block_size    memory block size in bytes.
+/// \param[in]     attr          memory pool attributes; NULL: default values.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+ 
+/// Get name of a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return name as null-terminated string.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
+ 
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+ 
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     block         address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+ 
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return maximum number of memory blocks.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
+ 
+/// Get memory block size in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return memory block size in bytes.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+ 
+/// Get number of memory blocks used in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks used.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
+ 
+/// Get number of memory blocks available in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks available.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
+ 
+/// Delete a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+/// Create and Initialize a Message Queue object.
+/// \param[in]     msg_count     maximum number of messages in queue.
+/// \param[in]     msg_size      maximum message size in bytes.
+/// \param[in]     attr          message queue attributes; NULL: default values.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+ 
+/// Get name of a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return name as null-terminated string.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
+ 
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[in]     msg_ptr       pointer to buffer with message to put into a queue.
+/// \param[in]     msg_prio      message priority.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+ 
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[out]    msg_ptr       pointer to buffer for message to get from a queue.
+/// \param[out]    msg_prio      pointer to buffer for message priority or NULL.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+ 
+/// Get maximum number of messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum number of messages.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+ 
+/// Get maximum message size in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum message size in bytes.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
+ 
+/// Get number of queued messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of queued messages.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
+ 
+/// Get number of available slots for messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of available slots for messages.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
+ 
+/// Reset a Message Queue to initial empty state.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
+ 
+/// Delete a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // CMSIS_OS2_H_

CMSIS_5

@@ -1 +0,0 @@
-Subproject commit 13b9f72f212688d2306d0d085d87cbb4bf9e5d3f

CMakeLists.txt

@@ -2,8 +2,9 @@ option(USE_USBCDC_FOR_STDIO "Export an extra USB-CDC interface for stdio, instea
 set(FAMILY "rp2040" CACHE STRING "Board/MCU family, decides which drivers to use. Set to RP2040 by default.")
 set(BOARD "raspberry_pi_pico" CACHE STRING "Board used, determines the pinout. Defaults to the Raspberry Pi Pico.")
 
-# use directory name for project id # FIXME: use fixed project name
-get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
+# use directory name for project id
+#get_filename_component(PROJECT "Dragon Probe" NAME)
+set(PROJECT "DragonProbe")
 set(PROJECT ${BOARD}-${PROJECT})
 
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
@@ -20,21 +21,18 @@ if(FAMILY STREQUAL "rp2040")
   option(PICO_NO_FLASH "Disable writing the compiled program to flash, and only load it to RAM. Useful for testing, but not much else (OFF by default)." OFF)
   option(PICO_COPY_TO_RAM "Run all code in RAM, while the program is also stored on flash. On bootup, everything will be copied to RAM (OFF by default)." OFF)
 
-  if (USE_SYSTEMWIDE_PICOSDK)
-    set(TOP "$ENV{PICO_SDK_PATH}/lib/tinyusb")
-    get_filename_component(TOP "${TOP}" REALPATH)
-    include(cmake/pico_sdk_import.cmake)
-  else()
-    set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
-    include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
-  endif()
+  include(pico_sdk_import.cmake)
+  set(TOP "${PICO_SDK_PATH}/lib/tinyusb")
+  get_filename_component(TOP "${TOP}" REALPATH)
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake) # tinyusb stuff
+  include(${TOP}/hw/bsp/family_support.cmake) # tinyusb stuff
 
   family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-  project(${PROJECT})
-  family_initialize_project(PROJECT ${CMAKE_CURRENT_LIST_DIR}) # calls pico_sdk_init()
-  #pico_sdk_init()
+  #set(PROJECT DragonProbe)
+  project(${PROJECT} C CXX ASM)
+  #family_initialize_project(PROJECT ${CMAKE_CURRENT_LIST_DIR}) # calls pico_sdk_init()
+  pico_sdk_init()
 
   #pico_set_program_name(${PROJECT} "${PROJECT}")
   #pico_set_program_version(${PROJECT} "0.1")
@@ -44,34 +42,59 @@ if(FAMILY STREQUAL "rp2040")
   # need uart stdio, usb is busy doing other stuff
   if(USE_USBCDC_FOR_STDIO)
     # we're going to manually implement this case
-    pico_enable_stdio_uart(${PROJECT} 0)
+	#pico_enable_stdio_uart(${PROJECT} 0)
     target_compile_definitions(${PROJECT} PUBLIC USE_USBCDC_FOR_STDIO=1 PICO_STDIO_USB=1)
   else()
-    pico_enable_stdio_uart(${PROJECT} 1)
+	  #pico_enable_stdio_uart(${PROJECT} 1)
+	  #set_target_properties(${PROJECT} PROPERTIES PICO_TARGET_STDIO_UART 1)
   endif()
+  pico_enable_stdio_uart(${PROJECT} 1)
   pico_enable_stdio_usb(${PROJECT} 0)
+  #set_target_properties(${PROJECT} PROPERTIES PICO_TARGET_STDIO_UART 1)
+  #set_target_properties(${PROJECT} PROPERTIES PICO_TARGET_STDIO_USB 0)
 else()
   message(FATAL_ERROR "Invalid FAMILY '${FAMILY}' specified")
 endif()
 
 target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/no_malloc.c
   ${CMAKE_CURRENT_SOURCE_DIR}/libco/libco.S
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/JTAG_DP.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP_vendor.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/SWO.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/SW_DP.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/cdc_uart.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/i2c_tinyusb.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/spi_serprog.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/tempsensor.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Firmware/Source/DAP.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Firmware/Source/JTAG_DP.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Firmware/Source/DAP_vendor.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Firmware/Source/SWO.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Firmware/Source/SW_DP.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Firmware/Source/UART.c
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/unique.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_serprog.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/src/vnd_i2ctinyusb.c
   ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/src/rtconf.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/alloc.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/modeset.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/thread.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/tusb_plt.S
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/src/tempsensor.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/vnd_cfg.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_default/_default.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_default/cdc_serprog.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_default/tempsensor.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_default/vnd_i2ctinyusb.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_isp/_isp.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_isp/mehfet.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_jscan/_jscan.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_jscan/jscan.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_sump/_sump.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/m_sump/cdc_sump.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/cdc_uart.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/dap_jtag.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/dap_swd.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/dap_uart.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/dap_swo.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/i2c_tinyusb.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/spi_serprog.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/tempsensor.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_isp/mehfet_hw.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_isp/sbw_hw.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_jscan/jscan_hw.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_sump/sump_hw.c
 )
 if(USE_USBCDC_FOR_STDIO)
   target_sources(${PROJECT} PUBLIC
@@ -81,21 +104,25 @@ endif()
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/
   ${CMAKE_CURRENT_SOURCE_DIR}/libco/
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Include/
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/Core/Include/
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Firmware/Include/
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Core/Include/
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/Driver/Include/
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS-DAP/RTOS2/Include/
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/default/
 )
 
-set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -Wextra")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -Wextra -Werror=implicit-function-declaration -Werror=return-type")
 set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra")
 
 add_custom_target(fix_db ALL WORKING_DIRECTORY ${OUTPUT_DIR}
   COMMAND "${CMAKE_CURRENT_SOURCE_DIR}/scripts/fix_clang_db.py")
 
 if(FAMILY STREQUAL "rp2040")
+  # NOTE: do NOT enable pico_runtime here, as it pulls in malloc!
   target_link_libraries(${PROJECT} pico_stdlib pico_unique_id hardware_spi
-    pico_fix_rp2040_usb_device_enumeration hardware_i2c hardware_adc
+    hardware_i2c hardware_adc hardware_pio hardware_dma hardware_pwm
+    pico_fix_rp2040_usb_device_enumeration
     tinyusb_device tinyusb_board tinyusb_additions)
 
   if(USE_USBCDC_FOR_STDIO)
@@ -113,6 +140,12 @@ if(FAMILY STREQUAL "rp2040")
     target_link_libraries(${PROJECT} pico_stdio)
   endif()
 
+  pico_generate_pio_header(${PROJECT} ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/dap_jtag.pio)
+  pico_generate_pio_header(${PROJECT} ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/dap_swd.pio)
+  pico_generate_pio_header(${PROJECT} ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/swo_uart_rx.pio)
+  pico_generate_pio_header(${PROJECT} ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_default/swo_manchester_encoding.pio)
+  pico_generate_pio_header(${PROJECT} ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/m_isp/sbw.pio)
+
   pico_add_extra_outputs(${PROJECT})
 
 else()

LICENSE.jtagenum

@@ -0,0 +1,10 @@
+The below copyright and permission notice applies to portions of the following files, which have
+been modified from their original versions in <https://github.com/cyphunk/JTAGenum>
+(the "JTAGEnum repository")
+
+ - src/m_jscan/jscan.c
+
+The below notice does not apply to any modifications made to the above files since the versions
+present in the JTAGenum repository, nor to any files not present in the JTAGenum repository.
+
+This license for this code is whatever you want it to be

LICENSE.pico-examples

@@ -0,0 +1,36 @@
+The BSD-3-Clause license applies to portions of the following files, which have
+been modified from their original versions in <https://github.com/raspberrypi/pico-examples/>
+(the "Pico examples repository")
+
+ - bsp/rp2040/m_default/swo_manchester_encoding.pio
+ - bsp/rp2040/m_default/swo_uart_rx.pio
+
+The below notice does not apply to any modifications made to the above files
+since the versions present in the Pico examples repository, nor to any files
+not present in the Pico exmaples repository.
+
+
+
+
+
+ Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
+following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following
+   disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
+   disclaimer in the documentation and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSE.picoprobe-sump

@@ -0,0 +1,37 @@
+The below copyright and permission notice applies to portions of the following
+files, which have been modified from their original versions in
+<https://github.com/perexg/picoprobe-sump> (the "picoprobe-sump repository")
+
+ - bsp/rp2040/m_sump/sump_hw.c
+ - bsp/rp2040/m_sump/sump_hw.h
+ - src/m_sump/cdc_sump.c
+ - src/m_sump/sump.h
+
+The below notice does not apply to any modifications made to the above files
+since the versions present in the picoprobe-usb repository, nor to any files
+not present in the picoprobe-usb repository.
+
+
+
+
+The MIT License (MIT)
+
+Copyright (c) 2021 Jaroslav Kysela <perex@perex.cz>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

LICENSE.swdscan

@@ -0,0 +1,10 @@
+The GNU GPL v3 applies to portions of the following files, which have
+been modified from their original versions in <https://github.com/szymonh/SWDscan>
+(the "SWDscan repository")
+
+ - src/m_jscan/jscan.c
+
+To comply with the GPL, this repository has also been made available under
+version 3 of the GPL.
+
+For the full text of the GNU GPL v3, please refer to the `COPYING' file.

README.md

@@ -1,6 +1,4 @@
-# DapperMime-JTAG
-
-(name is still WIP)
+# Dragon Probe
 
 This project attempts to add Bus Pirate/...-like functionality to a number of
 MCUs, mainly the Raspberry Pi Pico. It was originally based on [Dapper
@@ -59,224 +57,75 @@ Other options are:
 
 ## Usage
 
-These microcontrollers support the following protocols:
-
-| MCU    | SWD | JTAG | UART | SPI (flashrom) | I2C | Other stuff     |
-|:------ |:---:|:----:|:----:|:-------------- |:--- |:--------------- |
-| RP2040 | X   | X    | X    | X              | X   |     Planned     |
-
-The [original repository]() (Dapper
-Mime) supported only SWD and UART, and worked for the RP2040 Pico and the
-STM32F072 Discovery. This fork focusses on adding more protocols, but the
-author of this fork only has a Raspberry Pi Pico.
-
-The pin mapping for the RP2040 is as follows:
-
-| Pin number | Usage          | Usage          | Pin number |
-|:---------- |:-------------- | --------------:| ----------:|
-| GP0        | stdio UART TX  |                | VBUS       |
-| GP1        | stdio UART RX  |                | VSYS       |
-| GND        | <ground> | <ground> | GND        |
-| GP2        | SWCLK/TCK      |                | 3V3 EN     |
-| GP3        | SWDIO/TMS      |                | 3V3 OUT    |
-| GP4        | UART TX        |                | ADC VREF   |
-| GP5        | UART RX        |                | GP28 / ADC2|
-| GND        | <ground> | <ground> | GND  / AGND|
-| GP6        | TDI            |                | GP27 / ADC1|
-| GP7        | TDO            |                | GP26 / ADC0|
-| GP8        | nTRST          |                | RUN        |
-| GP9        | nRESET         |                | GP22       |
-| GND        | <ground> | <ground> | GND        |
-| GP10       | UART CTS       | SCL            | GP21       |
-| GP11       | UART RTS       | SDA            | GP20       |
-| GP12       | MISO           |                | GP19       |
-| GP13       | nCS            |                | GP18       |
-| GND        | <ground> | <ground> | GND        |
-| GP14       | SCLK           |                | GP17       |
-| GP15       | MOSI           |                | GP16       |
-| <end>| <bottom> | <bottom> | <end>|
-
-On the RP2040, two USB CDC interfaces are exposed: the first is the UART
-interface, the second is for Serprog. If you have no other USB-CDC intefaces,
-these will be `/dev/ttyACM0` and `/dev/ttyACM1`, respectively. If you have
-enabled the `USE_USBCDC_FOR_STDIO` option, there will be a third device file.
-
-### UART
-
-The UART pins are for connecting to the device to be debugged, the data is
-echoed back over the USB CDC interface (typically a `/dev/ttyACMx` device on
-Linux). If you want to get stdio readout of this program on your computer,
-connect GP0 to GP5, and GP1 to GP4, or alternatively, use the
-`USE_USBCDC_FOR_STDIO` CMake flag, which adds an extra USB-CDC interface for
-which stdio is used exclusively, while disabling stdio on the UART.
-
-### SWD and JTAG debugging
-
-In SWD mode, the pin mapping is entirely as with the standard Picoprobe setup,
-as described in Chapter 5 and Appendix A of [Getting Started with Raspberry Pi
-Pico](https://datasheets.raspberrypi.org/pico/getting-started-with-pico.pdf)
-
-In JTAG mode, TCK and TMS have the same pins as SWCLK and SWDIO, respectively,
-TDI and TDO are on the next two consecutive free pins.
-
-In your OpenOCD flags, use `-f interface/cmsis-dap.cfg`. Default transport is
-JTAG, if OpenOCD doesn't specify a default to the probe.
-
-### Serprog/Flashrom
-
-For Serprog, use the following `flashrom` options (if `/dev/ttyACM1` is the USB
-serial device on your machine corresponding to the Serprog CDC interface of the
-Pico):
-
-```
-flashrom -c <flashchip> -p serprog:dev=/dev/ttyACM1:115200 <rest of the read/write cmd>
-```
-
-Different serial speeds can be used, too. Serprog support is *techincally*
-untested, as in it does output the correct SPI commands as seen by my logic
-analyzer, but I don't have a SPI flash chip to test it on.
-
-### I2C-Tiny-USB
-
-The I2C-Tiny-USB functionality can be used as follows: first, load the
-`i2c-dev` and `i2c-tiny-usb` modules (for now you need a patched version of the
-latter, can be found in the `i2c-tiny-usb-misc/` folder in this repo). Then you
-can use the I2C USB bridge as any other I2C device on your computer. For
-example, the `i2cdetect`, `i2cget` and `i2cset` tools from `i2c-tools` should
-all work. You can find which I2C device corresponds to the I2C-Tiny-USB, by
-running `i2cdetect -l`:
-
-```
-$ sudo i2cdetect -l
-[...]
-i2c-1	i2c       	i915 gmbus dpb                  	I2C adapter
-i2c-8	i2c       	Radeon i2c bit bus 0x95         	I2C adapter
-i2c-15	i2c       	i2c-tiny-usb at bus 001 device 011	I2C adapter  # <---- !
-i2c-6	i2c       	Radeon i2c bit bus 0x93         	I2C adapter
-i2c-13	i2c       	AUX C/DDI C/PHY C               	I2C adapter
-[...]
-```
-
-**NOTE**: I2C functionality sometimes breaks with certain USB hubs. If this is
-the case, try unplugging and replugging the entire hub.
-
-#### I2C temperature sensor emulation
-
-If the board/MCU has a builtin temperature sensor, a fake I2C device on the bus
-can optionally be enabled to use it as a Jedec JC42.2-compliant temperature
-sensor (the exact sensor emulated is the Microchip MCP9808). To have it show
-up in `sensors`, do the following (with `BUSNUM` the number from the above
-`i2cdetect -l` output):
-```
-$ ./dmctl.py /dev/ttyACM1 --i2ctemp 0x18     # need to give it an address first
-$ sudo modprobe jc42
-$ # now tell the jc42 module that the device can be found at this address
-$ echo "jc42 0x18" | sudo tee /sys/bus/i2c/devices/i2c-BUSNUM/new_device
-$ sudo sensors                               # it should show up now:
-jc42-i2c-BUSNUM-18
-Adapter: i2c-tiny-usb at bus 001 device 032
-temp1:        +23.1°C  (low  = -20.0°C)
-                       (high = +75.0°C, hyst = +75.0°C)
-                       (crit = +80.0°C, hyst = +80.0°C)
-```
-
-Temperature readout may be a bit higher than the ambient temperature.
-
-### Runtime configuration
-
-Several settings can be applied at runtime, using the `dmctl` Python script.
-Settings are communicated over the Serprog USB serial port.
-
-The currently implemented options are:
-- `support`: tells you which features this implementation/board supports
-- `ctsrts`: Enable/disable CTS/RTS-based hardware flow control for the UART port
-- `i2ctemp`: Get or set the I2C address of the fake I2C device of the temperature
-             sensor. Use 0 for getting the value, 0xff for disabling, and any
-             other for setting the address. The I2C device emulated is an MCP9808.
-             When setting a value, the old value is printed.
-
-```
-usage: dmctl [-h] [-v] [--ctsrts [CTSRTS]] tty
-
-Runtime configuration control for DapperMime-JTAG
-
-positional arguments:
-  tty                Path to DapperMime-JTAG Serprog UART device
-
-optional arguments:
-  -h, --help           show this help message and exit
-  -v, --verbose        Verbose logging (for this utility)
-  --ctsrts [CTSRTS]    Enable or disable CTS/RTS flow control (--ctsrts [true|false])
-  --i2ctemp [I2CTEMP]  Control the builtin I2C temperature controller: get (0),
-                       disable (-1/0xff) or set/enable (other) the current
-                       status and I2C bus address
-  --support            Get list of supported/implemented functionality
-```
-
-example:
-
-```
-$ ./dmctl.py /dev/ttyACM1 --ctsrts true
-```
+For detailed usage notes, please visit the [wiki](https://git.lain.faith/sys64738/DragonProbe/wiki/Home).
 
 ## License
 
+The code of this project itself is licensed under the [GPL v3](https://opensource.org/licenses/GPL-3.0).
+
 TinyUSB is licensed under the [MIT license](https://opensource.org/licenses/MIT).
 
 ARM's CMSIS 5 code is licensed under the [Apache 2.0 license](https://opensource.org/licenses/Apache-2.0).
 
-libco is licensed under the [ISC license](https://opensource.org/licenses/ISC)
+libco is licensed under the [ISC license](https://opensource.org/licenses/ISC).
+
+Some code has been incorporated from the [DapperMime](https://github.com/majbthrd/DapperMime),
+[picoprobe-sump](https://github.com/perexg/picoprobe-sump),
+[JTAGenum](https://github.com/cyphunk/JTAGenum),
+[SWDscan](https://github.com/szymonh/SWDscan) and the [Raspberry Pico
+examples](https://github.com/raspberrypi/pico-examples/)
+projects. These respective licenses can be found in
+[this](./LICENSE.dappermime), [this](./LICENSE.picoprobe-sump),
+[this](./LICENSE.jtagenum), [this](./LICENSE.swdscan) and
+[this](./LICENSE.pico-examples) file.
 
 ## TODO
 
-- [ ] A name
-- [x] CMSIS-DAP JTAG implementation
-- [x] Flashrom/SPI support using Serprog
-  - Parallel ROM flashing support, too, by having the device switch into a
-    separate mode that temporarily disables all other IO protocols
-    - Not enough IO, rip.
-- [x] UART with CTS/RTS flow control
-  - [x] Needs configurable stuff as well, as some UART interfaces won't use this.
+- [ ] **A (VID and) PID**
+- [ ] GPL license headers on every file
 - [x] Debug interface to send printf stuff directly to USB, instead of having
       to use the UART interface as a loopback thing.
   - [ ] Second UART port for when stdio UART is disabled?
-- [x] I2C support by emulating the I2C Tiny USB
+- [x] I2C support ~~by emulating the I2C Tiny USB~~
   - [x] Expose RP2040-internal temperature ADC on I2C-over-USB bus?
   - [ ] ~~Does SMBus stuff need special treatment here?~~ ~~No.~~  Actually, some
-    parts do, but, laziness.
+        parts do, but, laziness.
   - [x] 10-bit I2C address support (Needs poking at the Pico SDK, as it only
         supports 7-bit ones).
-- [ ] A proper interface for sending commands etc. instead of shoehorning it
-      into Serprog.
-- [ ] JTAG pinout detector
-  - https://github.com/cyphunk/JTAGenum
-- [ ] Host-side script that is an XVC (or hw_server) cable and communicates
-      with the device to perform the JTAG commands, because Vivado no likey
-      OpenOCD.
-  - CMSIS-DAP interface can be used directly, see CMSIS_5/CMSIS/DoxyGen/DAP/src/dap_USB_cmds.txt
-  - https://github.com/BerkeleyLab/XVC-FTDI-JTAG
-  - https://www.eevblog.com/forum/fpga/xilinx-jtag-and-tcf/
-  - https://git.eclipse.org/c/tcf/org.eclipse.tcf.git/plain/docs/TCF%20Linux%20Agent%20Prototype.html
-  - http://www.eclipse.org/tcf/
-  - https://debugmo.de/2012/02/xvcd-the-xilinx-virtual-cable-daemon/
-  - https://github.com/Xilinx/XilinxVirtualCable/
-  - https://github.com/derekmulcahy/xvcpi
-  - OpenOCD as XVC client??
-- [ ] SUMP logic analyzer mode?
-  - see also [this](https://github.com/perexg/picoprobe-sump)
+- [ ] **1-wire**
+- [ ] **make modes persistent?**
 - [ ] FT2232 emulation mode?
+  - watch out, still need a vnd cfg interface! libftdi expects the following stuff: (TODO: acquire detailed protocol description)
+    - interface 0 ("A"): index 1, epin 0x02, epout 0x81
+    - interface 1 ("B"): index 2, epin 0x04, epout 0x83
+    - interface 2 ("C"): index 3, epin 0x06, epout 0x85
+    - interface 3 ("D"): index 4, epin 0x08, epout 0x87
+- [ ] "Complex Trigger" mode for aiding with glitching triggers, by turning
+      UART/SPI/I2C/eMMC/... sequences into a GPIO toggle
 - [ ] Mode where you can define custom PIO stuff for custom pinouts/protocols??????
   - Maybe also with code that auto-reacts to stuff from the environment?
+- [ ] Facedancer implementation by connecting two picos via GPIO, one doing host
+      stuff, the other device, commands being sent over GPIO to do stuff
 - [ ] Maybe use the ADCs for something?
 - [ ] SD/MMC/SDIO (will be a pain)
+- [ ] MSP430 programming
+  - https://dlbeer.co.nz/mspdebug/usb.html
+  - https://github.com/dlbeer/mspdebug
+  - https://www.ti.com/lit/an/slaa754/slaa754.pdf
+  - https://www.ti.com/lit/ug/slau320aj/slau320aj.pdf
 - [ ] AVR programming (USBavr emulation?)
   - AVR ISP is hardly used anymore
   - TPI/UPDI requires 5V levels, Pico doesn't do that :/
   - debugWIRE????
+  - https://github.com/travisgoodspeed/goodfet/blob/master/firmware/apps/avr/avr.c
+- [ ] PIC programming
+  - https://github.com/travisgoodspeed/goodfet/tree/master/firmware/apps/pic
 - iCE40 programming??
+  - https://github.com/adamgreig/ffp
 - Renesas E7-{0,1,2} programming thing????
   - Renesas tell us how this works pls
+  - https://github.com/szymonh/rl78check is something at least
 - Maybe steal other features from the Bus Pirate, [HydraBus](https://github.com/hydrabus/hydrafw) or Glasgow or so
-  - 1-wire and 3-wire? Never seen this one in the wild
+  - 3-wire? Never seen this one in the wild
   - CAN? LIN? MOD? If I'd first be able to find a CAN device to test it with, sure
 

bsp/default/cdc_uart.c

@@ -1,11 +0,0 @@
-// vim: set et:
-
-#include "protos.h"
-
-void cdc_uart_init(void) { }
-
-void cdc_uart_task(void) { }
-
-void cdc_uart_set_hwflow(bool enable) { (void)enable; }
-void cdc_uart_set_baud_rate(uint32_t brate) { (void)brate; }
-

bsp/default/i2c_tinyusb.c

@@ -1,36 +0,0 @@
-// vim: set et:
-
-#include "i2ctinyusb.h"
-
-__attribute__((__const__)) enum ki2c_funcs i2ctu_get_func(void) { return 0; }
-
-void i2ctu_init(void) { }
-
-uint32_t i2ctu_set_freq(uint32_t freq, uint32_t us) {
-    (void)freq;
-    (void)us;
-
-    return 0;
-}
-
-enum itu_status i2ctu_write(enum ki2c_flags flags, enum itu_command startstopflags, uint16_t addr,
-    const uint8_t* buf, size_t len) {
-    (void)flags;
-    (void)startstopflags;
-    (void)addr;
-    (void)buf;
-    (void)len;
-
-    return ITU_STATUS_ADDR_NAK;
-}
-enum itu_status i2ctu_read(enum ki2c_flags flags, enum itu_command startstopflags, uint16_t addr,
-    uint8_t* buf, size_t len) {
-    (void)flags;
-    (void)startstopflags;
-    (void)addr;
-    (void)buf;
-    (void)len;
-
-    return ITU_STATUS_ADDR_NAK;
-}
-

bsp/default/protocfg.h

@@ -1,45 +0,0 @@
-// vim: set et:
-
-#ifndef PROTOCFG_H_
-#define PROTOCFG_H_
-
-/*#define DBOARD_HAS_UART
-#define DBOARD_HAS_CMSISDAP
-#define DBOARD_HAS_SERPROG
-#define DBOARD_HAS_I2C
-#define DBOARD_HAS_TEMPSENSOR*/
-
-enum {
-    /*HID_N_CMSISDAP = 0,*/
-
-    HID_N__NITF
-};
-enum {
-/*CDC_N_UART = 0,
-CDC_N_SERPROG,*/
-#ifdef USE_USBCDC_FOR_STDIO
-    CDC_N_STDIO,
-#endif
-
-    CDC_N__NITF
-};
-enum { VND_N__NITF = 0 };
-
-#define CFG_TUD_HID 0
-#ifdef USE_USBCDC_FOR_STDIO
-#define CFG_TUD_CDC 1
-#else
-#define CFG_TUD_CDC 0
-#endif
-#define CFG_TUD_VENDOR 0
-
-/*#define USB_VID 0x2e8a*/ /* Raspberry Pi */
-#define USB_VID 0xcafe     /* TinyUSB */
-/*#define USB_VID 0x1209*/ /* Generic */
-/*#define USB_VID 0x1d50*/ /* OpenMoko */
-#define USB_PID 0x1312
-
-#define INFO_BOARDNAME "Unknown"
-
-#endif
-

bsp/default/spi_serprog.c

@@ -1,26 +0,0 @@
-// vim: set et:
-
-#include "protos.h"
-#include "serprog.h"
-
-void sp_spi_init(void) { }
-
-uint32_t __not_in_flash_func(sp_spi_set_freq)(uint32_t freq_wanted) {
-    (void)freq_wanted;
-    return 0;
-}
-
-void __not_in_flash_func(sp_spi_cs_deselect)(void) { }
-void __not_in_flash_func(sp_spi_cs_select)(void) { }
-void __not_in_flash_func(sp_spi_op_begin)(void) { }
-void __not_in_flash_func(sp_spi_op_end)(void) { }
-
-void __not_in_flash_func(sp_spi_op_write)(uint32_t write_len, const uint8_t* write_data) {
-    (void)write_len;
-    (void)write_data;
-}
-void __not_in_flash_func(sp_spi_op_read)(uint32_t read_len, uint8_t* read_data) {
-    (void)read_len;
-    (void)read_data;
-}
-

bsp/default/tempsensor.c

@@ -1,14 +0,0 @@
-// vim: set et:
-
-#include "tempsensor.h"
-
-void tempsense_dev_init(void) { }
-
-// clang-format off
-// 8.4
-int16_t tempsense_dev_get_temp (void) { return 0 << 4; }
-int16_t tempsense_dev_get_lower(void) { return trunc_8fix4(float2fix(  0)); }
-int16_t tempsense_dev_get_upper(void) { return trunc_8fix4(float2fix(  0)); }
-int16_t tempsense_dev_get_crit (void) { return trunc_8fix4(float2fix(  0)); }
-// clang-format on
-

bsp/rp2040/DAP_config.h

@@ -60,12 +60,15 @@ This information includes:
 
 #include "bsp/board.h"
 #include "cmsis_compiler.h"
-#include "pinout.h"
-#include "protos.h"
+
+#include "info.h"
 #include "util.h"
+#include "m_default/bsp-feature.h"
+#include "m_default/pinout.h"
 
 #define PINOUT_SWCLK PINOUT_JTAG_TCK
 #define PINOUT_SWDIO PINOUT_JTAG_TMS
+#define PINOUT_SWO   PINOUT_JTAG_TDO
 
 #define PINOUT_SWCLK_MASK (1UL << PINOUT_SWCLK)
 #define PINOUT_SWDIO_MASK (1UL << PINOUT_SWDIO)
@@ -126,14 +129,18 @@ This information includes:
 
 /// Indicate that UART Serial Wire Output (SWO) trace is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define SWO_UART 0  ///< SWO UART:  1 = available, 0 = not available.
+#define SWO_UART 1  ///< SWO UART:  1 = available, 0 = not available.
+
+// should cause a linker error, because we're not using a hardware UART on the pico for SWO
+#define SWO_UART_DRIVER 9999
 
 /// Maximum SWO UART Baudrate.
 #define SWO_UART_MAX_BAUDRATE 10000000U  ///< SWO UART Maximum Baudrate in Hz.
+// ^ 10 MHz
 
 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define SWO_MANCHESTER 0  ///< SWO Manchester:  1 = available, 0 = not available.
+#define SWO_MANCHESTER 1  ///< SWO Manchester:  1 = available, 0 = not available.
 
 /// SWO Trace Buffer Size.
 #define SWO_BUFFER_SIZE 4096U  ///< SWO Trace Buffer Size in bytes (must be 2^n).
@@ -143,10 +150,10 @@ This information includes:
 
 /// Indicate that UART Communication Port is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_UART 0  ///< DAP UART:  1 = available, 0 = not available.
+#define DAP_UART 1  ///< DAP UART:  1 = available, 0 = not available.
 
 /// USART Driver instance number for the UART Communication Port.
-#define DAP_UART_DRIVER 1  ///< USART Driver instance number (Driver_USART#).
+#define DAP_UART_DRIVER _DAPFAKE  ///< USART Driver instance number (Driver_USART#).
 
 /// UART Receive Buffer Size.
 #define DAP_UART_RX_BUFFER_SIZE 64U  ///< Uart Receive Buffer Size in bytes (must be 2^n).
@@ -176,7 +183,7 @@ This information includes:
 #define TARGET_DEVICE_NAME   "Pico"          ///< String indicating the Target Device
 #endif
 
-#include "DAP.h"
+/*#include "DAP.h"*/
 
 /** Get Vendor ID string.
 \param str Pointer to buffer to store the string.
@@ -202,7 +209,11 @@ __STATIC_INLINE uint8_t DAP_GetProductString(char* str) {
 \param str Pointer to buffer to store the string.
 \return String length.
 */
-__STATIC_INLINE uint8_t DAP_GetSerNumString(char* str) { return get_unique_id_u8((uint8_t*)str); }
+__STATIC_INLINE uint8_t DAP_GetSerNumString(char* str) {
+    int len = get_unique_id_u8((uint8_t*)str);
+    str[len] = 0;
+    return len;
+}
 
 /** Get Target Device Vendor string.
 \param str Pointer to buffer to store the string (max 60 characters).
@@ -294,76 +305,79 @@ Configures the DAP Hardware I/O pins for JTAG mode:
  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
  - TDO to input mode.
 */
-__STATIC_INLINE void PORT_JTAG_SETUP(void) {
-    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
-
-    /* set to default high level */
-    sio_hw->gpio_oe_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
-                          PINOUT_nRESET_MASK;
-    sio_hw->gpio_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
-                       PINOUT_nRESET_MASK;
-    /* TDO needs to be an input */
-    sio_hw->gpio_oe_clr = PINOUT_TDO_MASK;
-
-    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TCK],
-        PADS_BANK0_GPIO0_IE_BITS,  // bits to set: input enable
-        PADS_BANK0_GPIO0_IE_BITS |
-            PADS_BANK0_GPIO0_OD_BITS);  // bits to mask out: input enable, output disable
-    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TMS], PADS_BANK0_GPIO0_IE_BITS,
-        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDI], PADS_BANK0_GPIO0_IE_BITS,
-        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDO],
-        PADS_BANK0_GPIO0_IE_BITS |
-            PADS_BANK0_GPIO0_OD_BITS,  // TDO needs to have its output disabled
-        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nTRST], PADS_BANK0_GPIO0_IE_BITS,
-        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nRESET], PADS_BANK0_GPIO0_IE_BITS,
-        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-
-    // NOTE: hiZ: ctrl = (ctrl & ~(CTRL_OEOVER_BITS)) | (GPIO_OVERRIDE_LOW << CTRL_OEOVER_LSB);
-    // normal == 0, low == 2
-
-    // set pin modes to general IO (SIO)
-    iobank0_hw->io[PINOUT_JTAG_TCK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-    iobank0_hw->io[PINOUT_JTAG_TMS].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-    iobank0_hw->io[PINOUT_JTAG_TDI].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-    iobank0_hw->io[PINOUT_JTAG_TDO].ctrl = (GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB)
-        /*| (GPIO_OVERRIDE_LOW << IO_BANK0_GPIO0_CTRL_OEOVER_LSB)*/;
-    iobank0_hw->io[PINOUT_JTAG_nTRST].ctrl  = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-    iobank0_hw->io[PINOUT_JTAG_nRESET].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-}
+void PORT_JTAG_SETUP(void);
+//__STATIC_INLINE void PORT_JTAG_SETUP(void) {
+//    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+//
+//    /* set to default high level */
+//    sio_hw->gpio_oe_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
+//                          PINOUT_nRESET_MASK;
+//    sio_hw->gpio_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
+//                       PINOUT_nRESET_MASK;
+//    /* TDO needs to be an input */
+//    sio_hw->gpio_oe_clr = PINOUT_TDO_MASK;
+//
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TCK],
+//        PADS_BANK0_GPIO0_IE_BITS,  // bits to set: input enable
+//        PADS_BANK0_GPIO0_IE_BITS |
+//            PADS_BANK0_GPIO0_OD_BITS);  // bits to mask out: input enable, output disable
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TMS], PADS_BANK0_GPIO0_IE_BITS,
+//        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDI], PADS_BANK0_GPIO0_IE_BITS,
+//        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDO],
+//        PADS_BANK0_GPIO0_IE_BITS |
+//            PADS_BANK0_GPIO0_OD_BITS,  // TDO needs to have its output disabled
+//        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nTRST], PADS_BANK0_GPIO0_IE_BITS,
+//        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nRESET], PADS_BANK0_GPIO0_IE_BITS,
+//        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+//
+//    // NOTE: hiZ: ctrl = (ctrl & ~(CTRL_OEOVER_BITS)) | (GPIO_OVERRIDE_LOW << CTRL_OEOVER_LSB);
+//    // normal == 0, low == 2
+//
+//    // set pin modes to general IO (SIO)
+//    iobank0_hw->io[PINOUT_JTAG_TCK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+//    iobank0_hw->io[PINOUT_JTAG_TMS].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+//    iobank0_hw->io[PINOUT_JTAG_TDI].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+//    iobank0_hw->io[PINOUT_JTAG_TDO].ctrl = (GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB)
+//        /*| (GPIO_OVERRIDE_LOW << IO_BANK0_GPIO0_CTRL_OEOVER_LSB)*/;
+//    iobank0_hw->io[PINOUT_JTAG_nTRST].ctrl  = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+//    iobank0_hw->io[PINOUT_JTAG_nRESET].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+//}
 
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
 */
-__STATIC_INLINE void PORT_SWD_SETUP(void) {
-    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
-
-    /* set to default high level */
-    sio_hw->gpio_oe_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
-    sio_hw->gpio_set    = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
-
-    hw_write_masked(&padsbank0_hw->io[PINOUT_SWCLK], PADS_BANK0_GPIO0_IE_BITS,
-        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-    hw_write_masked(&padsbank0_hw->io[PINOUT_SWDIO], PADS_BANK0_GPIO0_IE_BITS,
-        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-    iobank0_hw->io[PINOUT_SWCLK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-    iobank0_hw->io[PINOUT_SWDIO].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-}
+void PORT_SWD_SETUP(void);
+//__STATIC_INLINE void PORT_SWD_SETUP(void) {
+//    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+//
+//    /* set to default high level */
+//    sio_hw->gpio_oe_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+//    sio_hw->gpio_set    = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+//
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_SWCLK], PADS_BANK0_GPIO0_IE_BITS,
+//        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+//    hw_write_masked(&padsbank0_hw->io[PINOUT_SWDIO], PADS_BANK0_GPIO0_IE_BITS,
+//        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+//    iobank0_hw->io[PINOUT_SWCLK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+//    iobank0_hw->io[PINOUT_SWDIO].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+//}
 
 /** Disable JTAG/SWD I/O Pins.
 Disables the DAP Hardware I/O pins which configures:
  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
 */
-__STATIC_INLINE void PORT_OFF(void) {
+void PORT_OFF(void);
+/*__STATIC_INLINE void PORT_OFF(void) {
     sio_hw->gpio_oe_clr = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK |
                           PINOUT_TDI_MASK  //| PINOUT_TDO_MASK
                         | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
-}
+}*/
 
 // SWCLK/TCK I/O pin -------------------------------------
 
@@ -426,13 +440,15 @@ __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) {
 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
 called prior \ref PIN_SWDIO_OUT function calls.
 */
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { sio_hw->gpio_oe_set = PINOUT_SWDIO_MASK; }
+//__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { sio_hw->gpio_oe_set = PINOUT_SWDIO_MASK; }
+void PIN_SWDIO_OUT_ENABLE(void);
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
 called prior \ref PIN_SWDIO_IN function calls.
 */
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { sio_hw->gpio_oe_clr = PINOUT_SWDIO_MASK; }
+//__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { sio_hw->gpio_oe_clr = PINOUT_SWDIO_MASK; }
+void PIN_SWDIO_OUT_DISABLE(void);
 
 // TDI Pin I/O ---------------------------------------------
 
@@ -622,4 +638,7 @@ __STATIC_INLINE uint8_t RESET_TARGET(void) {
 
 ///@}
 
+extern int swdsm, swdoffset, jtagsm, jtagoffset;
+
 #endif /* __DAP_CONFIG_H__ */
+

bsp/rp2040/board.h

@@ -28,6 +28,8 @@
 #ifndef BOARD_H_MOD
 #define BOARD_H_MOD
 
+#include <pico/bootrom.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -48,6 +50,10 @@ extern "C" {
 #define UART_RX_PIN PICO_DEFAULT_UART_RX_PIN
 #endif
 
+// (not actually for TinyUSB overrides)
+// Reset to bootloader
+#define bsp_reset_bootloader() reset_usb_boot(0, 0)
+
 #ifdef __cplusplus
 }
 #endif

bsp/rp2040/bsp-info.h

@@ -0,0 +1,29 @@
+// vim: set et:
+
+#ifndef BSP_INFO_H_
+#define BSP_INFO_H_
+
+/*#define USB_VID 0x2e8a*/ /* Raspberry Pi */
+#define USB_VID 0xcafe     /* TinyUSB */
+/*#define USB_VID 0x1209*/ /* Generic */
+/*#define USB_VID 0x1d50*/ /* OpenMoko */
+#define USB_PID 0x1312
+
+/* openFPGAloader silliness */
+/*#define USB_VID 0x0d28*/ /* NXP */
+/*#define USB_PID 0x0204*/ /* ARM mbed */
+
+// TODO: other RP2040 boards
+#define INFO_BOARDNAME "RP2040 Pico"
+
+/* each CFG_TUD_xxx macro must be the max across all modes */
+// TODO: have this depend on the DBOARD_HAS_xxx macros?
+#define CFG_TUD_HID 1
+#ifdef USE_USBCDC_FOR_STDIO
+#define CFG_TUD_CDC 3
+#else
+#define CFG_TUD_CDC 2
+#endif
+#define CFG_TUD_VENDOR 2
+
+#endif

bsp/rp2040/cdc_stdio.c

@@ -2,24 +2,55 @@
 
 #include <hardware/irq.h>
 #include <pico/binary_info.h>
+#include <pico/bootrom.h>
 #include <pico/mutex.h>
 #include <pico/stdio.h>
 #include <pico/stdio/driver.h>
 #include <pico/time.h>
 
-#include "pinout.h"
-#include "protocfg.h"
-#include "tusb.h"
+#include "tusb_config.h"
+#include <tusb.h>
 
+
+// PICO_CONFIG: PICO_STDIO_USB_STDOUT_TIMEOUT_US, Number of microseconds to be blocked trying to write USB output before assuming the host has disappeared and discarding data, default=500000, group=pico_stdio_usb
 #ifndef PICO_STDIO_USB_STDOUT_TIMEOUT_US
 #define PICO_STDIO_USB_STDOUT_TIMEOUT_US 500000
 #endif
 
+// PICO_CONFIG: PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE, Enable/disable resetting into BOOTSEL mode if the host sets the baud rate to a magic value (PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE), type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE
+#define PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE, baud rate that if selected causes a reset into BOOTSEL mode (if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE is set), default=1200, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE
+#define PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE 1200
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via USB (either VIA_BAUD_RATE or VIA_VENDOR_INTERFACE), type=int, min=0, max=29, group=pico_stdio_usb
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED, Whether the pin specified by PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED is fixed or can be modified by picotool over the VENDOR USB interface, type=bool, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED
+#define PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED 0
+#endif
+
+// Any modes disabled here can't be re-enabled by picotool via VENDOR_INTERFACE.
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK, Optionally disable either the mass storage interface (bit 0) or the PICOBOOT interface (bit 1) when entering BOOTSEL mode via USB (either VIA_BAUD_RATE or VIA_VENDOR_INTERFACE), type=int, min=0, max=3, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK
+#define PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK 0u
+#endif
+
+
 // *mostly* the same as the SDK code, *except* we have to explicitely pass the
 // CDC interface number to the tusb functions, making the SDK code itself very
 // non-reusable >__>
 
 static mutex_t stdio_usb_mutex;
+static int CDC_N_STDIO = 0;
+
+void stdio_usb_set_itf_num(int itf) {
+    CDC_N_STDIO = itf;
+}
 
 static void stdio_usb_out_chars(const char* buf, int length) {
     static uint64_t last_avail_time;
@@ -107,3 +138,18 @@ bool stdio_usb_init(void) {
     return true;
 }
 
+void stdio_usb_line_coding_cb(cdc_line_coding_t const* line_coding) {
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE
+    if (line_coding->bit_rate == PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE) {
+        uint32_t gpio = 0;
+
+#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED
+        gpio = 1u << PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED;
+#endif
+
+        reset_usb_boot(gpio, PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK);
+    }
+#endif
+}
+
+

bsp/rp2040/linkdefs.h

@@ -0,0 +1,9 @@
+
+#ifndef BSP_LINKDEFS_H_
+#define BSP_LINKDEFS_H_
+
+#define BSP_HEAP_START_SYM __end__
+#define BSP_HEAP_END_SYM __StackLimit /* __HeapLimit? */
+
+#endif
+

bsp/rp2040/m_default/bsp-feature.h

@@ -0,0 +1,37 @@
+
+#ifndef BSP_FEATURE_M_DEFAULT_H_
+#define BSP_FEATURE_M_DEFAULT_H_
+
+#define DBOARD_HAS_UART
+#define DBOARD_HAS_CMSISDAP
+#define DBOARD_HAS_SPI
+#define DBOARD_HAS_I2C
+#define DBOARD_HAS_TEMPSENSOR
+
+#include "bsp-info.h"
+
+enum {
+    HID_N_CMSISDAP = 0,
+
+    HID_N__NITF
+};
+enum {
+    CDC_N_UART = 0,
+    CDC_N_SERPROG,
+#ifdef USE_USBCDC_FOR_STDIO
+    CDC_N_STDIO,
+#endif
+
+    CDC_N__NITF
+};
+enum {
+    VND_N_CMSISDAP = 0,
+#if CFG_TUD_VENDOR > 0
+    VND_N_CFG,
+#endif
+
+    VND_N__NITF
+};
+
+#endif
+

bsp/rp2040/m_default/cdc_uart.c

@@ -27,22 +27,46 @@
 #include <pico/binary_info.h>
 #include <pico/stdlib.h>
 
-#include "pinout.h"
-#include "protos.h"
-#include "tusb.h"
+#include <tusb.h>
+
+#include "m_default/bsp-feature.h"
+#include "m_default/pinout.h"
+#include "m_default/cdc.h"
 
 static uint8_t rx_buf[CFG_TUD_CDC_RX_BUFSIZE];
 static uint8_t tx_buf[CFG_TUD_CDC_TX_BUFSIZE];
+static bool hwflow = false;
+static int lc_brate = PINOUT_UART_BAUDRATE,
+           lc_data = 8, lc_parity = 0, lc_stop = 1;
 
 void cdc_uart_init(void) {
+    /*lc_brate = PINOUT_UART_BAUDRATE;
+    lc_data = 8;
+    lc_parity = 0;
+    lc_stop = 1;
+    hwflow = false;*/
+
     gpio_set_function(PINOUT_UART_TX, GPIO_FUNC_UART);
     gpio_set_function(PINOUT_UART_RX, GPIO_FUNC_UART);
-    uart_init(PINOUT_UART_INTERFACE, PINOUT_UART_BAUDRATE);
+    gpio_set_function(PINOUT_UART_CTS, GPIO_FUNC_SIO);
+    gpio_set_function(PINOUT_UART_RTS, GPIO_FUNC_SIO);
+    uart_init(PINOUT_UART_INTERFACE, lc_brate/*PINOUT_UART_BAUDRATE*/);
+    //uart_set_hw_flow(PINOUT_UART_INTERFACE, hwflow, hwflow);
+    uart_set_format(PINOUT_UART_INTERFACE, lc_data, lc_stop, lc_parity);
 
     bi_decl(bi_2pins_with_func(PINOUT_UART_TX, PINOUT_UART_RX, GPIO_FUNC_UART));
 }
+void cdc_uart_deinit(void) {
+    uart_deinit(PINOUT_UART_INTERFACE);
+    gpio_set_function(PINOUT_UART_TX, GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_UART_RX, GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_UART_CTS, GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_UART_RTS, GPIO_FUNC_NULL);
+}
 
 void cdc_uart_task(void) {
+    if (cdc_uart_dap_override) return;
+
     // Consume uart fifo regardless even if not connected
     uint rx_len = 0;
     while (uart_is_readable(PINOUT_UART_INTERFACE) && (rx_len < sizeof(rx_buf))) {
@@ -64,9 +88,43 @@ void cdc_uart_task(void) {
     }
 }
 
-void cdc_uart_set_hwflow(bool enable) { uart_set_hw_flow(PINOUT_UART_INTERFACE, enable, enable); }
-
-void cdc_uart_set_baudrate(uint32_t brate) {
-    uart_init(PINOUT_UART_INTERFACE, brate);
+bool cdc_uart_get_hwflow(void) {
+    return hwflow;
+}
+bool cdc_uart_set_hwflow(bool enable) {
+    hwflow = enable;
+    //uart_set_hw_flow(PINOUT_UART_INTERFACE, enable, enable);
+    // TODO: CTS
+    gpio_put(PINOUT_UART_RTS, enable);
+    return true;
 }
 
+uint32_t cdc_uart_set_coding(uint32_t brate,
+        uint8_t stop, uint8_t parity, uint8_t data) {
+    // tusb: parity: 0=none 1=odd  2=even 3=mark 4=space
+    // pîco: parity: 0=none 1=even 2=odd
+    int picopar = 0;
+    switch (parity) {
+        case 0: break;
+        case 2: picopar = 1; break;
+        case 1: picopar = 2; break;
+        default: picopar = lc_parity; break;
+    }
+
+    // FIXME: this is broken fsr
+    /*uart_set_format(PINOUT_UART_INTERFACE, data, stop, picopar);
+
+    lc_data = data;
+    lc_parity = picopar;
+    lc_stop = stop;*/
+    return (lc_brate = uart_set_baudrate(PINOUT_UART_INTERFACE, brate));
+}
+
+// idk where to put this otherwise
+
+bi_decl(bi_program_feature("Mode 1: UART"));
+bi_decl(bi_program_feature("Mode 1: CMSIS-DAP"));
+bi_decl(bi_program_feature("Mode 1: SPI"));
+bi_decl(bi_program_feature("Mode 1: I2C"));
+bi_decl(bi_program_feature("Mode 1: temperature sensor"));
+

bsp/rp2040/m_default/dap_jtag.c

@@ -0,0 +1,623 @@
+// vim: set et:
+
+#include <hardware/clocks.h>
+#include <hardware/gpio.h>
+#include <hardware/pio.h>
+
+#include "util.h"
+
+#include "DAP_config.h"
+#include <DAP.h>
+
+#include "dap_jtag.pio.h"
+#include "dap_swd.pio.h"
+
+#define JTAG_PIO
+
+int jtagsm = -1, jtagoffset = -1;
+
+void PORT_OFF(void) {
+    //printf("disable\n");
+    if (jtagsm >= 0) {
+        pio_sm_set_enabled(PINOUT_JTAG_PIO_DEV, jtagsm, false);
+        pio_sm_unclaim(PINOUT_JTAG_PIO_DEV, jtagsm);
+    }
+    if (jtagoffset >= 0) {
+        pio_remove_program(PINOUT_JTAG_PIO_DEV, &dap_jtag_program, jtagoffset);
+    }
+    jtagoffset = jtagsm = -1;
+
+    if (swdsm >= 0) {
+        pio_sm_set_enabled(PINOUT_JTAG_PIO_DEV, swdsm, false);
+        pio_sm_unclaim(PINOUT_JTAG_PIO_DEV, swdsm);
+    }
+    if (swdoffset >= 0) {
+        pio_remove_program(PINOUT_JTAG_PIO_DEV, &dap_swd_program, swdoffset);
+    }
+    swdoffset = swdsm = -1;
+
+    sio_hw->gpio_oe_clr = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK |
+                          PINOUT_TDI_MASK  //| PINOUT_TDO_MASK
+                        | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
+}
+
+#ifndef JTAG_PIO
+void PORT_JTAG_SETUP(void) {
+    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+
+    /* set to default high level */
+    sio_hw->gpio_oe_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
+                          PINOUT_nRESET_MASK;
+    sio_hw->gpio_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
+                       PINOUT_nRESET_MASK;
+    /* TDO needs to be an input */
+    sio_hw->gpio_oe_clr = PINOUT_TDO_MASK;
+
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TCK],
+        PADS_BANK0_GPIO0_IE_BITS  // bits to set: input enable
+            | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS         // bits to mask out: input enable, output disable
+            | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TMS],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS
+            | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDI],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS
+            | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDO],
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS  // TDO needs to have its output disabled
+            | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nTRST], PADS_BANK0_GPIO0_IE_BITS,
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nRESET], PADS_BANK0_GPIO0_IE_BITS,
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+
+    // NOTE: hiZ: ctrl = (ctrl & ~(CTRL_OEOVER_BITS)) | (GPIO_OVERRIDE_LOW << CTRL_OEOVER_LSB);
+    // normal == 0, low == 2
+
+    // set pin modes to general IO (SIO)
+    iobank0_hw->io[PINOUT_JTAG_TCK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TMS].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TDI].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TDO].ctrl = (GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB)
+        /*| (GPIO_OVERRIDE_LOW << IO_BANK0_GPIO0_CTRL_OEOVER_LSB)*/;
+    iobank0_hw->io[PINOUT_JTAG_nTRST].ctrl  = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_nRESET].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+}
+
+/*void PORT_OFF(void) {
+    sio_hw->gpio_oe_clr = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK |
+                          PINOUT_TDI_MASK  //| PINOUT_TDO_MASK
+                        | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
+}*/
+
+/*void JTAG_Sequence(uint32_t info, const uint8_t* tdi, uint8_t* tdo) {
+    uint32_t n = info & JTAG_SEQUENCE_TCK;
+    if (n == 0) n = 64;
+
+//    printf("seq hi 0x%lx\n", info);
+//
+//    printf("%s", "tdi: ");
+//    for (size_t j = 0; j < ((n + 7) >> 3); ++j) {
+//        printf("0x%x ", ((const uint8_t*)tdi)[j]);
+//    }
+
+    if (info & JTAG_SEQUENCE_TMS) PIN_SWDIO_TMS_SET();
+    else PIN_SWDIO_TMS_CLR();
+
+    for (size_t i = 0; n != 0; ++i) {
+        uint8_t iv = tdi[i], ov = 0;
+
+        for (size_t k = 0; k < 8 && n != 0; ++k, --n) {
+            PIN_TDI_OUT((iv >> k) & 1);
+            PIN_SWCLK_TCK_CLR();
+            PIN_DELAY_SLOW(DAP_Data.clock_delay);
+            ov |= PIN_TDO_IN() << k;
+            PIN_SWCLK_TCK_SET();
+            PIN_DELAY_SLOW(DAP_Data.clock_delay);
+        }
+
+        if (info & JTAG_SEQUENCE_TDO) tdo[i] = ov;
+    }
+
+    n = info & JTAG_SEQUENCE_TCK;
+    if (n == 0) n = 64;
+
+//    if (info & JTAG_SEQUENCE_TDO) {
+//        printf("%s", "\ntdo: ");
+//        for (size_t j = 0; j < ((n + 7) >> 3); ++j) {
+//            printf("0x%x ", ((const uint8_t*)tdo)[j]);
+//        }
+//        printf("%c", '\n');
+//    } else printf("%s", "\nno tdo\n");
+}*/
+
+void jtag_tms_seq(uint32_t count, const uint8_t* data) {
+    for (size_t i = 0; i < count; ++i) {
+        uint8_t byte = data[i >> 3],
+                bit  = (byte >> (i & 7)) & 1;
+
+        if (bit) PIN_SWDIO_TMS_SET();
+        else PIN_SWDIO_TMS_CLR();
+        PIN_SWCLK_TCK_CLR();
+        PIN_DELAY_SLOW(DAP_Data.clock_delay);
+        PIN_SWCLK_TCK_SET();
+        PIN_DELAY_SLOW(DAP_Data.clock_delay);
+    }
+}
+#else
+
+void PORT_JTAG_SETUP(void) {
+    //printf("jtag setup\n");
+    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+
+    /* set to default high level */
+    sio_hw->gpio_oe_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
+                          PINOUT_nRESET_MASK;
+    sio_hw->gpio_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK |
+                       PINOUT_nRESET_MASK;
+    /* TDO needs to be an input */
+    sio_hw->gpio_oe_clr = PINOUT_TDO_MASK;
+
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TCK],
+        PADS_BANK0_GPIO0_IE_BITS  // bits to set: input enable
+            | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS         // bits to mask out: input enable, output disable
+            | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TMS],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS
+            | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDI],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS
+            | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDO],
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS  // TDO needs to have its output disabled
+            | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nTRST], PADS_BANK0_GPIO0_IE_BITS,
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nRESET], PADS_BANK0_GPIO0_IE_BITS,
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+
+    // NOTE: hiZ: ctrl = (ctrl & ~(CTRL_OEOVER_BITS)) | (GPIO_OVERRIDE_LOW << CTRL_OEOVER_LSB);
+    // normal == 0, low == 2
+
+    // set pin modes to general IO (SIO)
+    iobank0_hw->io[PINOUT_JTAG_TCK].ctrl = GPIO_FUNC_PIO0 << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TMS].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TDI].ctrl = GPIO_FUNC_PIO0 << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TDO].ctrl = (GPIO_FUNC_PIO0 << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB)
+        /*| (GPIO_OVERRIDE_LOW << IO_BANK0_GPIO0_CTRL_OEOVER_LSB)*/;
+    iobank0_hw->io[PINOUT_JTAG_nTRST].ctrl  = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_nRESET].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+
+    if (jtagsm == -1) jtagsm = pio_claim_unused_sm(PINOUT_JTAG_PIO_DEV, false);
+    if (jtagoffset == -1)
+        jtagoffset = pio_add_program(PINOUT_JTAG_PIO_DEV, &dap_jtag_program);
+    dap_jtag_program_init(PINOUT_JTAG_PIO_DEV, jtagsm, jtagoffset,
+             50*1000, PINOUT_JTAG_TCK, PINOUT_JTAG_TDI, PINOUT_JTAG_TDO);
+}
+
+#define JTAG_SEQUENCE_NO_TMS 0x80000u /* should be large enough */
+
+void JTAG_Sequence(uint32_t info, const uint8_t* tdi, uint8_t* tdo) {
+    //printf("jtag seq\n");
+    //pio_sm_set_enabled(PINOUT_JTAG_PIO_DEV, jtagsm, true);
+
+    float div = (float)clock_get_hz(clk_sys) / (4 * DAP_Data.clock_freq);
+    if (div < 2) div = 2;
+    else if (div > 65536) div = 65536;
+    pio_sm_set_clkdiv(PINOUT_JTAG_PIO_DEV, jtagsm, div);
+    /*dap_jtag_program_init(PINOUT_JTAG_PIO_DEV, jtagsm, offset,
+             DAP_Data.clock_freq, PINOUT_JTAG_TCK, PINOUT_JTAG_TDI, PINOUT_JTAG_TDO);*/
+
+    uint32_t n = info & JTAG_SEQUENCE_TCK;
+    if (n == 0) n = 64;
+
+    //if (!(n & JTAG_SEQUENCE_NO_TMS)) {
+        if (info & JTAG_SEQUENCE_TMS) PIN_SWDIO_TMS_SET();
+        else PIN_SWDIO_TMS_CLR();
+    //}
+
+    io_wo_8* tx = (io_wo_8*)&PINOUT_JTAG_PIO_DEV->txf[jtagsm];
+    io_ro_8* rx = (io_ro_8*)&PINOUT_JTAG_PIO_DEV->rxf[jtagsm];
+
+    uint32_t bytelen = (n + 7) >> 3;
+    uint32_t last_shift = (8 - n) & 7;
+    //printf("n=%lu bytelen=%lu last_shift=%lu\n", n, bytelen, last_shift);
+    uint32_t txremain = bytelen,
+             rxremain = last_shift ? bytelen : (bytelen + 1);
+    //printf("txremain=%lu rxremain=%lu\n", txremain, rxremain);
+
+    /*printf("%s", "tdi: ");
+    for (size_t j = 0; j < ((n + 7) >> 3); ++j) {
+        printf("0x%x ", ((const uint8_t*)tdi)[j]);
+    }
+    printf("%c", '\n');*/
+
+    pio_sm_put_blocking(PINOUT_JTAG_PIO_DEV, jtagsm, (uint8_t)(n - 1));
+
+    for (size_t oi = 0, ii = 0; txremain || rxremain; tight_loop_contents()) {
+        if (txremain && !pio_sm_is_tx_fifo_full(PINOUT_JTAG_PIO_DEV, jtagsm)) {
+            *tx = bitswap(tdi[ii]);
+            --txremain;
+            //printf("tx %02x rem %lu smpc=%x\n", tdi[ii], txremain, pio_sm_get_pc(PINOUT_JTAG_PIO_DEV, jtagsm));
+            ++ii;
+        }
+
+        if (rxremain && !pio_sm_is_rx_fifo_empty(PINOUT_JTAG_PIO_DEV, jtagsm)) {
+            uint8_t ov = *rx;
+            --rxremain;
+            //printf("rx %02x rem %lu smpc=%x\n", ov, rxremain, pio_sm_get_pc(PINOUT_JTAG_PIO_DEV, jtagsm));
+            // avoid writing extra byte generated by final 'push' insn, would cause buffer ovf
+            if ((info & JTAG_SEQUENCE_TDO) && oi < bytelen) {
+                if (last_shift && oi == bytelen - 1) {
+                    //printf("orig=%02x swap=%02x shamt=%lu result=%02x\n", ov, bitswap(ov), last_shift, bitswap(ov)>>last_shift);
+                    tdo[oi] = bitswap(ov) >> last_shift;
+                } else {
+                    tdo[oi] = bitswap(ov);
+                }
+                ++oi;
+            }
+        }
+    }
+
+    /*if (info & JTAG_SEQUENCE_TDO) {
+        printf("%s", "tdo: ");
+        for (size_t j = 0; j < ((n + 7) >> 3); ++j) {
+            printf("0x%x ", ((const uint8_t*)tdo)[j]);
+        }
+        printf("%c", '\n');
+    } else printf("%s", "no tdo\n");*/
+
+    //pio_sm_set_enabled(PINOUT_JTAG_PIO_DEV, jtagsm, false);
+}
+
+void jtag_tms_seq(uint32_t count, const uint8_t* data) {
+    //printf("jtag tms seq\n");
+    // work around openFPGAloader bug (how did this even get here?)
+    if (DAP_Data.clock_delay == 0) {
+        DAP_Data.clock_delay = 8;
+    }
+
+    /*pio_sm_set_out_pins(PINOUT_JTAG_PIO_DEV, jtagsm, PINOUT_JTAG_TMS, 1);
+    pio_sm_set_set_pins(PINOUT_JTAG_PIO_DEV, jtagsm, PINOUT_JTAG_TMS, 1);
+    pio_sm_set_pins(PINOUT_JTAG_PIO_DEV, jtagsm, gpio_get(PINOUT_JTAG_TMS)?1:0);
+    gpio_set_function(PINOUT_JTAG_TMS, GPIO_FUNC_PIO0 + ((PINOUT_JTAG_PIO_DEV == pio0) ? 0 : 1));
+
+    for (uint32_t i = 0, n; i < count; i += n) {
+        n = count - i;
+        if (n == 0) break;
+        if (n > 64) n = 64;
+        n &= JTAG_SEQUENCE_TCK;
+        JTAG_Sequence(n | JTAG_SEQUENCE_NO_TMS, data, NULL);
+    }
+
+    gpio_put(PINOUT_JTAG_TMS, data[(count >> 3)] & (1 << (count & 7)));
+    gpio_set_function(PINOUT_JTAG_TMS, GPIO_FUNC_SIO);
+    pio_sm_set_out_pins(PINOUT_JTAG_PIO_DEV, jtagsm, PINOUT_JTAG_TDI, 1);
+    pio_sm_set_set_pins(PINOUT_JTAG_PIO_DEV, jtagsm, PINOUT_JTAG_TDI, 1);*/
+
+    // FIXME: above doesn't seem to work somehow -- so fall back to bit-banging
+
+    const uint8_t tdibit = 0xff;
+    PIN_SWCLK_TCK_SET();
+    gpio_set_function(PINOUT_JTAG_TMS, GPIO_FUNC_SIO);
+    gpio_set_function(PINOUT_JTAG_TCK, GPIO_FUNC_SIO);
+    for (size_t i = 0; i < count; ++i) {
+        uint8_t byte = data[i >> 3],
+                bit  = byte & (1 << (i & 7));//(byte >> (i & 7)) & 1;
+
+        //JTAG_Sequence(1 | (bit ? JTAG_SEQUENCE_TMS : 0), &tdibit, NULL);
+        if (bit) PIN_SWDIO_TMS_SET();
+        else PIN_SWDIO_TMS_CLR();
+        PIN_SWCLK_TCK_CLR();
+        PIN_DELAY_SLOW(DAP_Data.clock_delay);
+        PIN_SWCLK_TCK_SET();
+        PIN_DELAY_SLOW(DAP_Data.clock_delay);
+    }
+    gpio_set_function(PINOUT_JTAG_TCK, GPIO_FUNC_PIO0);
+}
+#endif
+
+static void jtag_seq(uint32_t num, int tms, const void* tdi, void* tdo) {
+    static uint64_t last_bit = ~(uint64_t)0;
+    uint64_t devnull = 0;
+
+    bool notdi = tdi == NULL, notdo = tdo == NULL;
+
+    if (!notdo) tms |= JTAG_SEQUENCE_TDO;
+
+    const void* jdi;
+    void* jdo;
+
+    uint32_t nreal;
+    for (uint32_t i = 0; i < num; i += nreal) {
+        uint32_t nmod = (num - i) & 63;
+        nreal = nmod ? nmod : 64;
+
+        jdi = notdi ? (const void*)&last_bit : ((const uint8_t*)tdi + (i >> 3));
+        jdo = notdo ? (      void*)&devnull  : ((      uint8_t*)tdo + (i >> 3));
+
+        JTAG_Sequence(nmod | tms, jdi, jdo);
+    }
+
+    if (tdi) {
+        uint8_t lastbyte = *((const uint8_t*)tdi + (((num + 7) >> 3)) - 1);
+        last_bit = (lastbyte & (1 << (num & 7))) ? ~(uint64_t)0 : (uint64_t)0;
+    }
+}
+
+uint32_t JTAG_ReadIDCode(void) {
+    //printf("jtag readID\n");
+    // tdi=NULL: ~~0xff!~~ repeat last-seen bit, ignore otherwise
+    // tdo=NULL: ignore
+    jtag_seq(1, JTAG_SEQUENCE_TMS, NULL, NULL);
+    jtag_seq(2+DAP_Data.jtag_dev.index, 0, NULL, NULL);
+    uint32_t v=0, v2=0;
+    jtag_seq(31, 0, NULL, &v);
+    jtag_seq(2, JTAG_SEQUENCE_TMS, NULL, &v2);
+    v |= (v2 << 31);
+    jtag_seq(1, 0, NULL, NULL);
+    return v;
+
+    /*// TMS HI
+    // TCK LOW; DELAY; TCK HI; DELAY (DRscan)
+    // TMS LOW
+    // TCK LOW; DELAY; TCK HI; DELAY (capture)
+    // TCK LOW; DELAY; TCK HI; DELAY (shift)
+
+    for (size_t i = 0; i < DAP_Data.jtag_dev.index; ++i) {
+        // TCK LOW; DELAY; TCK HI; DELAY (bypass to correct chain location)
+    }
+
+    uint32_t v = 0;
+    for (size_t i = 0; i < 31; ++i) {
+        // TCK LOW
+        // DELAY
+        // GET TDO; TCK HI; DELAY
+        v |= tdo << k;
+    }
+    // TMS HI
+    // TCK LOW; DELAY; GET TDO; TCK HI; DELAY
+    v |= tdo << 31;
+
+    // TCK LOW; DELAY; TCK HI; DELAY
+    // TMS LO
+    // TCK LOW; DELAY; TCK HI; DELAY
+
+    return v;*/
+}
+
+void JTAG_IR(uint32_t ir) {
+    //printf("jtag IR\n");
+    jtag_seq(2,JTAG_SEQUENCE_TMS, NULL, NULL);
+    jtag_seq(2,0, NULL, NULL);
+    uint64_t v = ~(uint64_t)0;
+    jtag_seq(DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index],0, &v, NULL);
+    jtag_seq((DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index]-1),0, &ir, NULL);
+    uint32_t ir2 = ir >> (DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index]-1);
+    uint32_t n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index];
+    if (n) {
+        jtag_seq(1,0, &ir2, NULL);
+        ir = ~(uint32_t)0;
+        jtag_seq((n-1),0, &ir, NULL);
+        jtag_seq(1,JTAG_SEQUENCE_TMS, &ir, NULL);
+    } else {
+        jtag_seq(1,JTAG_SEQUENCE_TMS, &ir2, NULL);
+    }
+    jtag_seq(1,JTAG_SEQUENCE_TMS, NULL, NULL);
+    jtag_seq(1,0, NULL, NULL);
+    PIN_TDI_OUT(1); // TODO: TDI HI
+
+    /*// TMS HI
+    // TCK LOW; DELAY; TCK HI; DELAY (DRscan)
+    // TCK LOW; DELAY; TCK HI; DELAY (IRscan)
+    // TMS LO
+    // TCK LOW; DELAY; TCK HI; DELAY (capture)
+    // TCK LOW; DELAY; TCK HI; DELAY (shift)
+
+    // TDI HI
+    for (size_t i = 0; i < DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; ++i) {
+        // TCK LOW; DELAY; TCK HI; DELAY (bypass)
+    }
+    for (size_t i = 0; i < DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1; ++i) {
+        tdi = ir & 1;
+        // SET TDI
+        // TCK LOW; DELAY; TCK HI; DELAY
+        ir >>= 1;
+    }
+
+    uint32_t n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index];
+    if (n) {
+        tdi = ir & 1;
+        // SET TDI
+        // TCK LOW; DELAY; TCK HI; DELAY
+
+        for (size_t i = 1; i < n-1; ++i) {
+            // TCK LOW; DELAY; TCK HI; DELAY
+        }
+        // TMS HI
+        // TCK LOW; DELAY; TCK HI; DELAY
+    } else {
+        tdi = ir & 1;
+        // TMS HI
+        // SET TDI
+        // TCK LOW; DELAY; TCK HI; DELAY
+    }
+
+    // TCK LOW; DELAY; TCK HI; DELAY
+    // TMS LO
+    // TCK LOW; DELAY; TCK HI; DELAY
+    // TDI HI*/
+}
+
+static uint8_t xfer_base(uint32_t request, uint32_t* data, bool check_ack) {
+    jtag_seq(1,JTAG_SEQUENCE_TMS, NULL, NULL);
+    jtag_seq((2+DAP_Data.jtag_dev.index),0, NULL, NULL);
+    uint32_t ack=0;
+    uint32_t reqsh1 = request>>1;
+    jtag_seq(3,0, &reqsh1, &ack);
+    // ack bits are 1,0,2, not 0,1,2 => swap bottom 2 bits
+    ack = ((ack & 2) >> 1) | ((ack & 1) << 2) | (ack & ~(uint32_t)3);
+    if (ack!=DAP_TRANSFER_OK && check_ack) {
+        jtag_seq(1,JTAG_SEQUENCE_TMS, NULL, NULL);
+        goto exit;
+    } else ack=DAP_TRANSFER_OK;
+    if (request & DAP_TRANSFER_RnW) { // read
+        uint32_t val = 0;
+        jtag_seq(31,0, NULL, &val);
+        uint32_t n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1;
+        uint32_t valb = 0;
+        if (n) {
+            jtag_seq(1,0, NULL, &valb);
+            jtag_seq((n-1),0, NULL, NULL);
+            jtag_seq(1,JTAG_SEQUENCE_TMS, NULL, NULL);
+        } else {
+            jtag_seq(1,JTAG_SEQUENCE_TMS, NULL, &valb);
+        }
+        *data = val | (valb << 31);
+    } else {
+        uint32_t val = *data, valb=val>>31;
+        jtag_seq(31,0, &val, NULL);
+        uint32_t n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1;
+        if (n) {
+            jtag_seq(1,0, &valb, NULL);
+            jtag_seq((n-1),0, NULL, NULL);
+            jtag_seq(1,JTAG_SEQUENCE_TMS, NULL, NULL);
+        } else {
+            jtag_seq(1,JTAG_SEQUENCE_TMS, &valb, NULL);
+        }
+    }
+exit:
+    jtag_seq(1,JTAG_SEQUENCE_TMS, NULL, NULL);
+    jtag_seq(1,0, NULL, NULL);
+    PIN_TDI_OUT(1); // TDI HI (no clk)
+    if (request & DAP_TRANSFER_TIMESTAMP) DAP_Data.timestamp = TIMESTAMP_GET();
+    if (check_ack) jtag_seq(DAP_Data.transfer.idle_cycles, 0, NULL, NULL);
+    return (uint8_t)ack;
+
+
+    /*// TMS HI
+    // TCK LOW; DELAY; TCK HI; DELAY
+    // TMS LO
+    // TCK LOW; DELAY; TCK HI; DELAY
+    // TCK LOW; DELAY; TCK HI; DELAY
+
+    for (size_t i = 0; i < DAP_Data.jtag_dev.index; ++i) {
+        // TCK LOW; DELAY; TCK HI; DELAY
+    }
+
+    uint32_t ack = 0;
+
+    tdi = (request >> 1) & 1;
+    // SET TDI
+    // TCK LOW; DELAY
+    // GET TDO
+    // TCK HI; DELAY
+    ack = tdo << 1;
+
+    tdi = (request >> 2) & 1;
+    // SET TDI
+    // TCK LOW; DELAY
+    // GET TDO
+    // TCK HI; DELAY
+    ack |= tdo << 0;
+
+    tdi = (request >> 3) & 1;
+    // SET TDI
+    // TCK LOW; DELAY
+    // GET TDO
+    // TCK HI; DELAY
+    ack |= tdo << 2;
+
+    if (ack != DAP_TRANSFER_OK && check_ack) {
+        // TMS HI
+        // TCK LOW; DELAY; TCK HI; DELAY
+        goto exit;
+    }
+
+    if (request & DAP_TRANSFER_RnW) { // read
+        uint32_t val = 0;
+
+        for (size_t i = 0; i < 31; ++i) {
+            // TCK LOW; DELAY;
+            // GET TDO; TCK HI; DELAY
+            val |= tdo << i;
+        }
+
+        uint32_t n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1;
+        if (n) {
+            // TCK LOW; DELAY;
+            // GET TDO; TCK HI; DELAY
+            for (size_t i = 0; i < n - 1; ++i) {
+                // TCK LOW; DELAY; TCK HI; DELAY
+            }
+            // TMS HI
+            // TCK LOW; DELAY; TCK HI; DELAY
+        } else {
+            // TMS HI
+            // TCK LOW; DELAY;
+            // GET TDO; TCK HI; DELAY
+        }
+
+        val |= tdo << 31;
+    } else { // write
+        uint32_t val = *data;
+
+        for (size_t i = 0; i < 31; ++i) {
+            tdi = (val >> i) & 1;
+            // SET TDI
+            // TCK LOW; DELAY; TCK HI; DELAY
+        }
+
+        uint32_t n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1;
+        if (n) {
+            tdi = (val >> 31) & 1;
+            // SET TDI
+            // TCK LOW; DELAY; TCK HI; DELAY
+            for (size_t i = 0; i < n - 1; ++i) {
+                // TCK LOW; DELAY; TCK HI; DELAY
+            }
+            // TMS HI
+            // TCK LOW; DELAY; TCK HI; DELAY
+        } else {
+            tdi = (val >> 31) & 1;
+            // TMS HI
+            // SET TDI
+            // TCK LOW; DELAY; TCK HI; DELAY
+        }
+    }
+
+exit:
+    // TCK LOW; DELAY; TCK HI; DELAY
+    // TMS LO
+    // TCK LOW; DELAY; TCK HI; DELAY
+    // TDI HI
+
+    if (request & DAP_REQUEST_TIMESTAMP)
+        DAP_Data.timestamp = TIMESTAMP_GET();
+
+    for (size_t i = 0; i < DAP_Data.idle_cycles && check_ack; ++i) {
+        // TCK LOW; DELAY; TCK HI; DELAY
+    }
+
+    return (uint8_t)ack;*/
+}
+
+void JTAG_WriteAbort(uint32_t data) {
+    //printf("jtag wrabort\n");
+    xfer_base(0 /* write,A2=0,A3=0 */, &data, false);
+}
+
+uint8_t JTAG_Transfer(uint32_t request, uint32_t* data) {
+    //printf("jtag xfer\n");
+    return xfer_base(request, data, true);
+}
+//#endif
+

bsp/rp2040/m_default/dap_jtag.pio

@@ -0,0 +1,59 @@
+; vim: set et:
+
+; code mostly from https://github.com/phdussud/pico-dirtyJtag/blob/master/jtag.pio
+; which doesn't have a license...
+
+.program dap_jtag
+.side_set 1 opt
+
+; Pin assignments:
+; - TCK is side-set pin 0
+; - TDI is OUT pin 0
+; - TDO is IN pin 0
+;
+; Autopush and autopull must be enabled, and the serial frame size is set by
+; configuring the push/pull threshold (32 bits). Shift should be left
+;
+; data is captured on the leading edge of each TCK pulse, and
+; transitions on the trailing edge, or some time before the first leading edge.
+
+start:
+    pull                        ; get length-1 and disregard previous OSR state
+    out x, 32       side 0      ; this moves the first 32 bits into X
+loop:
+    out pins, 1     side 0      ; Stall here on empty (sideset proceeds even if instruction stalls, so we stall with SCK low
+    in pins, 1      side 1 [1]
+    jmp x-- loop    side 0
+end:
+    push            side 0      ; Force the last ISR bits to be pushed to the tx fifo
+
+
+% c-sdk {
+static inline void dap_jtag_program_init(PIO pio, uint sm, uint offset,
+        uint16_t freq, uint pin_tck, uint pin_tdi, uint pin_tdo) {
+    pio_sm_config c = dap_jtag_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, pin_tdi, 1);
+    //sm_config_set_set_pins(&c, pin_tdi, 1);
+    sm_config_set_in_pins(&c, pin_tdo);
+    sm_config_set_sideset_pins(&c, pin_tck);
+    // (shift to left, autopush/pull, threshold=nbits)
+    sm_config_set_out_shift(&c, false, true, 8); // shift left feature is broken???
+    sm_config_set_in_shift(&c, false, true, 8);
+    sm_config_set_clkdiv(&c, (float)clock_get_hz(clk_sys) / (4 * freq));
+
+    // TDI, TCK output are low, TDO is input
+    pio_sm_set_pins_with_mask(pio, sm, 0, (1u << pin_tck) | (1u << pin_tdi));
+    pio_sm_set_pindirs_with_mask(pio, sm, (1u << pin_tck) | (1u << pin_tdi),
+            (1u << pin_tck) | (1u << pin_tdi) | (1u << pin_tdo));
+    pio_gpio_init(pio, pin_tdi);
+    //pio_gpio_init(pio, pin_tdo);
+    pio_gpio_init(pio, pin_tck);
+
+    // jtag is synchronous, so bypass input synchroniser to reduce input delay.
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_tdo);
+    gpio_set_pulls(pin_tdo, false, true); // TDO is pulled down
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+%}

bsp/rp2040/m_default/dap_swd.c

@@ -0,0 +1,380 @@
+// vim: set et:
+
+#include <hardware/clocks.h>
+#include <hardware/gpio.h>
+#include <hardware/pio.h>
+#include <hardware/timer.h>
+
+#include "DAP_config.h"
+#include <DAP.h>
+
+#include "util.h"
+
+#include "dap_swd.pio.h"
+
+#define SWD_PIO
+
+int swdsm = -1, swdoffset = -1;
+
+#ifndef SWD_PIO
+void PORT_SWD_SETUP(void) {
+    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+
+    /* set to default high level */
+    sio_hw->gpio_oe_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+    sio_hw->gpio_set    = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+
+    hw_write_masked(&padsbank0_hw->io[PINOUT_SWCLK],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_SWDIO],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    iobank0_hw->io[PINOUT_SWCLK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_SWDIO].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+}
+
+void PIN_SWDIO_OUT_ENABLE(void) {
+    sio_hw->gpio_oe_set = PINOUT_SWDIO_MASK;
+}
+void PIN_SWDIO_OUT_DISABLE(void) {
+    sio_hw->gpio_oe_clr = PINOUT_SWDIO_MASK;
+}
+
+inline static void PIN_SWDIO_SET_PIO(void) { PIN_SWDIO_TMS_SET(); }
+
+/*#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET
+#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR
+
+#define SW_WRITE_BIT(bit)               \
+  PIN_SWDIO_OUT(bit);                   \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define SW_READ_BIT(bit)                \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  bit = PIN_SWDIO_IN();                 \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+
+void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) {
+  printf("hi seq\n");
+  uint32_t val;
+  uint32_t bit;
+  uint32_t n, k;
+
+  n = info & SWD_SEQUENCE_CLK;
+  if (n == 0U) {
+    n = 64U;
+  }
+
+  if (info & SWD_SEQUENCE_DIN) {
+    printf("seq n=%lu din\n", n);
+
+    while (n) {
+      val = 0U;
+      for (k = 8U; k && n; k--, n--) {
+        SW_READ_BIT(bit);
+        val >>= 1;
+        val  |= bit << 7;
+      }
+      val >>= k;
+      *swdi++ = (uint8_t)val;
+      printf("rx %02lx\n", val);
+    }
+  } else {
+    printf("seq n=%lu dout\n", n);
+
+    while (n) {
+      val = *swdo++;
+      printf("tx %02lx\n", val);
+      for (k = 8U; k && n; k--, n--) {
+        SW_WRITE_BIT(val);
+        val >>= 1;
+      }
+    }
+  }
+}*/
+#else
+
+void PORT_SWD_SETUP(void) {
+    //printf("swd setup\n");
+    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+
+    /* set to default high level */
+    sio_hw->gpio_oe_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+    sio_hw->gpio_set    = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+
+    hw_write_masked(&padsbank0_hw->io[PINOUT_SWCLK],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_SWDIO],
+        PADS_BANK0_GPIO0_IE_BITS | (GPIO_SLEW_RATE_SLOW << PADS_BANK0_GPIO0_SLEWFAST_LSB),
+        PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS | PADS_BANK0_GPIO0_SLEWFAST_BITS);
+    iobank0_hw->io[PINOUT_SWCLK].ctrl = GPIO_FUNC_PIO0 << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_SWDIO].ctrl = GPIO_FUNC_PIO0 << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+
+    if (swdsm == -1) swdsm = pio_claim_unused_sm(PINOUT_JTAG_PIO_DEV, false);
+    if (swdoffset == -1)
+        swdoffset = pio_add_program(PINOUT_JTAG_PIO_DEV, &dap_swd_program);
+    dap_swd_program_init(PINOUT_JTAG_PIO_DEV, swdsm, swdoffset,
+             50*1000, PINOUT_SWCLK, PINOUT_SWDIO);
+}
+
+// TODO: also hijack DAP_SWJ_PINS(?: should data pins be controlled like that? only rst stuff tbh)
+
+void PIN_SWDIO_OUT_ENABLE(void) {
+    pio_sm_set_pindirs_with_mask(PINOUT_JTAG_PIO_DEV, swdsm,
+            (1u << PINOUT_SWDIO), (1u << PINOUT_SWDIO));
+}
+void PIN_SWDIO_OUT_DISABLE(void) {
+    pio_sm_set_pindirs_with_mask(PINOUT_JTAG_PIO_DEV, swdsm,
+            (0u << PINOUT_SWDIO), (1u << PINOUT_SWDIO));
+}
+
+inline static void PIN_SWDIO_SET_PIO(void) {
+    pio_sm_set_pins_with_mask(PINOUT_JTAG_PIO_DEV, swdsm,
+            (1u << PINOUT_SWDIO), (1u << PINOUT_SWDIO));
+}
+
+void SWD_Sequence(uint32_t info, const uint8_t* swdo, uint8_t* swdi) {
+    //printf("swd sequence\n");
+    pio_sm_set_enabled(PINOUT_JTAG_PIO_DEV, swdsm, true);
+    //busy_wait_us_32(0);
+
+    float div = (float)clock_get_hz(clk_sys) / (2 * DAP_Data.clock_freq);
+    if (div < 2) div = 2;
+    else if (div > 65536) div = 65536;
+    pio_sm_set_clkdiv(PINOUT_JTAG_PIO_DEV, swdsm, div);
+
+    uint32_t n = info & SWD_SEQUENCE_CLK;
+    if (n == 0) n = 64;
+
+    io_wo_8* tx = (io_wo_8*)&PINOUT_JTAG_PIO_DEV->txf[swdsm];
+    io_ro_8* rx = (io_ro_8*)&PINOUT_JTAG_PIO_DEV->rxf[swdsm];
+
+    uint32_t bytelen = (n + 7) >> 3;
+    uint32_t last_shift = (8 - n) & 7;
+    uint32_t txremain = bytelen,
+             rxremain = last_shift ? bytelen : (bytelen + 1);
+
+    /*printf("seq n=%lu bytelen=%lu lsh=%lu txr=%lu rxr=%lu\n",
+            n, bytelen, last_shift, txremain, rxremain);*/
+
+    pio_sm_put_blocking(PINOUT_JTAG_PIO_DEV, swdsm,
+            (uint8_t)(n - 1) | ((info & SWD_SEQUENCE_DIN) ? 0x80000000u : 0));
+
+    if (info & SWD_SEQUENCE_DIN) {
+        for (size_t i = 0; rxremain; tight_loop_contents()) {
+            if (!pio_sm_is_rx_fifo_empty(PINOUT_JTAG_PIO_DEV, swdsm)) {
+                uint8_t v = *rx;
+                --rxremain;
+                //printf("seq din  rx %02x rxr=%lu\n", bitswap(v), rxremain);
+                if (i < bytelen) {
+                    if (last_shift && i == bytelen - 1) {
+                        swdi[i] = bitswap(v) >> last_shift;
+                    } else {
+                        swdi[i] = bitswap(v);
+                    }
+                    ++i;
+                }
+            }
+        }
+    } else {
+        for (size_t i = 0; txremain; tight_loop_contents()) {
+            if (!pio_sm_is_tx_fifo_full(PINOUT_JTAG_PIO_DEV, swdsm)) {
+                *tx = bitswap(swdo[i]);
+                --txremain;
+                //printf("seq dout tx %02x txr=%lu\n", swdo[i], txremain);
+                ++i;
+            }
+        }
+
+        // wait until FIFO empty, so that all bytes have been xmitted
+        while (!pio_sm_is_tx_fifo_empty(PINOUT_JTAG_PIO_DEV, swdsm)) tight_loop_contents();
+        // ^ isn't enough, because of the side-set, so we need the loop below
+        //   however, we still need the above one because otherwise we might
+        //   somehow miss sending some bits in practice...
+
+        // wait until last bit xmitted, and back at the starting insn
+        while (pio_sm_get_pc(PINOUT_JTAG_PIO_DEV, swdsm) != swdoffset) tight_loop_contents();
+    }
+
+    // we need to disable (and reenable at the start of this routine) the SM
+    // because we also use it to set the SWDIO pin and direction elsewhere,
+    // which shouldn't happen when the SM is enabled
+    //busy_wait_us_32(0);
+    pio_sm_set_enabled(PINOUT_JTAG_PIO_DEV, swdsm, false);
+
+    //printf("seq done, disabled\n");
+}
+#endif
+
+static void swd_seq(uint32_t count, uint32_t flags, const uint8_t* swdo, uint8_t* swdi) {
+    //printf("swd seqbase count=%lu\n", count);
+    static uint64_t last_bit = ~(uint64_t)0;
+    uint64_t devnull = 0;
+
+    if ( (flags & SWD_SEQUENCE_DIN) && !swdi) swdi = (uint8_t*)&devnull;
+    if (!(flags & SWD_SEQUENCE_DIN) && !swdo) swdo = (const uint8_t*)&last_bit;
+
+    if (flags & SWD_SEQUENCE_DIN) {
+        PIN_SWDIO_OUT_DISABLE();
+    } else {
+        PIN_SWDIO_OUT_ENABLE();
+    }
+
+    const uint8_t* sdo = NULL;
+    uint8_t* sdi = NULL;
+
+    uint32_t nreal;
+    for (uint32_t i = 0; i < count; i += nreal) {
+        uint32_t nmod = (count - i) & 63;
+        nreal = nmod ? nmod : 64;
+
+        if (flags & SWD_SEQUENCE_DIN) {
+            sdi = swdi ? &swdi[i >> 3] : (      uint8_t*)&devnull ;
+            sdo = NULL;
+        } else {
+            sdo = swdo ? &swdo[i >> 3] : (const uint8_t*)&last_bit;
+            sdi = NULL;
+        }
+
+        SWD_Sequence(nmod | flags, sdo, sdi);
+    }
+
+    if (!(flags & SWD_SEQUENCE_DIN) && swdo) {
+        uint8_t lastbyte = swdo[((count + 7) >> 3) - 1];
+        last_bit = (lastbyte & (1 << (count & 7))) ? ~(uint64_t)0 : (uint64_t)0;
+    }
+
+    //printf("swd seqbase end\n");
+}
+
+void jtag_tms_seq(uint32_t count, const uint8_t* data);
+
+void SWJ_Sequence(uint32_t count, const uint8_t* data) {
+    //printf("swj sequence\n");
+
+    // we can't just do a swd_seq() call here, as the debugger might be in JTAG
+    // instead of SWD mode.
+
+    if ((swdsm == -1 || swdoffset == -1) && jtagsm >= 0 && jtagoffset >= 0) {
+        jtag_tms_seq(count, data); // JTAG mode -- handle in JTAG code
+    } else if (swdsm >= 0 && swdoffset >= 0) {
+        swd_seq(count, 0, data, NULL); // SWD mode - we can do just this
+    } else {
+        //printf("E: SWJ_Sequence while not in JTAG or SBW mode\n");
+        // welp - can't really report an error to the upper CMSIS-DAP layers
+
+        jtag_tms_seq(count, data); // uses only SIO for now so ¯\_(ツ)_/¯
+    }
+
+    // hackier but stabler
+    /*jtag_tms_seq(count, data);
+    if (swdsm != -1 && swdoffset != -1 && jtagsm == -1 && jtagoffset == -1) {
+        gpio_set_function(PINOUT_JTAG_TMS, GPIO_FUNC_PIO0);
+    }*/
+}
+
+uint8_t SWD_Transfer(uint32_t request, uint32_t* data) {
+    //printf("swd xfer request=%08lx\n", request);
+    uint32_t parity;
+    uint8_t swdo;
+
+    parity = ((request >> 0) & 1) + ((request >> 1) & 1)
+           + ((request >> 2) & 1) + ((request >> 3) & 1);
+    swdo = 1 | ((request & 0xf) << 1) | ((parity & 1) << 5) | (0<<6) | (1<<7);
+    swd_seq(8, 0, &swdo, NULL);
+
+    swd_seq(DAP_Data.swd_conf.turnaround, SWD_SEQUENCE_DIN, NULL, NULL);
+
+    uint8_t ack = 0;
+    swd_seq(3, SWD_SEQUENCE_DIN, NULL, &ack);
+    //printf("  ack=%hhu\n", ack);
+
+    uint32_t num;
+    switch (ack) {
+    case DAP_TRANSFER_OK:
+        if (request & DAP_TRANSFER_RnW) {
+            //printf("  xfer ok, r\n");
+            uint64_t val = 0;
+            parity = 0;
+            // FIXME: this is little-endian-only!
+            swd_seq(33, SWD_SEQUENCE_DIN, NULL, (uint8_t*)&val);
+
+            for (size_t i = 0; i < 32; ++i) parity += ((uint32_t)val >> i) & 1;
+            if ((parity & 1) != ((uint32_t)(val >> 32) & 1)) {
+                ack = DAP_TRANSFER_ERROR;
+            }
+            if (data) *data = (uint32_t)val;
+
+            swd_seq(DAP_Data.swd_conf.turnaround, SWD_SEQUENCE_DIN, NULL, NULL);
+
+            //PIN_SWDIO_OUT_ENABLE();
+        } else { // write
+            //printf("  xfer ok, w\n");
+            swd_seq(DAP_Data.swd_conf.turnaround, SWD_SEQUENCE_DIN, NULL, NULL);
+
+            //PIN_SWDIO_OUT_ENABLE();
+
+            uint32_t val = *data;
+
+            parity = 0;
+            for (size_t i = 0; i < 32; ++i) parity += (val >> i) & 1;
+
+            uint64_t out = val | ((uint64_t)(parity & 1) << 32);
+            // FIXME: this is little-endian-only!
+            swd_seq(33, 0, (const uint8_t*)&out, NULL);
+        }
+
+        //printf("  set ts\n");
+        if (request & DAP_TRANSFER_TIMESTAMP) DAP_Data.timestamp = TIMESTAMP_GET();
+
+        num = DAP_Data.transfer.idle_cycles;
+        //printf("  idlecyc=%lu\n", num);
+        for (uint32_t i = 0; i < num; i += 64) {
+            uint64_t swdio = 0;
+
+            uint32_t cyc = num - i;
+            if (cyc > 64) cyc = 64;
+
+            //printf("  sequence of %lu\n", cyc);
+            SWD_Sequence((cyc & SWD_SEQUENCE_CLK), (const uint8_t*)&swdio, NULL);
+        }
+        //printf("  idlecyc end\n");
+        break;
+    case DAP_TRANSFER_WAIT: case DAP_TRANSFER_FAULT:
+        num = DAP_Data.swd_conf.turnaround;
+        if (DAP_Data.swd_conf.data_phase &&  (request & DAP_TRANSFER_RnW)) {
+            num += 33; // 32 bits + parity
+        }
+        //printf("  wait/fault: %lu\n", num);
+
+        swd_seq(num, SWD_SEQUENCE_DIN, NULL, NULL);
+
+        if (DAP_Data.swd_conf.data_phase && !(request & DAP_TRANSFER_RnW)) {
+            //printf("  w/f dataphase\n");
+
+            uint64_t swdio = 0;
+            swd_seq(33, 0, (const uint8_t*)&swdio, NULL); // 32 data bits + parity
+        }
+        break;
+    default: // protocol error
+        //printf("  proto error\n");
+        swd_seq(DAP_Data.swd_conf.turnaround + 33, SWD_SEQUENCE_DIN, NULL, NULL);
+        break;
+    }
+
+    //printf("  finished\n");
+    PIN_SWDIO_OUT_ENABLE();
+    PIN_SWDIO_SET_PIO();
+    return ack;
+}
+//#endif
+

bsp/rp2040/m_default/dap_swd.pio

@@ -0,0 +1,66 @@
+; vim: set et:
+
+.program dap_swd
+.side_set 1 opt
+
+; Pin assignments:
+; - SWCLK is side-set pin 0
+; - SWDIO is OUT pin 0 and IN pin 0
+;
+; Autopush and autopull must be enabled, and the serial frame size is set by
+; configuring the push/pull threshold (32 bits). Shift should be left
+;
+; data is captured on the leading edge of each SWCLK pulse, and
+; transitions on the trailing edge, or some time before the first leading edge.
+
+start_thing:
+    pull
+    out y,  1
+    out x, 31         side 0
+    jmp !y start_swdo side 0
+
+start_swdi:
+loop_swdi:
+    in pins, 1        side 1
+    jmp x-- loop_swdi side 0
+end_swdi:
+    push              side 0
+    jmp start_thing   side 0
+
+start_swdo:
+loop_swdo:
+    out pins, 1       side 0
+    jmp x-- loop_swdo side 1
+end_swdo:
+    jmp start_thing   side 0
+
+% c-sdk {
+static inline void dap_swd_program_init(PIO pio, uint sm, uint offset,
+        uint16_t freq, uint pin_swclk, uint pin_swdio) {
+    pio_sm_config c = dap_swd_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, pin_swdio, 1);
+    sm_config_set_in_pins(&c, pin_swdio);
+    sm_config_set_sideset_pins(&c, pin_swclk);
+    // (shift to left, autopush/pull, threshold=nbits)
+    sm_config_set_out_shift(&c, false, true, 8); // shift left feature is broken???
+    sm_config_set_in_shift(&c, false, true, 8);
+    sm_config_set_clkdiv(&c, (float)clock_get_hz(clk_sys) / (2 * freq));
+
+    // SWCLK is high, SWDIO is input (pull hi)
+    pio_sm_set_pins_with_mask(pio, sm,
+            (1u << pin_swclk),
+            (1u << pin_swclk) | (1u << pin_swdio));
+    pio_sm_set_pindirs_with_mask(pio, sm,
+            (1u << pin_swclk) | (0u << pin_swdio),
+            (1u << pin_swclk) | (1u << pin_swdio));
+    pio_gpio_init(pio, pin_swclk);
+    pio_gpio_init(pio, pin_swdio);
+
+    // swd is synchronous, so bypass input synchroniser to reduce input delay.
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_swdio);
+    gpio_set_pulls(pin_swclk, false, true); // SWDIO is pulled up
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+%}

bsp/rp2040/m_default/dap_swo.c

@@ -0,0 +1,268 @@
+// vim: set et:
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+#include <hardware/dma.h>
+#include <hardware/gpio.h>
+#include <hardware/pio.h>
+#include <hardware/structs/dma.h>
+
+#include "swo_uart_rx.pio.h"
+#include "swo_manchester_encoding.pio.h"
+
+static uint32_t
+    swo_baudrate = 115200,
+    swo_pio_off = ~(uint32_t)0, swo_num = 0;
+static int swo_sm = -1, swo_dmach = -1;
+static bool mode_enabled = false;
+
+#define SWO_PIO PINOUT_JTAG_SWO_DEV
+
+// Enable or disable SWO Mode (UART)
+//   enable: enable flag
+//   return: 1 - Success, 0 - Error
+uint32_t SWO_Mode_UART(uint32_t enable) {
+    //for(;;);//printf("SWO mode %lu\n", enable);
+    if (enable) {
+        if (mode_enabled) { // already inited!
+            return 0;
+        }
+
+        swo_sm = pio_claim_unused_sm(SWO_PIO, false);
+        if (swo_sm == -1) {
+            //for(;;);//printf("E: no PIO\n");
+            return 0;
+        }
+
+        swo_dmach = dma_claim_unused_channel(false);
+        if (swo_dmach == -1) {
+            //for(;;);//printf("E: no DMA\n");
+            pio_sm_unclaim(SWO_PIO, swo_sm);
+            swo_sm = -1;
+            return 0;
+        }
+
+        if (!pio_can_add_program(SWO_PIO, &swo_uart_rx_program)) {
+            //for(;;);//printf("E: no prg\n");
+            dma_channel_unclaim(swo_dmach);
+            swo_dmach = -1;
+            pio_sm_unclaim(SWO_PIO, swo_sm);
+            swo_sm = -1;
+            return 0;
+        }
+
+        swo_pio_off = pio_add_program(SWO_PIO, &swo_uart_rx_program);
+        swo_uart_rx_program_init(SWO_PIO, swo_sm, swo_pio_off, PINOUT_SWO, swo_baudrate);
+        gpio_set_function(PINOUT_SWO, GPIO_FUNC_PIO1);
+
+        mode_enabled = true;
+    } else {
+        mode_enabled = false;
+
+        if (swo_dmach >= 0) {
+            dma_channel_unclaim(swo_dmach); // ugh why is it "dma_channel_xyz" and "dma_xyz_channel"
+            swo_dmach = -1;
+        }
+
+        if (swo_sm >= 0) {
+            pio_sm_set_enabled(SWO_PIO, swo_sm, false);
+            pio_sm_unclaim(SWO_PIO, swo_sm);
+            swo_sm = -1;
+        }
+        if (~swo_pio_off != 0) {
+            pio_remove_program(SWO_PIO, &swo_uart_rx_program, swo_pio_off);
+            swo_pio_off = ~(uint32_t)0;
+        }
+
+        // hi-Z nothing
+        gpio_set_function(PINOUT_SWO, GPIO_FUNC_NULL);
+        gpio_set_pulls(PINOUT_SWO, false, false);
+    }
+
+    return 1;
+}
+
+// Configure SWO Baudrate (UART)
+//   baudrate: requested baudrate
+//   return: actual baudrate or 0 when not configured
+uint32_t SWO_Baudrate_UART(uint32_t baudrate) {
+    //for(;;);//printf("SWO baudrate %lu\n", baudrate);
+    swo_baudrate = baudrate;
+    if (!mode_enabled) return 0;
+
+    swo_uart_rx_program_init(SWO_PIO, swo_sm, swo_pio_off, PINOUT_SWO, baudrate);
+
+    return baudrate; // should be ok
+}
+
+// Control SWO Capture (UART)
+//   active: active flag
+//   return: 1 - Success, 0 - Error
+uint32_t SWO_Control_UART(uint32_t active) {
+    //for(;;);//printf("SWO control %lu\n", active);
+    if (!mode_enabled) return 0;
+
+    if (active) {
+        pio_sm_set_enabled(SWO_PIO, swo_sm, true);
+        dma_channel_start(swo_dmach);
+    }
+    else {
+        dma_channel_abort(swo_dmach);
+        pio_sm_set_enabled(SWO_PIO, swo_sm, false);
+        swo_num = 0;
+    }
+
+    return 1;
+}
+
+// Start SWO Capture (UART)
+//   buf: pointer to buffer for capturing
+//   num: number of bytes to capture
+void SWO_Capture_UART(uint8_t* buf, uint32_t num) {
+    //for(;;);//printf("SWO capture %p 0x%lx\n", buf, num);
+    if (!mode_enabled) return;
+
+    swo_num = num;
+
+    // set up DMA params
+    dma_channel_config dcfg = dma_channel_get_default_config(swo_dmach);
+    channel_config_set_read_increment(&dcfg, false);
+    channel_config_set_write_increment(&dcfg, true);
+    channel_config_set_dreq(&dcfg, pio_get_dreq(SWO_PIO, swo_sm, false));
+    channel_config_set_transfer_data_size(&dcfg, DMA_SIZE_8);
+    dma_channel_configure(swo_dmach, &dcfg, buf, &SWO_PIO->rxf[swo_sm], num, false);
+}
+
+// Get SWO Pending Trace Count (UART)
+//   return: number of pending trace data bytes
+uint32_t SWO_GetCount_UART(void) {
+    // DMA hw decreases transfer_count by one on every transfer, so it contains
+    // the number of remaining bytes to be received.
+    // however, CMSIS-DAP wants (badly worded) the number of bytes already
+    // received
+    if (!mode_enabled || swo_num == 0) return 0; // not initialized
+
+    uint32_t remaining = dma_hw->ch[swo_dmach].transfer_count;
+    //for(;;);//printf("SWO getcount -> 0x%lx\n", swo_num - remaining);
+    return swo_num - remaining;
+}
+
+/*** MANCHESTER **************************************************************/
+
+uint32_t SWO_Mode_Manchester(uint32_t enable) {
+    //for(;;);//printf("SWOM mode %lu\n", enable);
+    if (enable) {
+        if (mode_enabled) { // already inited!
+            return 0;
+        }
+
+        swo_sm = pio_claim_unused_sm(SWO_PIO, false);
+        if (swo_sm == -1) {
+            //for(;;);//printf("E: no PIO\n");
+            return 0;
+        }
+
+        swo_dmach = dma_claim_unused_channel(false);
+        if (swo_dmach == -1) {
+            //for(;;);//printf("E: no DMA\n");
+            pio_sm_unclaim(SWO_PIO, swo_sm);
+            swo_sm = -1;
+            return 0;
+        }
+
+        if (!pio_can_add_program(SWO_PIO, &swo_manchester_rx_program)) {
+            //for(;;);//printf("E: no prg\n");
+            dma_channel_unclaim(swo_dmach);
+            swo_dmach = -1;
+            pio_sm_unclaim(SWO_PIO, swo_sm);
+            swo_sm = -1;
+            return 0;
+        }
+
+        swo_pio_off = pio_add_program(SWO_PIO, &swo_manchester_rx_program);
+        swo_manchester_rx_program_init(SWO_PIO, swo_sm, swo_pio_off, PINOUT_SWO, swo_baudrate);
+        gpio_set_function(PINOUT_SWO, GPIO_FUNC_PIO1);
+
+        mode_enabled = true;
+    } else {
+        mode_enabled = false;
+
+        if (swo_dmach >= 0) {
+            dma_channel_unclaim(swo_dmach); // ugh why is it "dma_channel_xyz" and "dma_xyz_channel"
+            swo_dmach = -1;
+        }
+
+        if (swo_sm >= 0) {
+            pio_sm_set_enabled(SWO_PIO, swo_sm, false);
+            pio_sm_unclaim(SWO_PIO, swo_sm);
+            swo_sm = -1;
+        }
+        if (~swo_pio_off != 0) {
+            pio_remove_program(SWO_PIO, &swo_manchester_rx_program, swo_pio_off);
+            swo_pio_off = ~(uint32_t)0;
+        }
+
+        // hi-Z nothing
+        gpio_set_function(PINOUT_SWO, GPIO_FUNC_NULL);
+        gpio_set_pulls(PINOUT_SWO, false, false);
+    }
+
+    return 1;
+    return 0;
+}
+
+uint32_t SWO_Baudrate_Manchester(uint32_t baudrate) {
+    //for(;;);//printf("SWOM baudrate %lu\n", baudrate);
+    swo_baudrate = baudrate;
+    if (!mode_enabled) return 0;
+
+    swo_manchester_rx_program_init(SWO_PIO, swo_sm, swo_pio_off, PINOUT_SWO, baudrate);
+
+    return baudrate; // should be ok
+}
+
+uint32_t SWO_Control_Manchester(uint32_t active) {
+    //for(;;);//printf("SWOM control %lu\n", active);
+    if (!mode_enabled) return 0;
+
+    if (active) {
+        pio_sm_set_enabled(SWO_PIO, swo_sm, true);
+        dma_channel_start(swo_dmach);
+    }
+    else {
+        dma_channel_abort(swo_dmach);
+        pio_sm_set_enabled(SWO_PIO, swo_sm, false);
+        swo_num = 0;
+    }
+
+    return 1;
+}
+
+void SWO_Capture_Manchester(uint8_t* buf, uint32_t num) {
+    //for(;;);//printf("SWOM capture %p 0x%lx\n", buf, num);
+    if (!mode_enabled) return;
+
+    swo_num = num;
+
+    // set up DMA params
+    dma_channel_config dcfg = dma_channel_get_default_config(swo_dmach);
+    channel_config_set_read_increment(&dcfg, false);
+    channel_config_set_write_increment(&dcfg, true);
+    channel_config_set_dreq(&dcfg, pio_get_dreq(SWO_PIO, swo_sm, false));
+    channel_config_set_transfer_data_size(&dcfg, DMA_SIZE_8);
+    dma_channel_configure(swo_dmach, &dcfg, buf, &SWO_PIO->rxf[swo_sm], num, false);
+}
+
+uint32_t SWO_GetCount_Manchester(void) {
+    // DMA hw decreases transfer_count by one on every transfer, so it contains
+    // the number of remaining bytes to be received.
+    // however, CMSIS-DAP wants (badly worded) the number of bytes already
+    // received
+    if (!mode_enabled || swo_num == 0) return 0; // not initialized
+
+    uint32_t remaining = dma_hw->ch[swo_dmach].transfer_count;
+    //for(;;);//printf("SWO getcount -> 0x%lx\n", swo_num - remaining);
+    return swo_num - remaining;
+}
+

bsp/rp2040/m_default/dap_uart.c

@@ -0,0 +1,290 @@
+// vim: set et:
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+#include <hardware/dma.h>
+#include <hardware/irq.h>
+#include <hardware/uart.h>
+#include <pico/stdlib.h>
+
+#include "Driver_USART.h"
+
+#include "m_default/bsp-feature.h"
+#include "m_default/pinout.h"
+#include "m_default/cdc.h"
+
+bool cdc_uart_dap_override = false;
+
+static int rxdmach = -1, txdmach = -1;
+static ARM_USART_SignalEvent_t irq_callback = NULL;
+
+static void dap_uart_dma_isr() {
+    uint32_t ints = dma_hw->ints0;
+    uint32_t events = 0;
+
+    if (ints & (1u << rxdmach)) {
+        dma_hw->ints0 = 1u << rxdmach;
+        events |= ARM_USART_EVENT_RECEIVE_COMPLETE;
+    }
+    if (ints & (1u << txdmach)) {
+        dma_hw->ints0 = 1u << txdmach;
+        events |= ARM_USART_EVENT_SEND_COMPLETE;
+    }
+
+    if (events && irq_callback) irq_callback(events);
+}
+
+static void dap_uart_err_isr() {
+    uint32_t mis = uart_get_hw(PINOUT_UART_INTERFACE)->mis;
+    uint32_t events = 0;
+
+    if (mis & UART_UARTMIS_OEMIS_BITS) {
+        uart_get_hw(PINOUT_UART_INTERFACE)->icr = UART_UARTICR_OEIC_BITS;
+        events |= ARM_USART_EVENT_RX_OVERFLOW;
+    }
+    if (mis & UART_UARTMIS_PEMIS_BITS) {
+        uart_get_hw(PINOUT_UART_INTERFACE)->icr = UART_UARTICR_PEIC_BITS;
+        events |= ARM_USART_EVENT_RX_PARITY_ERROR;
+    }
+    if (mis & UART_UARTMIS_FEMIS_BITS) {
+        uart_get_hw(PINOUT_UART_INTERFACE)->icr = UART_UARTICR_FEIC_BITS;
+        events |= ARM_USART_EVENT_RX_FRAMING_ERROR;
+    }
+
+    if (events && irq_callback) irq_callback(events);
+}
+
+static int32_t dap_uart_initialize(ARM_USART_SignalEvent_t cb) {
+    if (cdc_uart_dap_override) return ARM_DRIVER_ERROR;
+
+    cdc_uart_dap_override = true;
+    irq_callback = cb;
+    // TODO: do anything?
+    //       cdc_uart.c probably has already inited (otherwise stuff is broken),
+    //       so we don't really have to do anything else here
+    // TODO: cb needs to be called on:
+    //       * send() complete
+    //       * receive() complete
+    //       * rx overflow
+    //       * rx framing error
+    //       * rx parity error
+    //
+    // USB timeout is one second. for a good implementation, we'd want to use
+    // DMA to do the UART transfers in the background, but, laziness. so we do
+    // it in a blocking way in send/receive, and then immediately afterwards do
+    // the callback (instead of requiring irq stuff). gettxcount and getrxcount
+    // then always return the last num values
+    // ... except that doesn't work for receive FIFOs... welp
+
+    rxdmach = dma_claim_unused_channel(false);
+    if (rxdmach == -1) return ARM_DRIVER_ERROR;
+    txdmach = dma_claim_unused_channel(false);
+    if (txdmach == -1) {
+        dma_channel_unclaim(rxdmach);
+        rxdmach = -1;
+        return ARM_DRIVER_ERROR;
+    }
+
+    // make DMAing to/from UART possible
+    hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->dmacr,
+            UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS
+    );
+    // set error interrupt bits CMSIS-DAP wants
+    hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->imsc,
+            UART_UARTIMSC_OEIM_BITS | UART_UARTIMSC_PEIM_BITS
+            | UART_UARTIMSC_FEIM_BITS
+    );
+
+    // start disabled
+    hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr,
+            UART_UARTCR_RXE_BITS | UART_UARTCR_TXE_BITS
+    );
+
+    irq_set_enabled(DMA_IRQ_0, false);
+    irq_set_enabled(UART1_IRQ, false);
+    irq_add_shared_handler(DMA_IRQ_0, dap_uart_dma_isr,
+            PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY);
+    irq_add_shared_handler(UART1_IRQ, dap_uart_err_isr,
+            PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY);
+    irq_set_enabled(UART1_IRQ, true);
+    irq_set_enabled(DMA_IRQ_0, true);
+
+    return ARM_DRIVER_OK;
+}
+static int32_t dap_uart_uninitialize(void) {
+    // Control() may have disabled some stuff, so were going to reenable it now
+    hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr,
+            UART_UARTCR_RXE_BITS | UART_UARTCR_TXE_BITS
+    );
+
+    hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->imsc,
+            UART_UARTIMSC_OEIM_BITS | UART_UARTIMSC_PEIM_BITS
+            | UART_UARTIMSC_FEIM_BITS
+    );
+
+    irq_set_enabled(UART1_IRQ, false);
+    irq_set_enabled(DMA_IRQ_0, false);
+    irq_remove_handler(UART1_IRQ, dap_uart_err_isr);
+    irq_remove_handler(DMA_IRQ_0, dap_uart_dma_isr);
+
+    dma_channel_abort(rxdmach);
+    dma_channel_abort(txdmach);
+
+    dma_channel_unclaim(rxdmach);
+    dma_channel_unclaim(txdmach);
+
+    hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->dmacr,
+            UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS
+    );
+
+    cdc_uart_dap_override = false;
+    return ARM_DRIVER_OK;
+}
+static int32_t dap_uart_powercontrol(ARM_POWER_STATE state) {
+    (void)state; // let's ignore that
+    return ARM_DRIVER_OK;
+}
+
+// DAP/Firmware/Source/UART.c doesn't use these, so let's not implement them
+static ARM_DRIVER_VERSION dap_uart_getversion(void) {
+    panic("dap_uart: GetVersion: not impl");
+    __builtin_unreachable();
+}
+static ARM_USART_CAPABILITIES dap_uart_getcapabilities(void) {
+    panic("dap_uart: GetCapabilities: not impl");
+    __builtin_unreachable();
+}
+static int32_t dap_uart_transfer(const void* out, void* in, uint32_t n) {
+    (void)out; (void)in; (void)n;
+    panic("dap_uart: Transfer: not impl");
+    __builtin_unreachable();
+}
+static ARM_USART_STATUS dap_uart_getstatus(void) {
+    panic("dap_uart: GetStatus: not impl");
+    __builtin_unreachable();
+}
+static int32_t dap_uart_setmodemcontrol(ARM_USART_MODEM_CONTROL mctl) {
+    (void)mctl;
+    panic("dap_uart: SetModemControl: not impl");
+    __builtin_unreachable();
+}
+static ARM_USART_MODEM_STATUS dap_uart_getmodemstatus(void) {
+    panic("dap_uart: GetModemStatus: not impl");
+    __builtin_unreachable();
+}
+
+// actual useful stuff now
+int32_t dap_uart_send(const void* data, uint32_t num) {
+    dma_channel_config dcfg = dma_channel_get_default_config(txdmach);
+    channel_config_set_read_increment(&dcfg, true);
+    channel_config_set_write_increment(&dcfg, false);
+    channel_config_set_dreq(&dcfg, DREQ_UART1_TX);
+    channel_config_set_transfer_data_size(&dcfg, DMA_SIZE_8);
+    dma_irqn_set_channel_enabled(0, txdmach, true);
+    dma_channel_configure(txdmach, &dcfg,
+            &uart_get_hw(PINOUT_UART_INTERFACE)->dr, data, num, true);
+
+    return ARM_DRIVER_OK;
+}
+int32_t dap_uart_receive(void* data, uint32_t num) {
+    dma_channel_config dcfg = dma_channel_get_default_config(rxdmach);
+    channel_config_set_read_increment(&dcfg, false);
+    channel_config_set_write_increment(&dcfg, true);
+    channel_config_set_dreq(&dcfg, DREQ_UART1_RX);
+    channel_config_set_transfer_data_size(&dcfg, DMA_SIZE_8);
+    dma_irqn_set_channel_enabled(0, rxdmach, true);
+    dma_channel_configure(rxdmach, &dcfg, data,
+            &uart_get_hw(PINOUT_UART_INTERFACE)->dr, num, true);
+
+    return ARM_DRIVER_OK;
+}
+uint32_t dap_uart_gettxcount(void) { // gets number of bytes transmitted of send() call
+    return dma_channel_hw_addr(txdmach)->transfer_count;
+}
+uint32_t dap_uart_getrxcount(void) { // gets number of bytes received of receive() call
+    return dma_channel_hw_addr(rxdmach)->transfer_count;
+}
+
+int32_t dap_uart_control(uint32_t control, uint32_t arg) {
+    // ARM_USART_CONTROL_RX 1/0
+    // ARM_USART_CONTROL_TX 1/0
+    // ARM_USART_ABORT_RECEIVE x
+    // ARM_USART_ABORT_SEND x
+    // control ARM_USART_MODE_ASYNCHRONOUS, ARM_USART_FLOW_CONTROL_NONE (ignore this)   baudrate!
+    // control:
+    //  Bit 3..0: Data bits: 5 = 5 Data bits, 6 = 6 Data bits, 7 = 7 Data bits, 0 = 8 Data bits
+    //  Bit 5..4: Parity: 0 = None, 1 = Even, 2 = Odd
+    //  Bit 7..6: Stop bits: 0 = 1 Stop bit, 1 = 2 Stop bits
+
+    if (control == ARM_USART_CONTROL_RX) {
+        if (arg)
+            hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr, UART_UARTCR_RXE_BITS);
+        else
+            hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr, UART_UARTCR_RXE_BITS);
+    } else if (control == ARM_USART_CONTROL_TX) {
+        if (arg)
+            hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr, UART_UARTCR_TXE_BITS);
+        else
+            hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr, UART_UARTCR_TXE_BITS);
+    } else if (control == ARM_USART_ABORT_SEND) {
+        dma_channel_abort(txdmach);
+    } else if (control == ARM_USART_ABORT_RECEIVE) {
+        dma_channel_abort(rxdmach);
+    } else if (control & ARM_USART_MODE_ASYNCHRONOUS) {
+        // for now, don't set some stuff as it can sometimes be a bit borked
+        // with the rp2040 uart(?): parity, stop, data bits
+
+        uint32_t crv = uart_get_hw(PINOUT_UART_INTERFACE)->cr
+            & (UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS | UART_UARTCR_UARTEN_BITS);
+
+        // disable interrupts for a moment so that flushing the FIFOs won't
+        // suddenly cause spurious interrupts
+        hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->imsc,
+                UART_UARTIMSC_OEIM_BITS | UART_UARTIMSC_PEIM_BITS
+                | UART_UARTIMSC_FEIM_BITS
+        );
+
+        // disable momentarily
+        hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr, crv);
+        hw_clear_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->lcr_h, UART_UARTLCR_H_FEN_BITS); // clears the FIFO(?)
+
+        uart_set_baudrate(PINOUT_UART_INTERFACE, arg);
+
+        // reenable
+        hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->lcr_h, UART_UARTLCR_H_FEN_BITS);
+        hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->cr, crv);
+        hw_set_bits(&uart_get_hw(PINOUT_UART_INTERFACE)->imsc,
+                UART_UARTIMSC_OEIM_BITS | UART_UARTIMSC_PEIM_BITS
+                | UART_UARTIMSC_FEIM_BITS
+        );
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+extern ARM_DRIVER_USART Driver_USART_DAPFAKE;
+ARM_DRIVER_USART Driver_USART_DAPFAKE = {
+    .GetVersion = dap_uart_getversion, // nop
+    .GetCapabilities = dap_uart_getcapabilities, // nop
+
+    .Initialize = dap_uart_initialize,
+    .Uninitialize = dap_uart_uninitialize,
+    .PowerControl = dap_uart_powercontrol,
+
+    .Send = dap_uart_send,
+    .Receive = dap_uart_receive,
+    .Transfer = dap_uart_transfer, // nop
+
+    .GetTxCount = dap_uart_gettxcount,
+    .GetRxCount = dap_uart_getrxcount,
+
+    .Control = dap_uart_control,
+    .GetStatus = dap_uart_getstatus, // nop
+    .SetModemControl = dap_uart_setmodemcontrol, // nop
+    .GetModemStatus = dap_uart_getmodemstatus // nop
+};
+
+// USB-CDC stuff
+uint8_t USB_COM_PORT_Activate(uint32_t _) { (void)_; return 0; }
+

bsp/rp2040/m_default/i2c_tinyusb.c

@@ -9,9 +9,10 @@
 #include <pico/stdlib.h>
 #include <pico/timeout_helper.h>
 
-#include "i2ctinyusb.h"
-#include "pinout.h"
-#include "protocfg.h"
+#include "m_default/bsp-feature.h"
+#include "m_default/pinout.h"
+
+#include "m_default/i2ctinyusb.h"
 
 static int delay = 10, delay2 = 5;
 
@@ -380,13 +381,13 @@ static inline int i2cex_read_timeout_us(i2c_inst_t* i2c, uint16_t addr, bool a10
     return i2cex_read_blocking_until(i2c, addr, a10bit, dst, len, nostop, t);
 }
 
-__attribute__((__const__)) enum ki2c_funcs i2ctu_get_func(void) {
+__attribute__((__const__)) enum ki2c_funcs i2ctu_dev_get_func(void) {
     // TODO: SMBUS_EMUL_ALL => I2C_M_RECV_LEN
     // TODO: maybe also PROTOCOL_MANGLING, NOSTART
     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 }
 
-void i2ctu_init(void) {
+void i2ctu_dev_init(void) {
     // default to 100 kHz (SDK example default so should be ok)
     delay  = 10;
     delay2 = 5;
@@ -399,8 +400,19 @@ void i2ctu_init(void) {
 
     bi_decl(bi_2pins_with_func(PINOUT_I2C_SCL, PINOUT_I2C_SDA, GPIO_FUNC_I2C));
 }
+void i2ctu_dev_deinit(void) {
+    gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_NULL);
+    gpio_disable_pulls(PINOUT_I2C_SCL);
+    gpio_disable_pulls(PINOUT_I2C_SDA);
 
-uint32_t i2ctu_set_freq(uint32_t freq, uint32_t us) {
+    // default to 100 kHz (SDK example default so should be ok)
+    delay  = 10;
+    delay2 = 5;
+    i2c_deinit(PINOUT_I2C_DEV);
+}
+
+uint32_t i2ctu_dev_set_freq(uint32_t freq, uint32_t us) {
     delay  = us;
     delay2 = us >> 1;
     if (!delay2) delay2 = 1;
@@ -408,7 +420,7 @@ uint32_t i2ctu_set_freq(uint32_t freq, uint32_t us) {
     return i2c_set_baudrate(PINOUT_I2C_DEV, freq);
 }
 
-enum itu_status i2ctu_write(enum ki2c_flags flags, enum itu_command startstopflags, uint16_t addr,
+enum itu_status i2ctu_dev_write(enum ki2c_flags flags, enum itu_command startstopflags, uint16_t addr,
         const uint8_t* buf, size_t len) {
     bool nostop = !(startstopflags & ITU_CMD_I2C_IO_END);
     bool bit10  = flags & I2C_M_TEN;
@@ -422,12 +434,12 @@ enum itu_status i2ctu_write(enum ki2c_flags flags, enum itu_command startstopfla
             return ITU_STATUS_ADDR_ACK;
     } else*/
     {
-        int rv = i2cex_write_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len, nostop, 1000 * 1000);
+        int rv = i2cex_write_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len, nostop, 400 * 1000);
         if (rv < 0 || (size_t)rv < len) return ITU_STATUS_ADDR_NAK;
         return ITU_STATUS_ADDR_ACK;
     }
 }
-enum itu_status i2ctu_read(enum ki2c_flags flags, enum itu_command startstopflags, uint16_t addr,
+enum itu_status i2ctu_dev_read(enum ki2c_flags flags, enum itu_command startstopflags, uint16_t addr,
         uint8_t* buf, size_t len) {
     bool nostop = !(startstopflags & ITU_CMD_I2C_IO_END);
     bool bit10  = flags & I2C_M_TEN;
@@ -440,7 +452,7 @@ enum itu_status i2ctu_read(enum ki2c_flags flags, enum itu_command startstopflag
             return ITU_STATUS_ADDR_ACK;
     } else*/
     {
-        int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len, nostop, 1000 * 1000);
+        int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len, nostop, 400 * 1000);
         // printf("p le rv=%d buf=%02x ", rv, buf[0]);
         if (rv < 0 || (size_t)rv < len) return ITU_STATUS_ADDR_NAK;
         return ITU_STATUS_ADDR_ACK;

bsp/rp2040/m_default/pinout.h

@@ -1,11 +1,11 @@
-// vim: set et:
+// vim: set et ts=8:
 
 #ifndef PINOUT_H_
 #define PINOUT_H_
 
 // UART config
-#define PINOUT_UART_TX         4
-#define PINOUT_UART_RX         5
+#define PINOUT_UART_TX         8
+#define PINOUT_UART_RX         9
 #define PINOUT_UART_CTS       10
 #define PINOUT_UART_RTS       11
 #define PINOUT_UART_INTERFACE uart1
@@ -14,10 +14,12 @@
 // JTAG config
 #define PINOUT_JTAG_TCK    2  // == SWCLK
 #define PINOUT_JTAG_TMS    3  // == SWDIO
-#define PINOUT_JTAG_TDI    6
-#define PINOUT_JTAG_TDO    7
-#define PINOUT_JTAG_nTRST  8
-#define PINOUT_JTAG_nRESET 9
+#define PINOUT_JTAG_TDI    4
+#define PINOUT_JTAG_TDO    5  // == SWO
+#define PINOUT_JTAG_nTRST  6
+#define PINOUT_JTAG_nRESET 7
+#define PINOUT_JTAG_PIO_DEV pio0
+#define PINOUT_JTAG_SWO_DEV pio0
 
 // SPI config
 #define PINOUT_SPI_DEV  spi1
@@ -47,5 +49,40 @@
 #endif
 #endif /* PICOPROBE_LED */
 
+/*
+ * HARDWARE RESOURCE USAGE:
+ *
+ * IRQ:
+ *   DMA0	DAP-UART
+ *   UART1	DAP-UART
+ *
+ * DMA: (max. 12)
+ *   DAP-UART	2
+ *   SWO-UART	1
+ *   SWO-MC	1
+ *
+ * PIO:
+ *   PIO0: (max. 4 SM, max. 32 insn)
+ *     JTAG	1	6
+ *     SWD	1	11
+ *     SWO	2	6 (manchester) + 9 (uart)
+ *
+ *     PIO0 IS NOW FULL!
+ *   PIO1: (max. 4 SM, max. 32 insn)
+ *
+ * UART: stdio
+ *   0: stdio
+ *   1: USB-CDC/DAP-UART
+ *
+ * SPI:
+ *   1: SPI access
+ *
+ * I2C:
+ *   0: I2C access
+ *
+ * ADC:
+ *   temperature sensor
+ */
+
 #endif
 

bsp/rp2040/m_default/spi_serprog.c

@@ -0,0 +1,177 @@
+// vim: set et:
+
+#include <stdio.h>
+
+#include <hardware/clocks.h>
+#include <hardware/spi.h>
+#include <pico/binary_info.h>
+#include <pico/stdlib.h>
+
+#include "m_default/bsp-feature.h"
+#include "m_default/pinout.h"
+
+#include "m_default/serprog.h"
+
+static bool cs_asserted;
+
+static uint32_t freq;
+static enum serprog_flags sflags;
+static uint8_t bpw;
+
+void sp_spi_init(void) {
+    cs_asserted = false;
+
+    freq = 512*1000;  // default to 512 kHz
+    sflags = 0; // CPOL 0, CPHA 0, MSB first
+    bpw = 8;
+    spi_init(PINOUT_SPI_DEV, freq);
+
+    gpio_set_function(PINOUT_SPI_MISO, GPIO_FUNC_SPI);
+    gpio_set_function(PINOUT_SPI_MOSI, GPIO_FUNC_SPI);
+    gpio_set_function(PINOUT_SPI_SCLK, GPIO_FUNC_SPI);
+
+    // gpio_set_function(PINOUT_SPI_nCS, GPIO_FUNC_SIO);
+    gpio_init(PINOUT_SPI_nCS);
+    gpio_put(PINOUT_SPI_nCS, 1);
+    gpio_set_dir(PINOUT_SPI_nCS, GPIO_OUT);
+
+    bi_decl(bi_3pins_with_func(PINOUT_SPI_MISO, PINOUT_SPI_MOSI, PINOUT_SPI_SCLK, GPIO_FUNC_SPI));
+    bi_decl(bi_1pin_with_name(PINOUT_SPI_nCS, "SPI #CS"));
+}
+void sp_spi_deinit(void) {
+    cs_asserted = false;
+    sflags = 0;
+    freq = 512*1000;
+    bpw = 8;
+
+    gpio_set_function(PINOUT_SPI_MISO, GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_SPI_MOSI, GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_SPI_SCLK, GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_SPI_nCS , GPIO_FUNC_NULL);
+
+    gpio_set_dir(PINOUT_SPI_nCS, GPIO_IN);
+    gpio_disable_pulls(PINOUT_SPI_nCS);
+
+    spi_deinit(PINOUT_SPI_DEV);
+}
+
+uint32_t sp_spi_set_freq(uint32_t freq_wanted) {
+    freq = spi_set_baudrate(PINOUT_SPI_DEV, freq_wanted);
+    return freq;
+}
+
+static void apply_settings(void) {
+    /*spi_set_format(PINOUT_SPI_DEV, bpw,
+            (sflags & S_FLG_CPOL) ? SPI_CPOL_1 : SPI_CPOL_0,
+            (sflags & S_FLG_CPHA) ? SPI_CPHA_1 : SPI_CPHA_0,
+            SPI_MSB_FIRST);*/
+
+    hw_write_masked(&spi_get_hw(PINOUT_SPI_DEV)->cr0,
+              ((uint32_t)(bpw - 1) << SPI_SSPCR0_DSS_LSB)
+            | ((uint32_t)((sflags & S_FLG_CPOL) ? SPI_CPOL_1 : SPI_CPOL_0) << SPI_SSPCR0_SPO_LSB)
+            | ((uint32_t)((sflags & S_FLG_CPHA) ? SPI_CPHA_1 : SPI_CPHA_0) << SPI_SSPCR0_SPH_LSB)
+            | ((uint32_t)((sflags >> 2) & 3) << SPI_SSPCR0_FRF_LSB),
+        SPI_SSPCR0_DSS_BITS | SPI_SSPCR0_SPO_BITS | SPI_SSPCR0_SPH_BITS | SPI_SSPCR0_FRF_BITS
+    );
+}
+enum serprog_flags sp_spi_set_flags(enum serprog_flags flags) {
+    if ((flags & (3<<2)) == (3<<2)) flags &= ~(uint32_t)(3<<2); // change to moto if bad value
+
+    sflags = flags & ~S_FLG_LSBFST; // ignore LSB-first flag, we don't support it
+
+    apply_settings();
+
+    return sflags;
+}
+uint8_t sp_spi_set_bpw(uint8_t bpw_) {
+    bpw = bpw_;
+    if (bpw <  4) bpw =  4;
+    if (bpw > 16) bpw = 16;
+
+    apply_settings();
+
+    return bpw;
+}
+
+__attribute__((__const__)) const struct sp_spi_caps* sp_spi_get_caps(void) {
+    static struct sp_spi_caps caps = {
+        .freq_min = ~(uint32_t)0,
+        .freq_max = 0,
+        .num_cs = 1,
+        .min_bpw = 4,
+        .max_bpw = 16,
+        .caps = S_CAP_CPOL_HI | S_CAP_CPOL_LO | S_CAP_CPHA_HI | S_CAP_CPHA_LO
+            | S_CAP_STDSPI | S_CAP_MICROW | S_CAP_TISSP
+            | S_CAP_MSBFST | S_CAP_LSBFST | S_CAP_CSACHI
+    };
+
+    caps.freq_min = clock_get_hz(clk_peri) / 254;
+    caps.freq_max = clock_get_hz(clk_peri) /   1;
+
+    return &caps;
+}
+
+void __not_in_flash_func(sp_spi_cs_deselect)(uint8_t csflags) {
+    (void)csflags;
+
+    asm volatile("nop\nnop\nnop");  // idk if this is needed
+    gpio_put(PINOUT_SPI_nCS, 1);
+    asm volatile("nop\nnop\nnop");  // idk if this is needed
+    cs_asserted = false;
+}
+void __not_in_flash_func(sp_spi_cs_select)(uint8_t csflags) {
+    (void)csflags;
+
+    asm volatile("nop\nnop\nnop");  // idk if this is needed
+    gpio_put(PINOUT_SPI_nCS, 0);
+    asm volatile("nop\nnop\nnop");  // idk if this is needed
+    cs_asserted = true;
+}
+
+void __not_in_flash_func(sp_spi_op_begin)(uint8_t csflags) {
+    // sp_spi_cs_select(csflags);
+    (void)csflags;
+
+    if (!cs_asserted) {
+        asm volatile("nop\nnop\nnop");  // idk if this is needed
+        gpio_put(PINOUT_SPI_nCS, 0);
+        asm volatile("nop\nnop\nnop");  // idk if this is needed
+    }
+}
+void __not_in_flash_func(sp_spi_op_end)(uint8_t csflags) {
+    // sp_spi_cs_deselect(csflags);
+    (void)csflags;
+
+    if (!cs_asserted) {                 // YES, this condition is the intended one!
+        asm volatile("nop\nnop\nnop");  // idk if this is needed
+        gpio_put(PINOUT_SPI_nCS, 1);
+        asm volatile("nop\nnop\nnop");  // idk if this is needed
+    }
+}
+
+// TODO: use dma?
+void sp_spi_op_write(uint32_t write_len, const void* write_data) {
+    if (bpw > 8) {
+        spi_write16_blocking(PINOUT_SPI_DEV, (const uint16_t*)write_data, write_len >> 1);
+    } else {
+        spi_write_blocking(PINOUT_SPI_DEV, (const uint8_t*)write_data, write_len);
+    }
+}
+void sp_spi_op_read(uint32_t read_len, void* read_data) {
+    if (bpw > 8) {
+        spi_read16_blocking(PINOUT_SPI_DEV, 0, (uint16_t*)read_data, read_len >> 1);
+    } else {
+        spi_read_blocking(PINOUT_SPI_DEV, 0, (uint8_t*)read_data, read_len);
+    }
+}
+void sp_spi_op_read_write(uint32_t len, void* read_data,
+        const void* write_data) {
+    if (bpw > 8) {
+        spi_write16_read16_blocking(PINOUT_SPI_DEV, (const uint16_t*)write_data,
+                (uint16_t*)read_data, len >> 1);
+    } else {
+        spi_write_read_blocking(PINOUT_SPI_DEV, (const uint8_t*)write_data,
+                (uint8_t*)read_data, len);
+    }
+}
+

bsp/rp2040/m_default/swo_manchester_encoding.pio

@@ -0,0 +1,94 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program swo_manchester_tx
+.side_set 1 opt
+
+; Transmit one bit every 12 cycles. a '0' is encoded as a high-low sequence
+; (each part lasting half a bit period, or 6 cycles) and a '1' is encoded as a
+; low-high sequence.
+;
+; Side-set bit 0 must be mapped to the GPIO used for TX.
+; Autopull must be enabled -- this program does not care about the threshold.
+; The program starts at the public label 'start'.
+
+.wrap_target
+do_1:
+    nop         side 0 [5] ; Low for 6 cycles (5 delay, +1 for nop)
+    jmp get_bit side 1 [3] ; High for 4 cycles. 'get_bit' takes another 2 cycles
+do_0:
+    nop         side 1 [5] ; Output high for 6 cycles
+    nop         side 0 [3] ; Output low for 4 cycles
+public start:
+get_bit:
+    out x, 1               ; Always shift out one bit from OSR to X, so we can
+    jmp !x do_0            ; branch on it. Autopull refills the OSR when empty.
+.wrap
+
+% c-sdk {
+static inline void swo_manchester_tx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, 1u << pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+    pio_gpio_init(pio, pin);
+
+    pio_sm_config c = swo_manchester_tx_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, pin);
+    sm_config_set_out_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset + swo_manchester_tx_offset_start, &c);
+
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+.program swo_manchester_rx
+
+; Assumes line is idle low, first bit is 0
+; One bit is 12 cycles
+; a '0' is encoded as 10
+; a '1' is encoded as 01
+;
+; Both the IN base and the JMP pin mapping must be pointed at the GPIO used for RX.
+; Autopush must be enabled.
+; Before enabling the SM, it should be placed in a 'wait 1, pin` state, so that
+; it will not start sampling until the initial line idle state ends.
+
+start_of_0:            ; We are 0.25 bits into a 0 - signal is high
+    wait 0 pin 0       ; Wait for the 1->0 transition - at this point we are 0.5 into the bit
+    in y, 1 [8]        ; Emit a 0, sleep 3/4 of a bit
+    jmp pin start_of_0 ; If signal is 1 again, it's another 0 bit, otherwise it's a 1
+
+.wrap_target
+start_of_1:            ; We are 0.25 bits into a 1 - signal is 1
+    wait 1 pin 0       ; Wait for the 0->1 transition - at this point we are 0.5 into the bit
+    in x, 1 [8]        ; Emit a 1, sleep 3/4 of a bit
+    jmp pin start_of_0 ; If signal is 0 again, it's another 1 bit otherwise it's a 0
+.wrap
+
+% c-sdk {
+static inline void swo_manchester_rx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+
+    pio_sm_config c = swo_manchester_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    sm_config_set_in_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+
+    // X and Y are set to 0 and 1, to conveniently emit these to ISR/FIFO.
+    pio_sm_exec(pio, sm, pio_encode_set(pio_x, 1));
+    pio_sm_exec(pio, sm, pio_encode_set(pio_y, 0));
+    // Assume line is idle low, and first transmitted bit is 0. Put SM in a
+    // wait state before enabling. RX will begin once the first 0 symbol is
+    // detected.
+    pio_sm_exec(pio, sm, pio_encode_wait_pin(1, 0) | pio_encode_delay(2));
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}

bsp/rp2040/m_default/swo_uart_rx.pio

@@ -0,0 +1,94 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program swo_uart_rx_mini
+
+; Minimum viable 8n1 UART receiver. Wait for the start bit, then sample 8 bits
+; with the correct timing.
+; IN pin 0 is mapped to the GPIO used as UART RX.
+; Autopush must be enabled, with a threshold of 8.
+
+    wait 0 pin 0        ; Wait for start bit
+    set x, 7 [10]       ; Preload bit counter, delay until eye of first data bit
+bitloop:                ; Loop 8 times
+    in pins, 1          ; Sample data
+    jmp x-- bitloop [6] ; Each iteration is 8 cycles
+
+% c-sdk {
+#include "hardware/clocks.h"
+#include "hardware/gpio.h"
+
+static inline void swo_uart_rx_mini_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    gpio_pull_up(pin);
+
+    pio_sm_config c = swo_uart_rx_mini_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT, IN
+    // Shift to right, autopush enabled
+    sm_config_set_in_shift(&c, true, true, 8);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+.program swo_uart_rx
+
+; Slightly more fleshed-out 8n1 UART receiver which handles framing errors and
+; break conditions more gracefully.
+; IN pin 0 and JMP pin are both mapped to the GPIO used as UART RX.
+
+start:
+    wait 0 pin 0        ; Stall until start bit is asserted
+    set x, 7    [10]    ; Preload bit counter, then delay until halfway through
+bitloop:                ; the first data bit (12 cycles incl wait, set).
+    in pins, 1          ; Shift data bit into ISR
+    jmp x-- bitloop [6] ; Loop 8 times, each loop iteration is 8 cycles
+    jmp pin good_stop   ; Check stop bit (should be high)
+
+    irq 4 rel           ; Either a framing error or a break. Set a sticky flag,
+    wait 1 pin 0        ; and wait for line to return to idle state.
+    jmp start           ; Don't push data if we didn't see good framing.
+
+good_stop:              ; No delay before returning to start; a little slack is
+    push                ; important in case the TX clock is slightly too fast.
+
+
+% c-sdk {
+static inline void swo_uart_rx_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    gpio_pull_up(pin);
+
+    pio_sm_config c = swo_uart_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT, IN
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    // Shift to right, autopull disabled
+    sm_config_set_in_shift(&c, true, false, 32);
+    // Deeper FIFO as we're not doing any TX
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+
+    pio_sm_init(pio, sm, offset, &c);
+    //pio_sm_set_enabled(pio, sm, true);
+}
+
+static inline char swo_uart_rx_program_getc(PIO pio, uint sm) {
+    // 8-bit read from the uppermost byte of the FIFO, as data is left-justified
+    io_rw_8 *rxfifo_shift = (io_rw_8*)&pio->rxf[sm] + 3;
+    while (pio_sm_is_rx_fifo_empty(pio, sm))
+        tight_loop_contents();
+    return (char)*rxfifo_shift;
+}
+
+%}

bsp/rp2040/m_default/tempsensor.c

@@ -1,8 +1,9 @@
 // vim: set et:
 
-#include "tempsensor.h"
+#include "m_default/tempsensor.h"
 
 #include <hardware/adc.h>
+#include <hardware/resets.h>
 
 #define T_SLOPE (-0.001721f)
 #define T_BIAS  (0.706f)
@@ -26,6 +27,13 @@ void tempsense_dev_init(void) {
     adc_init();
     adc_set_temp_sensor_enabled(true);
 }
+void tempsense_dev_deinit(void) {
+    adc_set_temp_sensor_enabled(false);
+    // call init, as it resets the ADC control register
+    adc_init();
+    // we still need to disable it again afterwards, though
+    reset_block(RESETS_RESET_ADC_BITS);
+}
 // 8.4
 int16_t tempsense_dev_get_temp(void) {
     adc_select_input(4);  // select temp sensor

bsp/rp2040/m_isp/bsp-feature.h

@@ -0,0 +1,35 @@
+
+#ifndef BSP_FEATURE_M_ISP_H_
+#define BSP_FEATURE_M_ISP_H_
+
+#define DBOARD_HAS_UART
+#define DBOARD_HAS_CMSISDAP
+#define DBOARD_HAS_MEHFET
+
+#include "bsp-info.h"
+
+enum {
+    HID_N_CMSISDAP = 0,
+
+    HID_N__NITF
+};
+enum {
+    CDC_N_UART = 0,
+#ifdef USE_USBCDC_FOR_STDIO
+    CDC_N_STDIO,
+#endif
+
+    CDC_N__NITF
+};
+enum {
+    VND_N_CMSISDAP = 0,
+#if CFG_TUD_VENDOR > 0
+    VND_N_CFG,
+#endif
+    VND_N_MEHFET,
+
+    VND_N__NITF
+};
+
+#endif
+

bsp/rp2040/m_isp/mehfet_hw.c

@@ -0,0 +1,205 @@
+// vim: set et:
+
+#include <hardware/gpio.h>
+#include <hardware/timer.h>
+#include <pico/time.h>
+
+#include "util.h"
+#include "m_isp/pinout.h"
+#include "m_isp/sbw_hw.h"
+
+#include "m_isp/mehfet.h"
+
+void mehfet_hw_delay_ms(uint32_t t) { busy_wait_ms   (t); }
+void mehfet_hw_delay_us(uint32_t t) { busy_wait_us_32(t); }
+
+static absolute_time_t target;
+void mehfet_hw_timer_start(bool us, uint32_t to_reach) {
+    target = us ? make_timeout_time_us(to_reach) : make_timeout_time_ms(to_reach);
+}
+bool mehfet_hw_timer_reached(void) { return time_reached(target); }
+
+
+void mehfet_hw_init(void) {
+    // don't init things just yet: PIO SM1 probably needs to be shared between
+    // multiple ISP/ICE/... protocols, so we only init stuff once actually starting
+
+    // TODO: init pin gpio mux stuff (to GPIO and not PIO first!)
+    //    ^: or not: this will probably keep the target into reset, maybe not
+    //       desired...
+}
+void mehfet_hw_deinit(void) {
+    // shrug
+    sbw_deinit(); // can't hurt
+
+    gpio_set_function(PINOUT_SBW_TCK , GPIO_FUNC_NULL);
+    gpio_set_function(PINOUT_SBW_TDIO, GPIO_FUNC_NULL);
+}
+
+__attribute__((__const__))
+enum mehfet_caps mehfet_hw_get_caps(void) {
+    // only support SBW for now. we could add JTAG, but this will probably
+    // become messy very quickly, as it's behind CMSIS-DAP. implement later
+    // if someone needs it.
+    return mehfet_cap_sbw_entryseq |
+        mehfet_cap_has_reset_tap | mehfet_cap_has_irshift | mehfet_cap_has_drshift;
+}
+
+const char* /*error string, NULL if no error*/ mehfet_hw_connect(enum mehfet_conn conn) {
+    sbw_preinit(conn & mehfet_conn_nrstmask);
+
+    if (!sbw_init()) {
+        mehfet_hw_deinit();
+        return "SBW PIO init failed";
+    }
+
+    return NULL;
+}
+void mehfet_hw_disconnect(void) {
+    sbw_deinit();
+}
+
+void mehfet_hw_set_clkspeed(bool fast) {
+    if (fast) {
+        sbw_set_freq(true, 350e3);
+    } else {
+        sbw_set_freq(false, 50e3);
+    }
+}
+uint8_t mehfet_hw_get_old_lines(void) {
+    return (sbw_get_last_tclk() ? 1 : 0)
+         | (sbw_get_last_tms () ? 2 : 0)
+         | (sbw_get_last_tdi () ? 4 : 0);
+}
+
+void mehfet_hw_tdio_seq(uint32_t ncyc, bool tmslvl, const uint8_t* tdi, uint8_t* tdo) {
+    sbw_sequence(ncyc, tmslvl, tdi, tdo);
+}
+void mehfet_hw_tms_seq(uint32_t ncyc, bool tdilvl, const uint8_t* tms) {
+    sbw_tms_sequence(ncyc, tdilvl, tms);
+}
+void mehfet_hw_tclk_edge(bool newtclk) {
+    sbw_clrset_tclk(newtclk);
+}
+void mehfet_hw_tclk_burst(uint32_t ncyc) {
+    sbw_tclk_burst(ncyc);
+}
+
+enum mehfet_resettap_status mehfet_hw_reset_tap(enum mehfet_resettap_flags flags) {
+    enum mehfet_resettap_status rv = 0;
+
+    if (flags & mehfet_rsttap_do_reset) {
+        // TDI always 1
+        // TMS=1,1,1,1,1,1    -- reset TAP state to initial
+        // TMS=0              -- test-logic-reset to run-test/idle
+        // TMS=1,0,1,0,1      -- perform fuse check
+        // TMS=1,0            -- back to run-test/idle (needed for SBW only)
+
+        //const uint16_t tms_seq = 0x1abf;//0x3f | (0<<6) | (0x15 << 7) | (0x1 << 12);
+        const uint8_t tms_seq[2] = {0xbf,0x1a};
+        sbw_tms_sequence(14, true, tms_seq);
+    }
+
+    if (flags & mehfet_rsttap_fuse_do) {
+        // TDI always 1
+        // TMS=01010110 // same sequence as above, but without TAP reset
+        const uint8_t tms_seq = 0x6a;
+        sbw_tms_sequence(8, true, &tms_seq);
+    }
+
+    if (flags & mehfet_rsttap_fuse_read) {
+        for (size_t i = 0; i < 3; ++i) {
+            mehfet_hw_shift_ir(0x14); // CNTRL_SIG_CAPTURE
+            uint16_t dr = mehfet_hw_shift_dr16(0xaaaa);
+            if (dr == 0x5555) {
+                rv |= mehfet_rsttap_fuse_blown;
+                break;
+            }
+        }
+    }
+
+    return rv;
+}
+
+uint8_t mehfet_hw_shift_ir(uint8_t newir) {
+    // 1100: run-test/idle -> select-dr-scan -> select-ir-scan -> capture-ir -> shift-ir
+    const uint8_t tms_seqa = 0x03;
+    const uint8_t tms_seqb = 0x03 >> 1;
+    sbw_tms_sequence(1, sbw_get_last_tclk(), &tms_seqa);
+    sbw_tms_sequence(3, true, &tms_seqb);
+
+    // 7 data bits with TMS=0
+    // 1 data bit with TMS=1 (to exit1-ir)
+    uint8_t res = 0, resb = 0, newir2 = newir >> 7;
+    sbw_sequence(7, false, &newir , &res );
+    sbw_sequence(1, true , &newir2, &resb);
+    res |= resb << 7;
+
+    // TMS=1 (to update-ir)
+    // TMS=0 (to run-test/idle)
+    const uint8_t tms_seq_2a = 0x01;
+    const uint8_t tms_seq_2b = 0x01 >> 1;
+    sbw_tms_sequence(1, true, &tms_seq_2a);
+    sbw_tms_sequence(1, sbw_get_last_tclk(), &tms_seq_2b);
+
+    return bitswap(res); // fsr also needed here
+}
+
+static void bitswap_n(uint32_t nbytes, uint8_t* data) {
+    for (uint32_t i = 0, j = nbytes - 1; i < nbytes; ++i, --j) {
+        if (i == j) data[i] = bitswap(data[i]);
+        else {
+            uint8_t tmp = bitswap(data[i]);
+            data[i] = bitswap(data[j]);
+            data[j] = tmp;
+        }
+    }
+}
+
+void mehfet_hw_shift_dr(uint32_t nbits, uint8_t* drin, uint8_t* drout) {
+    // 100: run-test/idle -> select-dr-scan -> capture-dr -> shift-dr
+    const uint8_t tms_seqa = 0x01;
+    const uint8_t tms_seqb = 0x01 >> 1;
+    sbw_tms_sequence(1, sbw_get_last_tclk(), &tms_seqa);
+    sbw_tms_sequence(2, true, &tms_seqb);
+
+    if (nbits == 16) { // fast path: DR is often 16 bits wide
+        // DR content is MSB-first instead of LSB-first (IR is the latter)
+        uint16_t newdr = bitswap(drin[1]) | ((uint16_t)bitswap(drin[0]) << 8);
+
+        // 15 data bits with TMS=0
+        // 1 data bit with TMS=1 (to exit1-dr)
+        uint16_t res = 0;
+        uint8_t newdr2 = newdr >> 15, resb = 0;
+        // this is little-endian-only, but that's fine on the rp2040
+        sbw_sequence(15, false, (const uint8_t*)&newdr, (uint8_t*)&res);
+        sbw_sequence( 1, true , &newdr2, &resb);
+        res |= (uint16_t)resb << 15;
+
+        drout[0] = bitswap(res >> 8);
+        drout[1] = bitswap(res & 0xff);
+    } else {
+        uint32_t nbytes = (nbits + 7) >> 3;
+
+        // DR content is MSB-first instead of LSB-first (IR is the latter)
+        bitswap_n(nbytes, drin);
+
+        // n-1 data bits with TMS=0
+        // 1 data bit with TMS=1 (to exit1-dr)
+        uint8_t newdr2, resb = 0;
+        newdr2 = drin[nbytes - 1] >> ((nbits - 1) & 7);
+        sbw_sequence(nbits - 1, false, drin, drout);
+        sbw_sequence(1, true , &newdr2, &resb);
+        drout[nbytes - 1] |= resb << ((nbits - 1) & 7);
+
+        bitswap_n(nbytes, drout);
+    }
+
+    // TMS=1 (to update-dr)
+    // TMS=0 (to run-test/idle)
+    const uint8_t tms_seq_2a = 0x01;
+    const uint8_t tms_seq_2b = 0x01 >> 1;
+    sbw_tms_sequence(1, true, &tms_seq_2a);
+    sbw_tms_sequence(1, sbw_get_last_tclk(), &tms_seq_2b);
+}
+

bsp/rp2040/m_isp/pinout.h

@@ -0,0 +1,83 @@
+// vim: set et ts=8:
+
+#ifndef PINOUT_H_
+#define PINOUT_H_
+
+// NOTE NOTE NOTE: as mode2 shares some stuff with mode1 (CMSIS-DAP, UART),
+//                 make sure that pinouts are compatible etc.
+
+// UART config
+#define PINOUT_UART_TX         8
+#define PINOUT_UART_RX         9
+/*#define PINOUT_UART_CTS       10
+#define PINOUT_UART_RTS       11*/
+#define PINOUT_UART_INTERFACE uart1
+#define PINOUT_UART_BAUDRATE  115200
+
+// JTAG config
+#define PINOUT_JTAG_TCK    2  // == SWCLK
+#define PINOUT_JTAG_TMS    3  // == SWDIO
+#define PINOUT_JTAG_TDI    4
+#define PINOUT_JTAG_TDO    5
+#define PINOUT_JTAG_nTRST  6
+#define PINOUT_JTAG_nRESET 7
+#define PINOUT_JTAG_PIO_DEV pio0
+#define PINOUT_JTAG_SWO_DEV pio0
+
+// SBW config
+#define PINOUT_SBW_PIO pio1
+#define PINOUT_SBW_TCK  10
+#define PINOUT_SBW_TDIO 11
+
+// LED config
+
+// you can change these two as you like
+#define PINOUT_LED_CONNECTED 1
+#define PINOUT_LED_RUNNING   0
+
+#ifndef PINOUT_LED
+#ifndef PICO_DEFAULT_LED_PIN
+#error "PICO_DEFAULT_LED_PIN is not defined, run PICOPROBE_LED=<led_pin> cmake"
+#elif PICO_DEFAULT_LED_PIN == -1
+#error "PICO_DEFAULT_LED_PIN is defined as -1, run PICOPROBE_LED=<led_pin> cmake"
+#else
+#define PINOUT_LED PICO_DEFAULT_LED_PIN
+#endif
+#endif /* PICOPROBE_LED */
+
+/*
+ * HARDWARE RESOURCE USAGE:
+ *
+ * IRQ:
+ *   DMA0	DAP-UART
+ *   UART1	DAP-UART
+ *
+ * DMA: (max. 12)
+ *   DAP-UART	2
+ *   SWO-UART	1
+ *   SWO-MC	1
+ *
+ * PIO:
+ *   PIO0: (max. 4 SM, max. 32 insn)
+ *     JTAG	1	6
+ *     SWD	1	11
+ *     SWO	2	6 (manchester) + 9 (uart)
+ *
+ *     PIO0 IS NOW FULL!
+ *   PIO1: (max. 4 SM, max. 32 insn)
+ *     SBW	1	32
+ *
+ * UART: stdio
+ *   0: stdio
+ *   1: USB-CDC/DAP-UART
+ *
+ * SPI:
+ *
+ * I2C:
+ *
+ * ADC:
+ *
+ */
+
+#endif
+

bsp/rp2040/m_isp/sbw.pio

@@ -0,0 +1,206 @@
+
+.program sbw
+.side_set 1
+
+; Pin assignments:
+; - SBWTCK is side-set pin 0
+; - SBWTDIO is OUT/IN pin 0
+;
+; Autopush and autopull must be enabled, set to 8
+; SBWTDIO input should not be guarded with sync flipflops, as TDO xfers are synchronous
+
+PUBLIC start:
+    ; SBWTCK hi to not lose/reset debug mode
+    pull                        side 1 ; clear leftover OSR bits, pull in new data
+startloop:
+    out exec, 16                side 1 ; use for set y, 0/1 ; in x, num ; jmp addr
+    jmp startloop               side 1
+
+; "subroutine" "calling convention"
+; * set y, 0/1 : initial TMS (sbw_seq) / TDI (sbw_tms_seq) / TCLK (sbw_tclk_burst) value
+; * in  x, num : number of JTAG cycles (sbw_seq/sbw_tms_seq) / TCLK half-cycles (sbw_tclk_burst)
+; * jmp subroutine
+; * ^ all 'side 1'
+
+; y: static TMS value to use
+; x: number of JTAG clock cycles minus one
+; TDI output gets sourced bit by bit from the TX FIFO
+; TDO input gets sent bit by bit to the RX FIFO
+PUBLIC sbw_seq:
+sbw_seq_iter:
+    ; tms slot:
+        set pindirs, 1          side 1      ; SBWTDIO is now output
+        mov pins,    y          side 1      ; output static TMS value
+        nop                     side 0 [1]  ; target reads TMS at falling edge
+    ; tdi slot:
+        out pins, 1             side 1 [1]  ; output TDI from FIFO
+        nop                     side 0 [1]  ; target reads TDI at falling edge
+    ; tdo slot:
+        set pindirs, 0          side 1 [1]  ; we need some clock pulse
+        nop                     side 0      ; give target some time to drive IO
+        in pins, 1              side 0      ; input TDO
+
+        jmp x--, sbw_seq_iter   side 1      ; also gives target some time to stop driving IO
+        ; NOTE: there's a glitch: if TMS=TDO!=TDI and !=TDI_next,
+        ;       then there's a short glitch (wrong voltage level) in the
+        ;       TDO->TMS high clock phase. it's benign.
+
+    push                        side 1      ; flush ISR
+    jmp start                   side 1
+
+
+; y: static TDI value to use
+; x: number of JTAG clock cycles minus one
+; TMS output gets sourced bit by bit from the TX FIFO
+PUBLIC sbw_tms_seq:
+    ; tms slot
+        set pindirs, 1          side 1      ; SBWTDIO is now output
+        out pins, 1             side 1      ; output TMS from FIFO
+        nop                     side 0 [1]  ; target reads TMS at falling edge
+    ; tdi slot
+        mov pins, y             side 1 [1]  ; output static TDI value
+        nop                     side 0 [1]  ; target reads TDI at falling edge
+    ; tdo slot
+        set pindirs, 0          side 1 [1]
+        jmp x--, sbw_tms_seq    side 0 [1]  ; ignore returned TDO, go back
+
+    jmp start                   side 1
+
+
+; stationary SBWTCK values are:
+;             jmp
+; TMS TDI TDO |TMS TDI TDO
+; |   |   |   ||   |   |
+; 1100110011001110011001100 ...
+;
+; a full cycle takes 13 cycles, a single slot 4
+; the SM divider should be sysclk/(4*baudrate)
+; baudrate shouldn't exceed 20 MHz (typical value is 18 MHz?)
+; SBWTCK LOW phases shouldn't exceed 7us, so the baudrate should be at least 40 kHz
+
+; y: initial/previous TCLK value
+; x: number of TCLK *half*-cycles minus one!
+; TCLK values get sourced from the TX FIFO. best is to use a DMA with fixed
+;      source address, with value 0x55/0xaa (depending on y) for strobes, or
+;      0x00/0xff (and x=0) for a single set/clear.
+; alternatively, one could set the "load-bearing instruction" to a
+; "set pins, 0/1 side 1 [12]" for a fixed value useful for single sets/clears
+PUBLIC sbw_tclk_burst:
+        set pindirs, 1          side 1     ; SBWTDIO is now output
+    ; tms slot:
+        set pins,   0           side 1     ; stay in run-test/idle TAP state
+        nop                     side 0     ; target reads TMS at falling edge
+        mov pins,   y           side 0     ; during low phase, prepare TCLK
+    ; tdi slot:
+        nop                     side 1 [6] ; wait a bit
+    burst_loop:
+;PUBLIC sbw_tclk_burst_loadbearing_insn:
+        out pins, 1             side 1 [6] ; in the middle of TDI hiphase: do TCLK
+        jmp x--, burst_loop     side 1 [6]
+        nop                     side 0 [1] ; need a low clock edge for TDO
+    ; tdo slot:
+        set pindirs, 0          side 1 [1]
+        nop                     side 0 [1]
+
+   ;jmp start                   side 1 ; not needed because of wrapping
+; 32 insns -- filling one entire PIO instruction memory
+
+; TODO: update this paragraph
+; a full TCLK cycle in this burst mode takes 24 PIOSM cycles. at a "standard"
+; baudrate of 18 MHz, this ends up being 375 kHz, which is in the required
+; range when doing eg. flash programming. at the max baudrate (20 MHz), the
+; TCLK speed is 417 kHz, which is still ok. max TCLK would be, if PIOSM freq is
+; 125 MHz, 2.6 MHz, which is good enough imo
+; TODO: determine minimum baudrate for stable TCLK (12 MHz?)
+
+
+% c-sdk {
+static inline void sbw_pio_init(PIO pio, uint sm, uint prog_offs,
+        float freq, uint pin_sbwclk, uint pin_sbwio) {
+    if (freq < 72e3) freq = 72e3;
+    if (freq > 20e6) freq = 20e6;
+
+    pio_sm_set_enabled(pio, sm, false);
+
+    pio_sm_config c = sbw_program_get_default_config(prog_offs);
+    sm_config_set_out_pins(&c, pin_sbwio, 1);
+    sm_config_set_set_pins(&c, pin_sbwio, 1);
+    sm_config_set_in_pins(&c, pin_sbwio);
+    sm_config_set_sideset_pins(&c, pin_sbwclk);
+    sm_config_set_out_shift(&c, false, true, 8);
+    sm_config_set_in_shift(&c, false, true, 8);
+    sm_config_set_clkdiv(&c, (float)clock_get_hz(clk_sys) / (4 * freq));
+    pio_sm_init(pio, sm, prog_offs, &c);
+
+    // SBWTDIO is low, SBWTCK is high, SBWTDIO is input by default
+    pio_sm_set_pindirs_with_mask(pio, sm,
+            (1u << pin_sbwclk) | (1u << pin_sbwio), (1u << pin_sbwclk) | (1u << pin_sbwio));
+
+    // need to do an extra set with sideset to make sure clk stays high and
+    // there's no glitch
+    pio_sm_exec(pio, sm, pio_encode_set(pio_pins, 1) | pio_encode_sideset(1, 1));
+
+    // SBW is mostly synchronous, bypass input synchroniser to reduce delay
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_sbwio);
+
+    gpio_set_pulls(pin_sbwio, false, true); // SBWTDIO is pulldn
+
+    pio_sm_set_enabled(pio, sm, true);
+
+    // set padsbank func to PIO *after* initing PIO, otherwise a glitch occurs
+    pio_gpio_init(pio, pin_sbwclk);
+    pio_gpio_init(pio, pin_sbwio );
+}
+
+// meant for sbw_seq/sbw_tms_seq
+static inline void sbw_pio_set_baudrate(PIO pio, uint sm, float freq) {
+    if (freq < 72e3) freq = 72e3;
+    if (freq > 20e6) freq = 20e6;
+
+    pio_sm_set_clkdiv(pio, sm, (float)clock_get_hz(clk_sys) / (4 * freq));
+}
+
+// meant for sbw_tclk_burst
+static inline void sbw_pio_set_tclkfreq(PIO pio, uint sm, float freq) {
+    if (freq < 250e3) freq = 250e3;
+    if (freq > 450e3) freq = 450e3;
+
+    pio_sm_set_clkdiv(pio, sm, (float)clock_get_hz(clk_sys) / (24 * freq));
+}
+
+static inline uint16_t sbw_pio_gen_setx(uint x) {
+    return pio_encode_set(pio_x, x) | pio_encode_sideset(1, 1) | (1<<12);
+}
+static inline uint16_t sbw_pio_gen_sety(uint y) {
+    return pio_encode_set(pio_y, y) | pio_encode_sideset(1, 1) | (1<<12);
+}
+static inline uint16_t sbw_pio_gen_outx(uint bits) {
+    return pio_encode_out(pio_x, bits) | pio_encode_sideset(1, 1) | (1<<12);
+}
+// subroutine is one of "sbw_offset_sbw_seq", "sbw_offset_sbw_tms_seq", "sbw_offset_sbw_tclk_burst"
+static inline uint16_t sbw_pio_gen_jmp(uint subroutine) {
+    return pio_encode_jmp(subroutine) | pio_encode_sideset(1, 1) | (1<<12);
+}
+
+/*static inline uint16_t sbw_pio_loadbearing_gen_outpins(void) {
+    return pio_encode_out(pio_pins, 1) | pio_encode_sideset(1, 1) | pio_encode_delay(12) | (1<<12);
+}
+static inline uint16_t sbw_pio_loadbearing_gen_setpins(uint value) {
+    return pio_encode_set(pio_pins, value) | pio_encode_sideset(1, 1) | pio_encode_delay(12) | (1<<12);
+}
+
+static inline void sbw_pio_loadbearing_set_outpins(PIO pio) {
+    pio->instr_mem[sbw_offset_sbw_tclk_burst_loadbearing_insn] =
+        sbw_pio_loadbearing_gen_outpins();
+}
+static inline void sbw_pio_loadbearing_set_setpins(PIO pio, uint value) {
+    pio->instr_mem[sbw_offset_sbw_tclk_burst_loadbearing_insn] =
+        sbw_pio_loadbearing_gen_setpins(value);
+}*/
+
+/*static inline bool sbw_pio_is_idle(PIO pio, uint sm, uint offset) {
+    return pio_sm_get_pc(pio, sm) < sbw_offset_sbw_seq + offset;
+}*/
+
+%}
+

bsp/rp2040/m_isp/sbw_hw.c

@@ -0,0 +1,335 @@
+// vim: set et:
+
+#include <stdio.h>
+
+#include <hardware/clocks.h>
+#include <hardware/dma.h>
+#include <hardware/gpio.h>
+#include <hardware/pio.h>
+#include <hardware/pio_instructions.h>
+#include <hardware/timer.h>
+
+#include "m_isp/pinout.h"
+#include "m_isp/sbw_hw.h"
+
+#include "sbw.pio.h"
+
+void sbw_preinit(bool nrst) {
+    //SLAU320AJ 2.3.1.1 ; SLAS722G p36:
+    // TEST/SBWTCK low for >100 us: reset debug state
+    // set nRST/NMI/SBWTDIO low: avoid sending an NMI when the debugger detaches
+    // TEST/SBWTCK high for >1 us : signal that we want a debugger
+    // nRST/NMI/SBWTDIO high: we want SBW
+    // TEST low for >0.025us <7us: latch on "we want SBW" signal
+    // TEST high again for >1 us: ready to SBW
+
+    // old impl, doesn't work, don't use
+    /*// TCK, TDIO now low
+    busy_wait_ms(4);//busy_wait_us_32(150); // reset debug state while keeping CPU in reset
+
+    gpio_put(PINOUT_SBW_TCK , true ); // we want a debugger
+    busy_wait_us_32(1);
+    gpio_put(PINOUT_SBW_TDIO, true ); // we want SBW
+    busy_wait_ms(20);//busy_wait_us_32(1);
+    gpio_put(PINOUT_SBW_TCK , false); // latch "we want SBW"
+    busy_wait_us_32(3);
+    gpio_put(PINOUT_SBW_TCK , true ); // start SBW stuff
+    busy_wait_ms(5);//busy_wait_us_32(100); // wait a bit more*/
+
+#if 1
+    (void)nrst; // always assumed nrst=false here :/
+    // from slau320 sources
+    //gpio_put(PINOUT_SBW_TCK , false);
+    gpio_put(PINOUT_SBW_TDIO, true ); // FIXME: ummmm TCK ???
+    gpio_put(PINOUT_SBW_TDIO, false);
+    gpio_set_dir(PINOUT_SBW_TCK , true);
+    gpio_set_dir(PINOUT_SBW_TDIO, true);
+    gpio_set_function(PINOUT_SBW_TCK , GPIO_FUNC_SIO);
+    gpio_set_function(PINOUT_SBW_TDIO, GPIO_FUNC_SIO);
+
+    gpio_put(PINOUT_SBW_TCK , false);
+    gpio_put(PINOUT_SBW_TDIO, true);
+    busy_wait_ms(4); // reset TEST logic
+    gpio_put(PINOUT_SBW_TDIO, true);
+    busy_wait_us_32(1);
+    gpio_put(PINOUT_SBW_TCK , true);
+    busy_wait_ms(20); // activate TEST logic
+
+    // "phase 1"
+    gpio_put(PINOUT_SBW_TDIO, true);
+    busy_wait_us_32(60);
+
+    // "phase 2"
+    gpio_put(PINOUT_SBW_TCK , false);
+
+    // "phase 3"
+    busy_wait_us_32(1);
+
+    // "phase 4"
+    gpio_put(PINOUT_SBW_TCK , true);
+    busy_wait_us_32(60);
+
+    // "phase 5"
+    busy_wait_ms(5);
+
+
+    //// new impl:
+#else
+    // from MSP430.DLL 'BIOS' (FETUIF?) sources
+    // can handle SBW/JTAG selection and nRST stuff
+    // ... but it doesn't seem to work
+
+    // TEST = TCK
+    // nRESET = TDIO = NMI
+    gpio_put(PINOUT_SBW_TCK , true/*false*/); // tck = test
+    gpio_put(PINOUT_SBW_TDIO, nrst/*true*/);
+    gpio_set_dir(PINOUT_SBW_TCK , true);
+    gpio_set_dir(PINOUT_SBW_TDIO, true);
+    gpio_set_function(PINOUT_SBW_TCK , GPIO_FUNC_SIO);
+    gpio_set_function(PINOUT_SBW_TDIO, GPIO_FUNC_SIO);
+    busy_wait_ms(4/*1*/); // 4?
+
+    gpio_put(PINOUT_SBW_TDIO, nrst);
+    busy_wait_us_32(1);
+    gpio_put(PINOUT_SBW_TCK , true);
+    // activate test logic
+    busy_wait_ms(20/*100*/); // 20 should be ok here I think?
+
+    // "phase 1"
+    gpio_put(PINOUT_SBW_TDIO, true); // false here if you want JTAG
+    busy_wait_us_32(40); // 60?
+
+    // "phase 2"
+    gpio_put(PINOUT_SBW_TCK, false); // ??? // true for JTAG?
+
+    // "phase 3"
+    // something (TDIO hi?) to do if RSTLOW & JTAG?
+    busy_wait_us_32(1);
+
+    // "phase 4"
+    gpio_put(PINOUT_SBW_TCK , true); // ??? // false for JTAG?
+    busy_wait_us_32(40/*60*/); // 40 should be ok here I think?
+
+    // phase 5
+    // something (TDIO hi?) to do if RSTHIGH & JTAG?
+    busy_wait_ms(5);
+#endif
+}
+
+static int sbw_piosm = -1, sbw_offset = -1;
+
+static bool last_tclk = true;
+static uint8_t last_tdi = 0xff, last_tms = 0xff;
+
+bool sbw_init(void) {
+    if (sbw_piosm >= 0 || sbw_offset >= 0) return false;
+
+    if (!pio_can_add_program(PINOUT_SBW_PIO, &sbw_program)) return false;
+    sbw_offset = pio_add_program(PINOUT_SBW_PIO, &sbw_program);
+
+    sbw_piosm = pio_claim_unused_sm(PINOUT_SBW_PIO, false);
+    if (sbw_piosm < 0) {
+        pio_remove_program(PINOUT_SBW_PIO, &sbw_program, sbw_offset);
+        sbw_offset = -1;
+        return false;
+    }
+
+    // need to start at 50 kHz: fuse check needs TMS cycles with a low phase
+    // of at least 5us. 50 kHz is below the required time (the actual maximum
+    // frequency would be around 80 kHz), but the exact frequency doesn't
+    // matter much as we'll switch to a higher one once the check has been
+    // completed
+    sbw_pio_init(PINOUT_SBW_PIO, sbw_piosm, sbw_offset, 50e3,
+            PINOUT_SBW_TCK, PINOUT_SBW_TDIO);
+
+    last_tdi = last_tms = 0xff;
+    last_tclk = true;
+
+    return true;
+}
+
+void sbw_deinit(void) {
+    if (sbw_piosm >= 0) {
+        pio_sm_set_enabled(PINOUT_SBW_PIO, sbw_piosm, false);
+        pio_sm_unclaim(PINOUT_SBW_PIO, sbw_piosm);
+        sbw_piosm = -1;
+    }
+
+    if (sbw_offset >= 0) {
+        pio_remove_program(PINOUT_SBW_PIO, &sbw_program, sbw_offset);
+        sbw_offset = -1;
+    }
+}
+
+void sbw_set_freq(bool tclk, float freq) {
+    if (tclk) {
+        sbw_pio_set_tclkfreq(PINOUT_SBW_PIO, sbw_piosm, freq);
+    } else {
+        sbw_pio_set_baudrate(PINOUT_SBW_PIO, sbw_piosm, freq);
+    }
+}
+
+static uint8_t bitswap(uint8_t in) {
+    static const uint8_t lut[16] = {
+        0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
+        0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf
+    };
+
+    return (lut[in&0xf] << 4) | lut[in>>4];
+}
+
+#define piosm_txf(width) (*(io_wo_##width *)&PINOUT_SBW_PIO->txf[sbw_piosm])
+#define piosm_rxf(width) (*(io_ro_##width *)&PINOUT_SBW_PIO->rxf[sbw_piosm])
+#define piosm_txf_wait() while (pio_sm_is_tx_fifo_full(PINOUT_SBW_PIO, sbw_piosm)) tight_loop_contents()
+
+bool sbw_get_last_tms(void) { return last_tms; }
+bool sbw_get_last_tdi(void) { return last_tdi; }
+bool sbw_get_last_tclk(void) { return last_tclk; }
+
+void sbw_sequence(uint32_t ncyc, bool tms, const uint8_t* tdi, uint8_t* tdo) {
+    if (ncyc == 0) return;
+
+    uint32_t nbytes = (ncyc + 7) >> 3;
+    uint32_t last_shift = (8 - ncyc) & 7;
+
+    uint32_t txremain = nbytes,
+             rxremain = last_shift ? nbytes : (nbytes + 1);
+
+    // initial TMS value in y
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_sety(tms ? 1 : 0);
+
+    // number of cycles in x
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_outx(32);
+    piosm_txf_wait();
+    piosm_txf(32) = ncyc - 1;
+
+    // jmp to correct subroutine
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_jmp(sbw_offset_sbw_seq + sbw_offset);
+
+    for (size_t oi = 0, ii = 0; txremain || rxremain; tight_loop_contents()) {
+        if (txremain && !pio_sm_is_tx_fifo_full(PINOUT_SBW_PIO, sbw_piosm)) {
+            piosm_txf(8) = bitswap(tdi ? tdi[ii] : last_tdi);
+            --txremain;
+            ++ii;
+        }
+
+        if (rxremain && !pio_sm_is_rx_fifo_empty(PINOUT_SBW_PIO, sbw_piosm)) {
+            uint8_t ov = piosm_rxf(8);
+            --rxremain;
+
+            if (tdo && oi < nbytes) {
+                if (last_shift && oi == nbytes - 1) {
+                    tdo[oi] = bitswap(ov) >> last_shift;
+                } else {
+                    tdo[oi] = bitswap(ov);
+                }
+                ++oi;
+            }
+        }
+    }
+
+    //while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
+
+    if (tdi) last_tdi = (tdi[nbytes - 1] & (1 << (ncyc & 7))) ? 0xff : 0;
+    last_tms = tms ? 0xff : 0;
+}
+
+void sbw_tms_sequence(uint32_t ncyc, bool tdi, const uint8_t* tms) {
+    if (ncyc == 0 || !tms) return;
+
+    uint32_t nbytes = (ncyc + 7) >> 3;
+    uint32_t txremain = nbytes;
+
+    // initial TDI value in y
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_sety(tdi ? 1 : 0);
+
+    // number of cycles in x
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_outx(32);
+    piosm_txf_wait();
+    piosm_txf(32) = ncyc - 1;
+
+    // jmp to correct subroutine
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_jmp(sbw_offset_sbw_tms_seq + sbw_offset);
+
+    for (size_t ii = 0; txremain; tight_loop_contents()) {
+        if (txremain && !pio_sm_is_tx_fifo_full(PINOUT_SBW_PIO, sbw_piosm)) {
+            piosm_txf(8) = bitswap(tms[ii]);
+            --txremain;
+            ++ii;
+        }
+    }
+
+    //while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
+
+    last_tdi = tdi ? 0xff : 0;
+    last_tms = (tms[nbytes - 1] & (1 << (ncyc & 7))) ? 0xff : 0;
+}
+
+void sbw_clrset_tclk(bool value) {
+    //sbw_pio_loadbearing_set_setpins(PINOUT_SBW_PIO, value ? 1 : 0); // new value
+
+    // pre-TCLK value
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_sety(last_tclk ? 1 : 0);
+
+    // only one TCLK
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_setx(0);
+
+    // jmp to subroutine
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_jmp(sbw_offset_sbw_tclk_burst + sbw_offset);
+
+    // always use out pins, 1
+    piosm_txf_wait();
+    piosm_txf(8) = value ? 0xff : 0;
+
+    // wait until done
+    /*while ( sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
+    while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();*/
+
+    last_tclk = value;
+}
+
+void sbw_tclk_burst(uint32_t ncyc) {
+    //sbw_pio_loadbearing_set_outpins(PINOUT_SBW_PIO);
+
+    uint32_t txremain = ((ncyc + 7) >> 3) * 2 - 1;
+
+    // MSB-first
+    uint8_t pattern = last_tclk ? 0x55 : 0xaa;
+
+    // pre-TCLK value
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_sety(last_tclk ? 1 : 0);
+
+    // number of TCLK half-cycles in x
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_outx(32);
+    piosm_txf_wait();
+    piosm_txf(32) = ncyc*2 - 1;
+
+    // jmp to subroutine
+    piosm_txf_wait();
+    piosm_txf(16) = sbw_pio_gen_jmp(sbw_offset_sbw_tclk_burst + sbw_offset);
+
+    for (; txremain; tight_loop_contents()) {
+        if (txremain && !pio_sm_is_tx_fifo_full(PINOUT_SBW_PIO, sbw_piosm)) {
+            piosm_txf(8) = pattern;
+            --txremain;
+        }
+    }
+
+    // wait until done
+    /*while ( sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
+    while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();*/
+
+    // last_tclk doesn't change - always an even number of TCLK half-cycles
+}
+

bsp/rp2040/m_isp/sbw_hw.h

@@ -0,0 +1,38 @@
+
+#ifndef BSP_RP2040_SBW_HW_H
+#define BSP_RP2040_SBW_HW_H
+
+#include <stdint.h>
+#include <stdbool.h>
+/*#include <hardware/pio.h>*/
+
+/*#define PINOUT_SBW_PIO pio0
+#define PINOUT_SBW_TCK  8
+#define PINOUT_SBW_TDIO 9*/
+
+//extern int sbw_piosm, sbw_offset;
+
+// does the debug handshake/SBW setup thingy, call before sbw_init()
+void sbw_preinit(bool nrst);
+
+bool sbw_init(void);
+void sbw_deinit(void);
+
+void sbw_set_freq(bool tclk, float freq);
+
+bool sbw_get_last_tms(void);
+bool sbw_get_last_tdi(void);
+bool sbw_get_last_tclk(void);
+
+void sbw_sequence(uint32_t ncyc, bool tms, const uint8_t* tdi, uint8_t* tdo);
+void sbw_tms_sequence(uint32_t ncyc, bool tdi, const uint8_t* tms);
+
+void sbw_clrset_tclk(bool tclk);
+
+static inline void sbw_clr_tclk(void) { sbw_clrset_tclk(false); }
+static inline void sbw_set_tclk(void) { sbw_clrset_tclk(true ); }
+
+void sbw_tclk_burst(uint32_t ncyc);
+
+#endif
+

bsp/rp2040/m_jscan/bsp-feature.h

@@ -0,0 +1,29 @@
+
+#ifndef BSP_FEATURE_M_JSCAN_H_
+#define BSP_FEATURE_M_JSCAN_H_
+
+#define DBOARD_HAS_JSCAN
+
+#include "bsp-info.h"
+
+// not all that much here
+
+enum {
+    HID_N__NITF = 0
+};
+enum {
+#ifdef USE_USBCDC_FOR_STDIO
+    CDC_N_STDIO,
+#endif
+
+    CDC_N__NITF
+};
+enum {
+#if CFG_TUD_VENDOR > 0
+    VND_N_CFG = 0,
+#endif
+
+    VND_N__NITF
+};
+
+#endif

bsp/rp2040/m_jscan/jscan_hw.c

@@ -0,0 +1,34 @@
+
+#include <hardware/gpio.h>
+
+#include "m_jscan/jscan.h"
+#include "m_jscan/jscan_hw.h"
+
+inline static uint32_t get_mask(void) {
+    uint32_t mask = (1 << JSCAN_PIN_MAX) - 1;
+    if (JSCAN_PIN_MIN)
+        mask ^= (1 << (JSCAN_PIN_MIN - 1)) - 1;
+
+    return mask;
+}
+
+void jscan_pin_enable(void) {
+    //gpio_init_mask(get_mask());
+    for (uint8_t i = JSCAN_PIN_MIN; i <= JSCAN_PIN_MAX; ++i) {
+        gpio_set_function(i, GPIO_FUNC_SIO);
+        gpio_disable_pulls(i);
+        gpio_set_dir(i, 0);
+    }
+}
+
+void jscan_pin_disable(void) {
+    for (uint8_t i = JSCAN_PIN_MIN; i <= JSCAN_PIN_MAX; ++i) {
+        gpio_disable_pulls(i);
+        gpio_set_dir(i, 0);
+        gpio_set_function(i, GPIO_FUNC_NULL);
+    }
+
+    //gpio_set_dir_masked(get_mask(), 0); // all inputs
+}
+
+

bsp/rp2040/m_jscan/jscan_hw.h

@@ -0,0 +1,33 @@
+
+#ifndef BSP_RP2040_JSCAN_HW_H_
+#define BSP_RP2040_JSCAN_HW_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+#include <hardware/gpio.h>
+#include <pico/time.h>
+
+// inclusive
+#define JSCAN_PIN_MIN 2
+#define JSCAN_PIN_MAX 22
+
+inline static void jscan_delay_half_clk(void) { sleep_us(25); }
+
+inline static void jscan_pin_mode(uint8_t pin, int mode) {
+    gpio_set_dir(pin, mode == 1);
+    if (mode == 0) gpio_pull_up(pin);
+    else gpio_disable_pulls(pin);
+}
+inline static bool jscan_pin_get(uint8_t pin) {
+    bool r = gpio_get(pin);
+    //printf("get pin %d -> %c\n", pin, r?'1':'0');
+    return r;
+}
+inline static void jscan_pin_set(uint8_t pin, bool v) {
+    //printf("set pin %d = %c\n", pin, v?'1':'0');
+    gpio_put(pin, v);
+}
+
+#endif

bsp/rp2040/m_sump/bsp-feature.h

@@ -0,0 +1,28 @@
+
+#ifndef BSP_FEATURE_M_SUMP_H_
+#define BSP_FEATURE_M_SUMP_H_
+
+#define DBOARD_HAS_SUMP
+
+#include "bsp-info.h"
+
+enum {
+    HID_N__NITF = 0
+};
+enum {
+    CDC_N_SUMP = 0,
+#ifdef USE_USBCDC_FOR_STDIO
+    CDC_N_STDIO,
+#endif
+
+    CDC_N__NITF
+};
+enum {
+#if CFG_TUD_VENDOR > 0
+    VND_N_CFG = 0,
+#endif
+
+    VND_N__NITF
+};
+
+#endif

bsp/rp2040/m_sump/sump_hw.c

@@ -0,0 +1,399 @@
+
+#include <hardware/clocks.h>
+#include <hardware/dma.h>
+#include <hardware/irq.h>
+#include <hardware/pio.h>
+#include <hardware/pwm.h>
+#include <hardware/structs/bus_ctrl.h>
+#include <hardware/sync.h>
+#include <hardware/vreg.h>
+#include <pico/binary_info.h>
+#include <pico/platform.h>
+#include <pico/stdlib.h>
+#include <stdio.h>
+
+#include "bsp-info.h"
+#include "m_sump/sump.h"
+
+
+#include "m_sump/sump_hw.h"
+
+#define SAMPLING_GPIO_MASK (((1 << SAMPLING_BITS) - 1) << SAMPLING_GPIO_FIRST)
+
+#define SAMPLING_GPIO_TEST 22
+
+#define SAMPLING_PIO    pio1
+#define SAMPLING_PIO_SM 0u
+
+#define SAMPLING_DMA_IRQ DMA_IRQ_1
+#define sump_dma_ints    (dma_hw->ints1)
+
+#define sump_dma_set_irq_channel_mask_enabled dma_set_irq1_channel_mask_enabled
+
+#define SUMP_SAMPLE_MASK ((1 << SAMPLING_BITS) - 1)
+#define SUMP_BYTE0_OR    ((~SUMP_SAMPLE_MASK) & 0xff)
+#define SUMP_BYTE1_OR    ((~SUMP_SAMPLE_MASK >> 8) & 0xff)
+
+#define SUMP_DMA_CH_FIRST 0
+#define SUMP_DMA_CH_LAST  7
+#define SUMP_DMA_CHANNELS (SUMP_DMA_CH_LAST - SUMP_DMA_CH_FIRST + 1)
+#define SUMP_DMA_MASK     (((1 << SUMP_DMA_CHANNELS) - 1) << SUMP_DMA_CH_FIRST)
+
+#define sump_irq_debug(format, ...)  ((void)0)
+#define picoprobe_info(format, ...)  ((void)0)
+#define picoprobe_debug(format, ...) ((void)0)
+#define picoprobe_dump(format, ...)  ((void)0)
+
+static uint16_t prog[2];
+// clang-format off
+static const struct pio_program program = {
+    .instructions = prog,
+    .length = count_of(prog),
+    .origin = -1
+};
+// clang-format on
+
+static uint32_t pio_prog_offset;
+static uint32_t dma_curr_idx = 0;
+static uint32_t oldprio;
+
+static bool overclock = false;
+
+uint32_t sump_hw_get_sysclk(void) { return clock_get_hz(clk_sys); }
+
+void sump_hw_get_cpu_name(char cpu[32]) {
+    snprintf(cpu, 32, INFO_BOARDNAME " @ %lu MHz",
+            sump_hw_get_sysclk() / (ONE_MHZ * SAMPLING_DIVIDER));
+}
+void sump_hw_get_hw_name(char hw[32]) {
+    snprintf(hw, 32, INFO_BOARDNAME " rev%hhu, ROM v%hhu", rp2040_chip_version(),
+            rp2040_rom_version());
+}
+
+static void sump_pio_init(uint8_t width, bool nogr0) {
+    uint32_t gpio = SAMPLING_GPIO_FIRST;
+
+#if SAMPLING_BITS > 8
+    if (width == 1 && nogr0) gpio += 8;
+#endif
+    // loop the IN instruction forewer (8-bit and 16-bit version)
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_in_pins(&c, gpio);
+    uint32_t off = pio_prog_offset + (width - 1);
+    sm_config_set_wrap(&c, off, off);
+
+    uint32_t divider = sump_calc_sysclk_divider();
+    sm_config_set_clkdiv_int_frac(&c, divider >> 8, divider & 0xff);
+    sm_config_set_in_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+
+    pio_sm_init(SAMPLING_PIO, SAMPLING_PIO_SM, off, &c);
+    picoprobe_debug("%s(): pc=0x%02x [0x%02x], gpio=%u\n", __func__, off, pio_prog_offset, gpio);
+}
+
+static void sump_pio_program(void) {
+    prog[0] = pio_encode_in(pio_pins, 8);
+    prog[1] = pio_encode_in(pio_pins, 16);
+
+    picoprobe_debug("%s(): 0x%04x 0x%04x len=%u\n", __func__, prog[0], prog[1], program.length);
+    pio_prog_offset = pio_add_program(SAMPLING_PIO, &program);
+}
+
+static uint32_t sump_pwm_slice_init(uint32_t gpio, uint32_t clock, bool swap_levels) {
+    uint32_t clksys = sump_hw_get_sysclk();
+    uint16_t top = 5, level_a = 1, level_b = 4;
+
+    // correction for low speed PWM
+    while ((clksys / clock / top) & ~0xff) {
+        top *= 1000;
+        level_a *= 1000;
+        level_b *= 1000;
+    }
+
+    uint32_t clkdiv = clksys / clock / top;
+
+    // pwm setup
+    uint32_t slice = pwm_gpio_to_slice_num(gpio);
+    gpio_set_function(gpio, GPIO_FUNC_PWM);
+    gpio_set_function(gpio + 1, GPIO_FUNC_PWM);
+    pwm_config c = pwm_get_default_config();
+    pwm_config_set_wrap(&c, top - 1);
+    pwm_config_set_clkdiv_int(&c, clkdiv);
+    pwm_init(slice, &c, false);
+
+    if (swap_levels) {
+        uint16_t tmp = level_a;
+        level_a      = level_b;
+        level_b      = tmp;
+    }
+
+    pwm_set_both_levels(slice, level_a, level_b);
+    picoprobe_debug("%s(): gpio=%u clkdiv=%u top=%u level=%u/%u freq=%.4fMhz (req %.4fMhz)\n",
+            __func__, gpio, clkdiv, top, level_a, level_b,
+            (float)clksys / (float)clkdiv / (float)top / 1000000.0, (float)clock / 1000000.0);
+
+    return 1u << slice;
+}
+
+static uint32_t sump_calib_init(void) {
+    uint32_t       clksys = sump_hw_get_sysclk(), clkdiv, slice;
+    const uint32_t clock  = 5 * ONE_MHZ;
+    const uint16_t top = 10, level_a = 5;
+
+    // set 5Mhz PWM on test pin
+
+    // should not go beyond 255!
+    clkdiv = clksys / clock / top;
+
+    // pwm setup
+    slice = pwm_gpio_to_slice_num(SAMPLING_GPIO_TEST);
+    gpio_set_function(SAMPLING_GPIO_TEST, GPIO_FUNC_PWM);
+    pwm_config c = pwm_get_default_config();
+    pwm_config_set_wrap(&c, top - 1);
+    pwm_config_set_clkdiv_int(&c, clkdiv);
+    pwm_init(slice, &c, false);
+    pwm_set_both_levels(slice, level_a, level_a);
+    picoprobe_debug("%s(): gpio=%u clkdiv=%u top=%u level=%u/%u freq=%.4fMhz (req %.4fMhz)\n",
+            __func__, SAMPLING_GPIO_TEST, clkdiv, top, level_a, level_a,
+            (float)clksys / (float)clkdiv / (float)top / 1000000.0, (float)clock / 1000000.0);
+    return 1u << slice;
+}
+
+static uint32_t sump_test_init(void) {
+    // Initialize test PWMs
+    const uint32_t gpio = SAMPLING_GPIO_FIRST;
+    uint32_t       mask;
+    // 10Mhz PWM
+    mask = sump_pwm_slice_init(gpio, 10000000, false);
+    // 1Mhz PWM
+    mask |= sump_pwm_slice_init(gpio + 2, 1000000, false);
+    // 1kHz PWM
+    mask |= sump_pwm_slice_init(gpio + 4, 1000, false);
+#if SAMPLING_BITS > 8
+    // 1kHz PWM (second byte)
+    mask |= sump_pwm_slice_init(gpio + 8, 1000, true);
+#endif
+    return mask;
+}
+
+static void sump_test_done(void) {
+    const uint32_t gpio = SAMPLING_GPIO_FIRST;
+
+    pwm_set_enabled(pwm_gpio_to_slice_num(gpio), false);
+    pwm_set_enabled(pwm_gpio_to_slice_num(gpio + 2), false);
+    pwm_set_enabled(pwm_gpio_to_slice_num(gpio + 4), false);
+#if SAMPLING_BITS > 8
+    pwm_set_enabled(pwm_gpio_to_slice_num(gpio + 8), false);
+#endif
+    for (uint32_t i = SAMPLING_GPIO_FIRST; i <= SAMPLING_GPIO_LAST; i++)
+        gpio_set_function(i, GPIO_FUNC_NULL);
+    // test pin
+    pwm_set_enabled(SAMPLING_GPIO_TEST, false);
+}
+
+static void sump_dma_chain_to_self(uint32_t ch) {
+    dma_channel_config cfg;
+
+    ch += SUMP_DMA_CH_FIRST;
+    cfg = dma_get_channel_config(ch);
+    channel_config_set_chain_to(&cfg, ch);
+    dma_channel_set_config(ch, &cfg, false);
+}
+
+void sump_hw_capture_setup_next(
+        uint32_t ch, uint32_t mask, uint32_t chunk_size, uint32_t next_count, uint8_t width) {
+    if ((next_count % chunk_size) == 0) {
+        ch = (mask + dma_curr_idx - 1) % SUMP_DMA_CHANNELS;
+        sump_dma_chain_to_self(ch);
+        ch = (ch + 1) % SUMP_DMA_CHANNELS;
+    } else {
+        ch = (mask + dma_curr_idx) % SUMP_DMA_CHANNELS;
+        dma_channel_set_trans_count(
+                ch + SUMP_DMA_CH_FIRST, (next_count % chunk_size) / width, false);
+    }
+    sump_irq_debug("%s(): %u: t=0x%08x\n", __func__, ch + SUMP_DMA_CH_FIRST,
+            (next_count % chunk_size) / width);
+
+    // break chain, reset unused DMA chunks
+    // clear all chains for high-speed DMAs
+    mask = SUMP_DMA_CHANNELS - ((next_count + chunk_size - 1) / chunk_size);
+    while (mask > 0) {
+        sump_dma_chain_to_self(ch);
+        sump_irq_debug(
+                "%s(): %u -> %u\n", __func__, ch + SUMP_DMA_CH_FIRST, ch + SUMP_DMA_CH_FIRST);
+        ch = (ch + 1) % SUMP_DMA_CHANNELS;
+        mask--;
+    }
+}
+static void __isr sump_hw_dma_irq_handler(void) {
+    uint32_t loop = 0;
+
+    while (1) {
+        uint32_t ch   = SUMP_DMA_CH_FIRST + dma_curr_idx;
+        uint32_t mask = 1u << ch;
+
+        if ((sump_dma_ints & mask) == 0) break;
+
+        // acknowledge interrupt
+        sump_dma_ints = mask;
+
+        dma_curr_idx = (dma_curr_idx + 1) % SUMP_DMA_CHANNELS;
+
+        dma_channel_set_write_addr(ch, sump_capture_get_next_dest(SUMP_DMA_CHANNELS), false);
+        // sump_irq_debug("%s(): %u: w=0x%08x, state=%u\n", __func__, ch, sump_dma_get_next_dest(),
+        // sump.state);
+
+        sump_capture_callback(ch, SUMP_DMA_CHANNELS);
+
+        // are we slow?
+        if (++loop == SUMP_DMA_CHANNELS) {
+            sump_capture_callback_cancel();
+            break;
+        }
+    }
+}
+
+static void sump_dma_program(
+        uint32_t ch, uint32_t pos, uint8_t width, uint32_t chunk_size, uint8_t* destbuf) {
+    dma_channel_config cfg = dma_channel_get_default_config(SUMP_DMA_CH_FIRST + ch);
+    channel_config_set_read_increment(&cfg, false);
+    channel_config_set_write_increment(&cfg, true);
+    channel_config_set_dreq(&cfg, pio_get_dreq(SAMPLING_PIO, SAMPLING_PIO_SM, false));
+    channel_config_set_chain_to(&cfg, SUMP_DMA_CH_FIRST + ((ch + 1) % SUMP_DMA_CHANNELS));
+    channel_config_set_transfer_data_size(&cfg, width == 1 ? DMA_SIZE_8 : DMA_SIZE_16);
+
+    dma_channel_configure(SUMP_DMA_CH_FIRST + ch, &cfg, destbuf + pos,
+            &SAMPLING_PIO->rxf[SAMPLING_PIO_SM], chunk_size / width, false);
+
+    picoprobe_debug("%s() %u: w=0x%08x r=0x%08x t=0x%08x -> %u\n", __func__, SUMP_DMA_CH_FIRST + ch,
+            destbuf + pos, &SAMPLING_PIO->rxf[SAMPLING_PIO_SM], chunk_size / width,
+            SUMP_DMA_CH_FIRST + ((ch + 1) % SUMP_DMA_CHANNELS));
+}
+
+/*uint64_t*/ void sump_hw_capture_start(
+        uint8_t width, int flags, uint32_t chunk_size, uint8_t* destbuf) {
+    sump_pio_init(width, flags & SUMP_FLAG1_GR0_DISABLE);
+
+    dma_curr_idx = 0;
+
+    uint32_t pwm_mask = sump_calib_init();
+    if (flags & SUMP_FLAG1_EXT_TEST) {
+        pwm_mask |= sump_test_init();
+    } else {
+        sump_test_done();
+    }
+
+    for (uint32_t i = 0; i < SUMP_DMA_CHANNELS; i++)
+        sump_dma_program(i, i * chunk_size, width, chunk_size, destbuf);
+
+    // let's go
+    uint32_t irq_state = save_and_disable_interrupts();
+    pio_sm_set_enabled(SAMPLING_PIO, SAMPLING_PIO_SM, true);
+
+    if (pwm_mask) pwm_set_mask_enabled(pwm_mask);
+
+    dma_channel_start(SUMP_DMA_CH_FIRST);
+    irq_set_enabled(SAMPLING_DMA_IRQ, true);
+    restore_interrupts(irq_state);
+
+    // return time_us_64();
+}
+void sump_hw_capture_stop(void) {
+    pio_sm_set_enabled(SAMPLING_PIO, SAMPLING_PIO_SM, false);
+    irq_set_enabled(SAMPLING_DMA_IRQ, false);
+}
+
+void sump_hw_init(void) {
+    if (overclock) {
+        vreg_set_voltage(VREG_VOLTAGE_1_15);
+        set_sys_clock_khz(200000, true);
+    }
+
+    // claim DMA channels
+    dma_claim_mask(SUMP_DMA_MASK);
+
+    // claim PIO state machine and add program
+    pio_claim_sm_mask(SAMPLING_PIO, 1u << SAMPLING_PIO_SM);
+    sump_pio_program();
+
+    // high bus priority to the DMA
+    oldprio               = bus_ctrl_hw->priority;
+    bus_ctrl_hw->priority = BUSCTRL_BUS_PRIORITY_DMA_W_BITS | BUSCTRL_BUS_PRIORITY_DMA_R_BITS;
+
+    // GPIO init
+    gpio_set_dir_in_masked(SAMPLING_GPIO_MASK);
+    gpio_put_masked(SAMPLING_GPIO_MASK, 0);
+    for (uint32_t i = SAMPLING_GPIO_FIRST; i <= SAMPLING_GPIO_LAST; i++) {
+        gpio_set_function(i, GPIO_FUNC_NULL);
+        gpio_set_pulls(i, false, false);
+    }
+
+    // test GPIO pin
+    gpio_set_dir(SAMPLING_GPIO_TEST, true);
+    gpio_put(SAMPLING_GPIO_TEST, true);
+    gpio_set_function(SAMPLING_GPIO_TEST, GPIO_FUNC_PWM);
+
+    // set exclusive interrupt handler
+    irq_set_enabled(SAMPLING_DMA_IRQ, false);
+    irq_set_exclusive_handler(SAMPLING_DMA_IRQ, sump_hw_dma_irq_handler);
+    sump_dma_set_irq_channel_mask_enabled(SUMP_DMA_MASK, true);
+
+    /*bi_decl(bi_pin_mask_with_name(SAMPLING_GPIO_MASK, "SUMP logic analyzer input"));
+    bi_decl(bi_1pin_with_name(SAMPLING_GPIO_TEST, "SUMP logic analyzer: test PWM"));*/
+    bi_decl(bi_program_feature("Mode 4: SUMP"));
+}
+
+void sump_hw_stop(void) {
+    // IRQ and PIO fast stop
+    irq_set_enabled(SAMPLING_DMA_IRQ, false);
+    pio_sm_set_enabled(SAMPLING_PIO, SAMPLING_PIO_SM, false);
+
+    // DMA abort
+    for (uint32_t i = SUMP_DMA_CH_FIRST; i <= SUMP_DMA_CH_LAST; i++) dma_channel_abort(i);
+
+    // IRQ status cleanup
+    sump_dma_ints = SUMP_DMA_MASK;
+
+    // PIO cleanup
+    pio_sm_clear_fifos(SAMPLING_PIO, SAMPLING_PIO_SM);
+    pio_sm_restart(SAMPLING_PIO, SAMPLING_PIO_SM);
+
+    // test
+    sump_test_done();
+}
+
+void sump_hw_deinit(void) {
+    set_sys_clock_khz(133333, false);
+    vreg_set_voltage(VREG_VOLTAGE_DEFAULT);
+
+    sump_hw_stop();
+
+    sump_dma_set_irq_channel_mask_enabled(SUMP_DMA_MASK, false);
+
+    gpio_set_dir(SAMPLING_GPIO_TEST, false);
+    gpio_set_function(SAMPLING_GPIO_TEST, GPIO_FUNC_NULL);
+
+    bus_ctrl_hw->priority = oldprio;
+
+    pio_remove_program(SAMPLING_PIO, &program, pio_prog_offset);
+    pio_sm_unclaim(SAMPLING_PIO, SAMPLING_PIO_SM);
+
+    for (uint32_t i = SUMP_DMA_CH_FIRST; i <= SUMP_DMA_CH_LAST; ++i) dma_channel_unclaim(i);
+}
+
+uint8_t sump_hw_get_overclock(void) {
+    return overclock ? 1 : 0;
+}
+void sump_hw_set_overclock(uint8_t v) {
+    overclock = v != 0;
+
+    if (overclock) {
+        // TODO: make this configurable
+        vreg_set_voltage(VREG_VOLTAGE_1_15);
+        set_sys_clock_khz(200000, true);
+    } else {
+        set_sys_clock_khz(133333, false);
+        vreg_set_voltage(VREG_VOLTAGE_DEFAULT);
+    }
+}
+

bsp/rp2040/m_sump/sump_hw.h

@@ -0,0 +1,19 @@
+#ifndef BSP_SUMP_HW_PICO_H
+#define BSP_SUMP_HW_PICO_H
+
+#define SAMPLING_DIVIDER	4	// minimal sysclk sampling divider
+
+#define SAMPLING_GPIO_FIRST	6
+#define SAMPLING_GPIO_LAST	21
+
+#define SAMPLING_BITS		(SAMPLING_GPIO_LAST-SAMPLING_GPIO_FIRST+1)
+#define SAMPLING_BYTES		((SAMPLING_BITS+7)/8)
+
+//#if PICO_NO_FLASH
+//#define SUMP_MEMORY_SIZE	151552/*102400*/	// 150kB
+//#else
+//#define SUMP_MEMORY_SIZE	204800	// 200kB
+//#endif
+#define SUMP_MAX_CHUNK_SIZE	4096
+
+#endif

bsp/rp2040/protocfg.h

@@ -1,48 +0,0 @@
-// vim: set et:
-
-#ifndef PROTOCFG_H_
-#define PROTOCFG_H_
-
-#define DBOARD_HAS_UART
-#define DBOARD_HAS_CMSISDAP
-#define DBOARD_HAS_SERPROG
-#define DBOARD_HAS_I2C
-#define DBOARD_HAS_TEMPSENSOR
-
-enum {
-    HID_N_CMSISDAP = 0,
-
-    HID_N__NITF
-};
-enum {
-    CDC_N_UART = 0,
-    CDC_N_SERPROG,
-#ifdef USE_USBCDC_FOR_STDIO
-    CDC_N_STDIO,
-#endif
-
-    CDC_N__NITF
-};
-enum {
-    VND_N__NITF = 0
-};
-
-#define CFG_TUD_HID 1
-#ifdef USE_USBCDC_FOR_STDIO
-#define CFG_TUD_CDC 3
-#else
-#define CFG_TUD_CDC 2
-#endif
-#define CFG_TUD_VENDOR 0
-
-/*#define USB_VID 0x2e8a*/ /* Raspberry Pi */
-#define USB_VID 0xcafe     /* TinyUSB */
-/*#define USB_VID 0x1209*/ /* Generic */
-/*#define USB_VID 0x1d50*/ /* OpenMoko */
-#define USB_PID 0x1312
-
-// TODO: other RP2040 boards
-#define INFO_BOARDNAME "RP2040 Pico"
-
-#endif
-