The CH32F1 routine now reads the IDCode into a local.
If the part number matches and appears to be the chip (based on Flash locking), it only then writes the IDCode into `t->idcode`, which is at the point we can only `return true` from the probe routine anyway.
"Single" core STM32WLE still sees AP1 but on first scan aborts gracefully
after some errors and on later runs sees AP1 as unusable. Fixes#832.
Decode the Cross trigger interface found on CPU2 on STM32WBxx.
E.g on STM32WXXX AP1 with C2BOOT not set, the AP base registers have valid
values but reading them fails and turns the AP unusable. BMDA reading CIDR
with multiple calls will will loop and finally hang up BMD. Other target
devices may show similar behaviour.
Reading CIDR with a single call allows recovery from in that case and
additional spares target transactions.
Try to look for repeating sectors before reverting to reading the
JEDEC ID of the flash chip. This way we don't interrupt the flash
execution if a valid program is running, but can detect the flash
size if the flash memory has been erased.
The command can be used either by specifying the length only, or
the start address and the length like so:
monitor erase_sector <length>
monitor erase_sector <start_addr> <length>
If no start address is specified, it will begin erasing from the
start of the flash sector.
There seems to be a bug in the bootrom for the rp2040 which means
that the chip erase command is not accepted. This is because the
CS pin must be released (set high) directly after sending the chip
erase command (0x60 or 0xC7) (see Winbond W25Q128JV datasheet for
details). Instead the bootrom sends the address after the command,
thus the SPI flash silently ignores the command. Instead, we must
erase each 64KB block one at a time, but thankfull the bootrom
handles this correctly for us.
There are some cases when the this old method for finding the flash
size will fail, such as if the flash chip has been erased with 0xFF
bytes (rather than blank 0x00 bytes). As this is unreliable,
setting the wrong flash size could cause problems when trying to
inspect memory regions which appear to be out of range.
lock_flash and lock_bootprot currently support only locking the whole flash and locking the maximal leading flash chunk (32k).
An optional numerical parameter is added. It can be specified in decimal or 0x prefixed hexadecimal.
For samd21 'lock_bootprot 0' locks the first 32k of flash while 'lock_bootprot 6' locks the first 512 bytes. 'lock_bootprot 0' is equivalent to 'unlock_bootprot'.
Similarly, 'lock_flash <number>' locks the flash segments corresponding to zeros in the binary representation of the given number.
'lock_flash 0xffff' is equivalent to 'unlock_flash'.
If the optional parameter is not given both commands work as previously.
The SAMD09 CPU is used in boards such as the Adafruit Seesaw. It has a
smaller amount of memory and flash than other SAMD ports.
This was tested with an Adafruit Seesaw. These boards come with preloaded
firmware. As a test, the firmware was dumped and flash was erased. Then,
flash was verified to be all zeroes. Finally, the firmware was loaded
back in:
(gdb) p/x *(unsigned int *)0@32
$8 = {0x20000f88, 0x1db, 0x1d1, 0x1d9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d9, 0x0, 0x0, 0xf5, 0x1081, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x0, 0x1d9, 0x1d9, 0x25e9, 0x0,
0x0, 0x1d9, 0x1d9, 0x1d9}
(gdb) dump ihex memory flash.ihex 0 8192
(gdb) mon erase_mass
Erase successful!
(gdb) p/x *(unsigned int *)0@32
$9 = {0xffffffff <repeats 32 times>}
(gdb) load flash.ihex
Loading section .sec1, size 0x2000 lma 0x0
Start address 0x00000000, load size 8192
Transfer rate: 5 KB/sec, 910 bytes/write.
(gdb) p/x *(unsigned int *)0@32
$10 = {0x20000f88, 0x1db, 0x1d1, 0x1d9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d9, 0x0, 0x0, 0xf5, 0x1081, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x0, 0x1d9, 0x1d9, 0x25e9, 0x0,
0x0, 0x1d9, 0x1d9, 0x1d9}
(gdb)
Signed-off-by: Sean Cross <sean@xobs.io>
Various SAMD devices have different amounts of memory. Up until now, all
SAMD devices have had the same amount, and therefore this value was
hardcoded to 32k of RAM and 256k of flash.
Add a parameter to the description field and set it to default to the
previous values. Use this description field when adding memories to the
target definition.
Signed-off-by: Sean Cross <sean@xobs.io>
Workaround for CMSIS-DAP/Bulk debugger orbtrace that returns NO_ACK
with high values of TRNCNT. Perhaps only STM32F767 needs write to DHCSR
with high occupancy to catch the device in a moment not sleeping.
Expect signal integrity errors when using jumper cables. Often probes switch
the SWJ GPIO with highest speed, resulting in possible reflections. Additional
ground wires may help. If there is isolation between probe and targets,
additional ground wires are a must or ground shift will wrack the transfer!
Rafael Silva
Jonathan Giles
dragonmux
SId Price
Maciej Musiał
Uwe Bonnes
James Turton
Dag Ågren
Gareth McMullin
Rafael Silva
Michal Moskal
mean
arpadbuermen
Frank Kunz
Sean Cross
Koen De Vleeschauwer
fabalthazar
SG