e1a928beb1
Fixes to compile with gcc11 #925
...
Target code changes are pure for formal correctness and not tested!
2021-10-10 15:59:57 +02:00
b076d5cea1
stm32f1: Check if unlock failed and propagate error.
2021-09-22 21:41:43 +02:00
554e34517e
Better reporting when monitor command fails.
2021-09-22 21:41:43 +02:00
9e98cfa220
adiv5: Remove leftover debug output.
2021-09-22 21:41:43 +02:00
9ebc44bcea
Make more functions static.
2021-09-22 15:16:20 +02:00
9de69bb3ab
Adiv5/Initial halt: More fixes for dd28fa5743. #925
...
Stlink does not like low level access and aborts with STLINK_SWD_DP_ERROR.
Either our implementation still has faults or stlink can not handle
MINDP devices with BMP/Firmware also seemm not to like low level access,
either du to some hidden error in BMP or by design
2021-09-22 15:16:20 +02:00
a9854e9b37
adiv5: Fix the MINDP case introduced with dd28fa5743 #925
2021-09-16 12:39:26 +02:00
f66caa0d29
add some more nxp s32k14x variants
...
the sdid bits correspond to s32k14x as well as s32k11x but i only have
access to the k14x variants so didn't bother w/ the k11x variants.
the memory/flash sizes also can come from the sdid bits, but the
splits still need to come from a lookup.
2021-09-13 23:01:05 +02:00
95288bcf75
fix a size format warning
2021-09-13 23:01:05 +02:00
dd28fa5743
adiv5: Tighten up loop to initial halt cortexm
...
Use TRNCNT when available.
Now the F767 with the NutOS 300 ms sleep example with the one ms tick is
halted even in hosted after few ms.
2021-09-04 21:15:07 +02:00
863a41daac
adiv5_swdp: Initialize initial_dp with the definition
2021-08-15 16:43:29 +02:00
6308506276
jtag: Make jtag_devs argument to jtag_handler.
2021-08-15 16:43:29 +02:00
6dff2a9f31
target: target_error_check now defaults to not indicate error.
...
Remove unneeded nop_function from efm32
2021-08-15 16:43:29 +02:00
3df692ecb2
adiv5_swdp_scan: If SWD scan fails, try a JTAG scan.
2021-08-15 16:43:29 +02:00
2d4a503135
jtag_scan: Rework chain detection
...
Fixme: stlinkv2/hosted probably does only handle STM devices. Check if
jtag_devs.c really needed.
2021-08-15 16:43:29 +02:00
1845d71f00
jtag_scan: Deliver full idcode to the handler.
2021-08-15 16:43:29 +02:00
c7bc4b6a5d
Bug fix in Flash erase function for LPC MCUs.
2021-08-13 16:18:53 +02:00
72bd825a60
Add support for NXP LPC11xx XL series, add 'readuid' command for some MCUs of the LPC11xx series where it was missing; add comments mapping Device IDs to part descriptions.
2021-07-31 16:08:34 +02:00
0c63903071
adiv5: Recover from bad AP access.
...
E.g. AP1 on a STM32WLE5 points to a ROM table, but access to the ROM table
via AP1 hangs forever.
- Substantial reduce timeout when wait for a response. Valid access should
succeed fast.
- Abort AP access to free DP for other accesses
- Don't throw exception, only set dp->fault
- React on higher level
2021-07-15 15:06:54 +02:00
5ea01030e2
Add nRF51 command for (only) erasing the UICR registers
...
Original implementation by: Benjamin Vedder <benjamin@vedder.se>
2021-06-07 13:50:36 +02:00
4b8c4990dc
Fix warning about unused variable in adiv5.c
...
This happens if the platform has debugging support but debugging
is not enabled.
2021-06-03 12:56:41 +02:00
711a87f7ba
Fix some warnings when compiling with -Wshadow
...
There are still a few more places that would need to be corrected
before -Wshadow could be added by default.
2021-06-03 12:55:28 +02:00
891633322a
lpc: Care for protected pages on LPC80x devices.
2021-06-01 16:23:19 +02:00
f7b4697280
lpc11xx/lpc8c04: Do not expose two top system flash sectors.
2021-06-01 16:23:19 +02:00
42ebcac329
efm32_devices: Rearrange struct efm32_device_t to save flash space.
2021-06-01 16:23:19 +02:00
21a702dc1e
lpc: More verbosity and more definitions
2021-06-01 16:23:19 +02:00
87acd99fe4
cortexm: For Cortex-M0+ devices, probe also for lpc11 to detect LPC80 #884
2021-05-18 12:24:00 +02:00
517d5b5b31
rp: Show spinner only when called from monitor command.
2021-05-16 11:26:14 +02:00
0ab10fee0b
rp: Increase timeout for flash_range_program
...
If the RP2040 is using the ring oscilator (ROSC) rather than the crystal
oscilator (XOSC) then flashing program will take much longer. As the XOSC is not
enabled at boot we should not assume it will be enabled before the debugger is
connected (or indeed at all), thus should use the longer timeout during load
commands.
2021-05-16 11:26:14 +02:00
ff30259354
rp: Add more debug logging during flash
2021-05-16 11:26:14 +02:00
e453740aca
rp: Increase spinner timeout to 500ms
...
Increasing spinner timeout to 500 means `tc_printf` is not called during
the `_flash_range_erase`. This is important as `_flash_range_erase` is
used when loading. This fixes the issue:
https://github.com/blacksphere/blackmagic/issues/875
Also adding spinner timeout counter to reduce bus traffic.
2021-05-16 11:26:14 +02:00
67c9003522
rp: Flush cache after erase and write
...
The RP2040 datasheet suggests that _flash_flush_cache and _flash_enter_cmd_xip
should be called after erasing and writing to flash.
2021-05-16 11:26:14 +02:00
f880734050
Fix compiling for native probe
2021-05-16 11:26:14 +02:00
e4421799ba
More header cleanup
2021-05-15 12:54:51 +02:00
f9414d5826
cmsis-dap: Handle ADI DP22 devices on probes not multidrop capable.
2021-04-26 18:18:18 +02:00
1f67bab475
nxpke04: Move unsafe_enables to target bool union.
2021-04-25 16:03:23 +02:00
f87dff8d83
kinetis: Remove static variables, add word union to target_s.
...
Add a word union to target structure to hold a single word variable.
2021-04-25 16:03:23 +02:00
ac7c1057cc
efm32/samd/samx5x: Remove static allocates strings. Allocate in priv_storage.
...
Static allocated variables in the different targets eat up common RAM and
will collide in chains with multiple similar targets.
2021-04-25 16:03:23 +02:00
cddf02f174
samx5: Verbose error reports on protected devices.
2021-04-25 16:03:23 +02:00
8c8aa980cf
adiv5: Detect unprotected SAMD5x only once
2021-04-25 16:02:20 +02:00
1b26ff560d
rp.c: Add reset_usb_boot as monitor command
2021-04-24 14:48:58 +02:00
52bffa70cf
rp: Handle flash.
...
- Beware, after reset, only a valid flash payload get mapped to XIP!
Only 0 is read from flash when flash image is not valid
2021-04-21 21:55:03 +02:00
2b0e255c40
cortexm: timeout and debug for run_stub()
2021-04-21 21:50:38 +02:00
61efe26348
swdp_scan: Break infinite loop after Dormant->SWD transition.
2021-04-21 21:50:38 +02:00
fa5e69e3be
RP 2040: Special handling for rescue DP
...
As the rescue DP provided no AP, trigger the reset with attach().
However attach will indicate failure also reset/halt has succeeded.
2021-04-21 21:50:38 +02:00
ea92c8b8c8
cmsis-dap: Allow to use adiv5_swdp_scan.
2021-04-21 21:50:38 +02:00
23f942ac8c
Raspberry RP2040: Recognize. No flash handling yet.
2021-04-21 21:50:35 +02:00
04d1c9805b
swd: Remove swd_proc and swdptap.h.
2021-04-21 21:50:04 +02:00
b6fbf86743
Extend ADIv5_DP_t for low level routines needed for multi-drop.
...
Will replace swd_proc
2021-04-21 21:50:04 +02:00
5abb288c7a
hosted: Provide the DP functions in swd_proc.
2021-04-21 21:50:04 +02:00
fa561c8d66
adiv5_swdp: Starting point to handle multi-drop
...
- RP2040 show both DPs
- Multidrop test with STM32L552 and STM32H745 allows selection
with "-m 0x4500041" (H7), "-m 1" (L552) or "-m 0x01002927" (RP2040)
2021-04-21 21:50:04 +02:00
be3bfc48a8
cortexm: M33 has up to 8 hardware breakpoints
2021-04-21 21:22:59 +02:00
b1ac4187b9
Fix some formatting strings for 32-bit compile
2021-04-21 21:22:59 +02:00
beaccf2714
target: stm32l4: add support for STM32WLxx
...
This adds support for the STM32WL series in stm32l4.c. These parts have
the same flash registers layout as the L4 series, but a different base.
Since there are already two sets of registers in this target file, this
adds support for register maps that can be customized for each device
ID.
2021-04-20 18:42:36 +02:00
f55ad67b1b
adiv5: catch timeout on adiv5_ap_read_id and abort
...
This adds a TRY_CATCH around the adiv5_ap_read_id() in
adiv5_component_probe() and resets the DP when that happens.
It seems like the STM32WLE5 comes with the AP of the inactive core
enabled in a way that does not make it detectable, and the current code
times out and leaves the whole device hanging.
Catching the timeout and calling adiv5_dp_abort() seems to restore the
device to a useable state.
Tested on Seed LoRa-E5 (STM32E5JC).
2021-04-19 16:57:13 +02:00
d6b24c00c8
Fixed STM32G43x/G44x option bytes support
...
Previously took L4 values so FLASH_SEC1R was not applied
2021-04-17 14:44:30 +02:00
99f9557cc0
Support for STM32G49x/G4Ax (category 4)
2021-04-17 14:44:30 +02:00
c85c946ce3
PRIx32 fix
2021-04-17 14:44:30 +02:00
a6a8606edb
STM32L55: Detect, memory map, read and flash write. Options handling missing.
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Only non-secure states considered!
2021-04-04 17:26:31 +02:00
6d6cfd6c98
Comprehensive STM32G03/4/5/6/7/8/B/C driver
2021-03-29 21:42:40 +02:00
58f153e12b
cortexm: Always halt and release reset before romtable scan
...
Only release from halt once after romtable scan
Should fix #836 .
2021-03-26 17:43:11 +01:00
a025c9a7bd
Revert "stm32f1: On ST parts there is no need to read IDCODE again."
...
Romtable partno is not unique for devices, e.g. in STM32F0
This reverts commit f89b07d892
2021-03-26 17:35:00 +01:00
f89b07d892
stm32f1: On ST parts there is no need to read IDCODE again.
...
IDCODE is already known from the Romtable
Probably this has the same effect as #836
2021-03-12 20:45:34 +01:00
7859a2aabd
adiv5_swd: Factor out creation of packet request.
2021-03-06 13:30:09 +01:00
cfb784d428
adiv5: Fix comments and debug output
2021-03-05 16:49:19 +01:00
560a046a22
Add support for NXP LPC802, LPC804, LPC832 and LPC834
2021-02-22 19:37:46 +01:00
0df44e205b
ADIv5: Abort Romtable scan also if CIDR0 is invalid after halting #832
...
STM32WLE5 has the same dual core chip as STM32WL5. For the second
core, the additional AP can be see, but access to e.g. CIDR0 for that
Romtable fails.
Aborting the scan too if again the second read of CIDR0 fails makes
sense anyways!
2021-02-19 18:48:02 +01:00
c776e7a9a6
swd_scan: Add '-m' as targetid argument to swd_scan to prepare multi-drop.
...
In a real multi-drop setup, the device to use must be specified.
2021-02-15 17:47:29 +01:00
8e2f6937d5
hosted: Run target specific monitor commands with -M "command" .
...
Lists available commands: "blackmagic -M help"
Quote multi argument monitor commands, e.g. STM32F1: blackmagic -M "option help"
2021-02-15 17:47:29 +01:00
165560edd8
cl_utils: target selection '-n' argument needs optarg.
...
foreach now returns the number of targets.
2021-02-15 17:47:29 +01:00
42f590ce0b
fixing some memory map errors for stm32h7, PR #821
2020-12-23 20:10:39 +01:00
2b06f045c4
target: kinetis: add S32K148
...
This adds support for the NXP S32K148. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-12-16 12:49:23 +01:00
020600aa56
target/lpc546xx: fix lpc546xx flash support ( #801 )
...
**Summary**
Modifications to fix flash support on the lpc546xx:
- fix IAP entrypoint to be `0x03000204`, not the value at that address
- add a reset and attach sequence before erasing flash sectors. there's
little documentation around this, but experimentally, erasing sector 0
fails when the ROM bootloader is mapped to it (on reset). stepping the
chip once and attaching is enough to snap the chip out of it, permitting
flash erase on sector 0.
- add a few test commands to the lpc546xx table (read_uid, erase/write
sector, etc).
- write the magic CRC value when writing to sector 0
(`lpc_flash_write_magic_vect`).
- move the lpc546xx probe to before the lpc43xx probe, to prevent
getting the lpc546xx into Lockup when reading an illegal memory location
during lpc43xx probing
Fixes #786 .
I don't 100% understand the reset/load sequence of this part, but these
changes are sufficient to program and debug the part now.
I didn't do a detailed analysis of what pyocd (via st-link hardware
adapter) and segger jlink do to handle the same, but both of those
worked without modification, so there's some difference in the
sequence they're using.
**Testing**
Verified I can now successfully erase and write an executable in sector
0 (and other sectors).
Verified the new commands work correctly.
2020-12-12 19:48:05 +01:00
518529a772
Support GD32E23x
2020-12-12 18:29:30 +01:00
dd6aadc54d
jtag: Add verbosity about devices found.
2020-12-06 15:18:08 +01:00
e318f884bf
Change the type of 'cortexm_wait_timeout' to unsigned.
...
It makes sense that the timeout value is unsigned, it also
resolves build errors on some platforms.
2020-12-04 11:44:50 +01:00
e3fd12ebc6
gd32f1/f3 detection and ram/flash autoset
2020-12-03 11:16:47 +01:00
575c25e570
Add support for STM32F1 clone with new AP_DESIGNER id
2020-12-01 10:23:16 +01:00
48a79ff9da
adiv5: More checks for a sensible DPIDR.
2020-11-29 21:11:11 +01:00
752bc26536
adiv5: Fix memleak with duplicated base.
2020-11-29 21:11:11 +01:00
acec489647
adiv5_jtagdp: Always set idcode.
2020-11-29 21:11:11 +01:00
f45c56af83
adiv5/swdp: Check early for valid DP idcode.
2020-11-29 15:48:50 +01:00
7df314e265
Firmware/Jlink: Fix double free when debug power-up fails ( #780 )
2020-11-29 15:48:50 +01:00
bf548e92c0
swd: After write low_access, always append 8 clk to move data through SW-DP.
...
Especially needed when leaving the debugger or during debug unit power-up.
ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
tells to clock the data through SW-DP to either :
- immediate start a new transaction
- continue to drive idle cycles
- or clock at least 8 idle cycles
Implement last option to favour correctness over slight speed decrease
Implement only for adapters where we assemble the seq_out_parity in our code,
as on firmware, ftdi and jlink. Hopefully the high level adapters do it right.
Reverts 2c33cde63fcde7726b87
2020-11-27 22:26:48 +01:00
3ee31473c6
cortexm.c: LPC15xx has designer 43b and Partno 4c3
...
Thanks to JojoS!
2020-11-27 22:26:48 +01:00
19e1fddba2
adiv5: Remove unnescessary read.
2020-11-27 22:26:48 +01:00
cda83d3084
Fix memleaks.
...
Happened e.g. when Stlink could not enter debug or when cortexm_prepare timed out.
2020-11-27 22:26:48 +01:00
9ac5adfcef
adiv5: Additional decoding.
2020-11-27 22:26:48 +01:00
d78d7838d3
stm32f1: Always read DBGMCU_IDCODE for t->idcode ( #770 )
...
At least STM32F042 has 0x440 as romtable partno vs 0x445 as DBGMCU_IDCODE.
Thanks to Andrey Melnikov(aam335) for pointing out!
2020-11-27 22:26:48 +01:00
653d486ee2
cortexm: Store CPUID in target structure.
2020-11-27 22:26:48 +01:00
80154c5c7a
adiv5_swdp: Fix more memory leak.
2020-11-27 22:26:48 +01:00
35bcb4f7c6
Switch on the lpc546xx target
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Enable the lpc546xx target. Tested on the LPCXpresso54628 dev board,
able to flash and debug.
2020-11-24 21:32:39 +01:00
e9c02296f2
target: kinetis: add S32K118
...
This adds support for the NXP S32K118. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-11-14 13:06:23 +01:00
f18be6ef7a
Add support for Kinetis K12 and placeholders for other K-series MCUs
2020-11-07 12:44:05 +01:00
2c33cde63f
cortexm.c/cortexm_halt_resume: Add some clock cycles to always get CPU going ( #768 )
2020-11-01 21:53:23 +01:00
1f7a716710
adiv5.c: Run cortexm_prepare on all suspected CortexM instances.
...
Gets all debug units of the second CPU of a STM32H745 visible.
2020-10-23 09:40:15 +02:00
18673d9a56
adiv5: Rework DP/AP refcounting.
...
ASAN non longer reports leaks with the STM32H745.
2020-10-23 09:40:15 +02:00
f76a7c4e92
adiv5: Release devices after scan.
...
Before, scanning only kept device stopped until POR or attach/detach cycle.
2020-10-23 09:40:15 +02:00
59dc1b7eb4
cortex-m7: Give hint about buggy core revision.
2020-10-23 09:40:15 +02:00
976c763747
jtag remote: Start fixing handling M0 (second jtag) for LPC4322 in high-level
...
- LPC11: Only print none-null unknown idcodes.
2020-10-23 09:40:15 +02:00
c161521c26
cortexm: Designer ARM must be in the default path when probing.
2020-10-23 09:40:15 +02:00
cdd07544d5
Cortexm: Allow pure debug on devices not yet handled for flashing
...
- Recognize STM32L552 and MIMXRT10XX
- Fix another PIDR
- Fix bad debug print string.
2020-10-23 09:40:15 +02:00
0ffb4f7b18
cortexm: Fix protected SAM detection
...
- Only run cortex_prepare() if reading cidr fails
- With Atmel DSU detected, run cortexm_probe()
2020-10-17 12:49:37 +02:00
5bc743d221
samd: Propagate security after setting security by chip reset.
2020-10-17 12:49:37 +02:00
8b929c12c9
hosted/jtag: Transfer jtag_devs to firmware.
2020-10-16 20:03:03 +02:00
3d92b82678
jtag: Use index and not device structure for jtag_dev_write_ir and jtag_dev_shift_dr
2020-10-16 20:03:03 +02:00
7ccf0d3e03
jtag_dev_t: Make dev, idcode and desc less generic.
...
No codechange intended.
2020-10-16 20:03:03 +02:00
87b546777a
nrf51: Be more verbose about the protection status.
2020-10-16 12:16:33 +02:00
4108b649c2
stm32h7: Add support for new product lines
...
Add support for:
* STM32H7B3/B0/A3 (RM0455)
* STM32H723/33/25/35/30 (RM0468)
Successfully tested with:
* STM32H7A3ZIT (RM0455)
* STM32H747XIH (check for regressions)
2020-10-10 22:09:34 +02:00
877b4be8ee
cortexm: Restrict probing by using the ap_designer.
...
More designers need to be observed and reported by users and added.
Request users to send needed data.
2020-10-07 20:12:35 +02:00
91d1ef8bf6
target/stm32: Use t->idcode with probe.
2020-10-07 20:12:35 +02:00
44bfb62715
Adiv5: Print Designer/Partno when device is not recognized
...
t->idcode is now 16 bit.
2020-10-07 20:12:35 +02:00
c456fc7f61
adiv5: Store AP designer and partno in the AP structure.
2020-10-07 20:12:32 +02:00
159196c2ad
Cortexm: Remove forced_halt.
2020-10-07 20:11:33 +02:00
9bb2807706
adiv5/romtable: Prepare CortexM devices to read the ROMTABLE
...
It seems, writing to DHCSR fails silent when the device is sleeping.
Reading DHCS during sleep may return nonsense.
Repeated write may at some point catch the device running and succeed.
With devices sleeping for long time and running on faster clock the
chance for a successful hotplug gets smaller.
- Try hard to halt a sleeping device
- Prepare vector catch and enable all debug units by TRACENA
- Release reset
- Apply device specific fixes
-- STM32F7: Store old value of DBGMCU_CR, enable debug in sleep in
DBGMCU before reading PIDR and restore DBGMCU on detach.
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
2020-10-07 20:11:17 +02:00
dc8924a2bc
stm32h7: Don't tc_printf from flash functions ( #747 )
...
* stm32h7: Don't tc_printf from flash functions
Receving an 'O' packet while flashing confuses GDB and then
weird stuff happens.
* Replace tc_printf with DEBUG_WARN
2020-10-05 10:45:18 +02:00
014abf6cc9
adiv5.c: Reduce number of errors if reading cidr fails.
2020-10-01 15:33:28 +02:00
be40d2b851
adiv5: Check Debug Base Address early
...
Reduces printout when scanning the romtable
2020-10-01 15:22:17 +02:00
38bc5bbf82
Add LPC546xx support #741 #553
2020-09-30 12:56:53 +02:00
2fdd94adeb
STM32F7: Add another missing Arch ID.
2020-09-24 16:20:34 +02:00
bdb351a6ea
adiv5_swdp: On ACK_FAULT, error() and try again once #731
...
when writing CSW.
2020-09-18 20:07:32 +02:00
120b3134bb
Add SAM4SD32C/B support.
2020-09-07 17:36:15 +02:00
8a2bce26f2
Hosted: Fix memory leak when platform_swdptap_init fails.
2020-09-04 11:49:13 +02:00
f65afb1588
Use correct IAP entry address for LPC84x
2020-08-14 20:00:18 +02:00
71e9d78210
adiv5.c: Add another ARCH_ID found STM32F205.
2020-08-01 14:00:17 +02:00
1b12e407fd
adiv5: Add missing arch identifiers for Cortex-M7 ETM.
2020-07-31 11:53:15 +02:00
696daa8352
adiv5: fix debug print of dev_type
...
Since dev_type is an 8 bit unsigned integer, use the PRIx8 macro instead
of PRIx32.
2020-07-29 11:32:24 +02:00
726d4b4496
adiv5.c: Add missing DEVTYPE and ARCHID to some existing PIDRs(#698,#699)
...
Probably more additions are needed.
2020-07-14 16:26:32 +02:00
09ceaea70f
adiv5_swdp: Fix another memory leak.
2020-07-14 15:02:13 +02:00
7ebb94d134
cortexm: Add comment on CPUID register
2020-07-12 22:54:39 +02:00
4391851f4d
adiv5: Change component descriptions from MTB to Micro Trace Buffer for consistency
2020-07-12 22:29:04 +02:00
0aadd0abce
Adiv6: Add comment on DEVTYPE and ARCHID fields with references
2020-07-12 22:27:46 +02:00
fcd945a529
cortexm: Read CPUID to identify core version
2020-07-12 12:08:22 +02:00
39a20d78ff
v8m: only check relevant bits in DHCSR when polling in cortexm_forced_halt
2020-07-12 12:07:12 +02:00
a35e9c8e5c
Adiv6: Read DEVTYPE and ARCHID to identify Cortex-M23 and Cortex-M33 debug components
2020-07-12 12:00:31 +02:00
661f78033a
stm32f1: Add F1 XL with dual bank handling,
2020-07-08 14:31:58 +02:00
eabd69dcdb
Adiv5: Protect DBG/SYSTEM Power-Up request with timeout too.
...
CMSIS-DAP without connected target looped infinite in that situation.
2020-06-07 13:14:32 +02:00
dc3fd2eb06
Classify debug messages
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Firmware BMP with ENABLE_DEBUG=1 will print WARN and INFO as before.
PC-Hosted BMPwill alway print to stderr. Warn is printed unconditional,
INFO, GDB, TARGET, DONGLE and WIRE will print if their appropriate bit in
cl_debuglevel is set via the -v verbose command line argument.
INFO will go to stdout with -t or -l.
2020-06-05 14:59:30 +02:00
64f3dff8a8
PC-Hosted: Better debug output.
2020-06-05 14:59:30 +02:00
b06c0ba8d5
bmp_remote: Use high level functions.
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Based on #570 (OpenOCD HLA interface driver for Blackmagic), but now
usefull for bmp-remote.
2020-06-05 14:59:30 +02:00
c3d509e6c0
Clean up PLATFORM_HAS_DEBUG
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Use only for firmware platforms.
2020-06-05 14:59:30 +02:00
563df2d354
Detour ADIv5 high-level functions.
2020-06-05 14:59:30 +02:00
9969c984f3
detour jtag primitives.
2020-06-05 14:59:30 +02:00
e34a27f72c
Detour swd primitives.
2020-06-05 14:59:30 +02:00
b0cf7d24bd
adiv5.c: Fix another leak.
2020-06-05 14:59:30 +02:00
783ec377d9
adiv5: Export extract.
2020-06-05 14:59:30 +02:00
966ac4036d
target.c: Check for valid flash structure.
2020-06-05 14:59:30 +02:00
60f39f55b4
MSP432: Warn when hardware version not supported.
2020-06-05 14:59:30 +02:00
05adcd9bf5
remote.c: Compile only relevant functions.
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Do no compile firmware functions when compiling pc-hosted.
2020-06-05 14:59:30 +02:00
16967b4328
adiv5: Remove only local dp_idcode used from ADIv5_DP_t struct.
2020-06-05 14:59:30 +02:00
b8b34e7b1d
adiv5: remove cfg for AP structure, cfg is only used local.
2020-06-05 14:59:30 +02:00
69e330849d
fix flash map for STM32G431, as it is a special case different from the STM32G47x and STM32G48x chips
2020-06-05 13:41:18 +02:00
f9f928e9d6
Add support for LPC8N04
2020-06-05 12:33:51 +02:00
6eb1b09c1c
pc-hosted semihosting
2020-05-27 12:51:29 +02:00
54ee00b0f6
set semihosting sys_clock time origin
2020-05-13 17:50:39 +02:00
499309f648
stm32f1: Tell user about STM32F10(3) clone.
2020-05-13 13:07:55 +02:00
1a83bc6892
Rename variant_string in efm32 samd samx5x ( #659 )
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* Rename variant_string
Files efm32 samd samx5x uses same function name that collides during
linking (checked with gcc10)
Signed-off-by: Alexey 'Alexxy' Shvetsov <alexxyum@gmail.com>
* Also make xxx_variant_string static
Signed-off-by: Alexey 'Alexxy' Shvetsov <alexxyum@gmail.com>
2020-05-12 17:47:04 +02:00
9b939f4a3a
stm32f4: Fix option byte handling ( #654 )
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Option bytes are not accessible with level 1 protection, so
Use FLASH_OPTCR(x)
Fix crash with "mon opt write xxxx"
Handle option manipulation better when HW Watchdog fuse is set
Allow abbreviated "mon option x<yyy>" commands
2020-05-05 12:52:32 +02:00
923949d5dd
Fixed variable/function name clash building on Windows
2020-05-03 15:45:31 +02:00
9f8c7be360
semihosting
2020-05-02 12:55:29 +02:00
8851504a41
new semihosting commands
2020-04-23 09:43:46 +02:00
ada17ada23
stm32f4/7: Always use largest flashsize for device family ( #633 , #635 , #644 )
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Do not care for the FLASHSIZE register. Leave it up to the user to abuse
flash area the ST did not announce.
2020-04-21 17:04:07 +02:00
164eb43f00
NRF5: Do not reset target options.
2020-04-14 19:01:43 +02:00
bea8436561
NRF5: Always set CORTEXM_TOPT_INHIBIT_SRST( #230 )
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The problem also happens with NRF52840. Set CORTEXM_TOPT_INHIBIT_SRST
for all NRF5 device.
People should be more persistent!
2020-04-14 18:11:23 +02:00
d1468530bd
add basic support for LPC11U68 (and maybe LPC11U68)
2020-04-06 23:36:49 +02:00
846dadcc39
lmi: add support for TM4C1294NCPDT
2020-04-03 19:42:24 +02:00
c4d7232223
Export function to read out PIDR and use for samd and samx5x.
2020-03-26 19:05:57 +01:00
a0e42e229b
Make more things static.
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No functional change intendend.
2020-03-26 18:44:19 +01:00
effd43ce38
Harden cortexm_reset() and remove double reset( #601 )
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Thanks to Dave Marples <dave@marples.net> for input.
- Issue only one reset. Start with SRST. Only if not seen, use SYSRESETREQ
- Wait for release of DHCSR_S_RESET_ST before issuing more commands
- Add timeout to catch reset line stuck low
- Remove AP errors
2020-03-25 11:22:14 +01:00
2e185ba578
BMP/PC: Allow to compile with mingw64 ( #615 )
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__USE_MINGW_ANSI_STDIO 1 must be set befor any windows specific included.
2020-03-24 17:59:13 +01:00
a7efe7cc14
cl-utils: Display targets found.
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+ other small changes in DEBUG output.
2020-03-10 17:34:30 +01:00
2065c70888
adiv5: Split PRIx64 into two PRIx32 as nanolib does not support PRIx64.
2020-03-10 10:56:42 +01:00
75186f7d50
ADIv5: More CoreSight device decoding:
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- MTB-M0+ (Simple Execution Trace)
- M33: Devices need finer decoding (DEVTYPE at offset 0xfcc)
2020-03-08 22:37:59 +01:00
919d9320fd
Remove unrelated files.
2020-03-06 19:33:20 +01:00
288620551f
adiv5: Print out SYSROM PIDR.
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We need to know more about what devices indicate proper PIDR and what
devices fail to do so.
2020-03-04 19:02:07 +01:00
8c959defca
efm32: Make local functions static.
2020-03-04 18:44:40 +01:00
470c8e8cf1
target_flash_erase: Do not crash when requesting erase of unavailable flash.
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Allow to erase from command line.
2019-12-13 14:59:42 +01:00
ab396f9745
Allow %z specifier in windows builds. Supercedes #562 .
2019-12-08 16:43:19 +01:00
1bef51e145
adiv5: Abort scanning APs after 8 void APs.
2019-12-08 16:43:19 +01:00
bdd76de517
Erase: Fix endless erase when erase-area did not end on (page|block) boarder.
2019-12-08 16:43:19 +01:00
25d24e5c34
efm32: Allow to compile with -Og.
2019-12-08 16:43:19 +01:00
5943552a6b
[efm32] Probe for the EFM32 Authentication Access Port (AAP)
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Supported functionality through this AP:
* Issuing a DEVICEERASE command
2019-12-08 16:21:02 +01:00
260fc88d8f
[efm32] Add command to set and print bootloader enable status
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This is a bit in the Lock Bit (LB) flash page, so it can only be
cleared by this routine
2019-12-08 16:17:02 +01:00
7f0d5febc3
[efm32] Print MSC Interrupt Flags to DEBUG after each flash write
2019-12-08 16:16:55 +01:00
e85df763b7
[efm32] add new devices PG12B, JG12B, GG11B, TG11B, GG12B
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Rework MSC layout check
2019-12-08 15:55:12 +01:00
f89542c79f
Merge pull request #203 from dlaw/master
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Add LPC11xx command to read out unique ID from target. Restore Ram and registers after call.
2019-12-08 15:45:49 +01:00
8a07f44435
Add support for the kinetis KL16Zxx devices. Tested on KL16Z128VFM4 custom hardware
2019-11-21 20:37:13 +01:00
e7e34600a4
lpc11: Only print Idcode if not zero and not yet handled.
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Otherwise for all Cortex-M not yet handled this LPC messages appears.
2019-11-17 13:24:39 +01:00
9198c951bb
Reduce flash space required for SAM D51/E5x driver
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* Reuse functions that are common with the SAM D1x/D2x driver
* Only include the mbist and write8/16/32 user commands if
SAMX5X_EXTRA_CMDS is defined
2019-11-17 12:45:49 +01:00
d3c330ea1a
Fix issues with Travis CI build
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It appears the Travis version of gcc-arm-none-eabi doesn't allow the %x
printf format specifier for size_t arguments, in contrast with the
version I'm running on Ubuntu 18.04 (15:6.3.1+svn253039-1build1).
2019-11-17 12:45:49 +01:00
26216beaab
Microchip SAM D51 / E5x support
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Adds a target driver for Microchip SAM D51 / E5x family.
Tested on SAMD51G19A and SAMD51J19A. According to the datasheet, the
D51 / E5x family share the same core feature set, differing only in the
addition of CAN (E51) or ethernet controllers (E53/54). All members of
the family should be equivalent from a debug and programming perspective.
2019-11-17 12:45:49 +01:00
28f0ced97e
Support NXP LPC1343
2019-11-09 18:47:07 +01:00
67f9d26644
samd: Add support for L21 & L22 (PR #345 )
2019-11-09 13:59:37 +01:00
b9249fe104
adiv5: Activate DP reset sequence, guarded with timeouts.
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While not working on most STM32, it succeeds on STM32G474.
Thanks to Dave Marples <dave@marples.net>
2019-10-20 22:15:28 +02:00
4a8cba0e9c
Add support for LPC1114/333 (LPC1100XL series)
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This is not given in the user manual but the register immediately
following DEVICE_ID does apparently contain the correct part ID.
2019-10-13 13:01:19 +02:00
5c805c7d35
Fix buffer overflow in adiv5_component_probe()
2019-10-12 11:44:08 +02:00
0ae7cea1ae
Add LPC84 from UM11029, Rev. 1.4, tested on LPC845 Breakout board.
2019-10-08 18:17:43 +02:00
1cf0b8ac13
Make all arguments for all commands (struct *t, int argc, const char **argv).
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-Wall on gcc8 otherwise warns without -Wno-cast-function-type but older
GCCs/CLang choke on that argument:
error: unknown warning option '-Wno-cast-function-type'; did you mean
'-Wno-bad-function-cast'? [-Werror,-Wunknown-warning-option]
This adds 24 byte to the binary, as some functions are now called with
additional dummy arguments:
"Pushing and popping garbage to keep the system happy"
2019-09-29 12:44:55 +02:00
f010a567bd
adiv5: Reject APs duplicating last AP.
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Seen with TM4C129 on black MSP432R401 Launchpad. Scanning of APs is aborted,
so valid APs after duplicated APs are ignored.
2019-09-29 12:44:37 +02:00
fae2966b72
Target: Default to nop-function() for all exported target functions.
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Fixes #522 .
2019-09-23 17:42:29 +02:00
Uwe Bonnes
dpc
Thiadmer Riemersma
Björn Mellström
James Turton
Fabio Baltieri
fabalthazar
Alex Norman
Sean Cross
Noah Pendleton
Aaron Lindsay
Stoyan Shopov
mean
Jonathan Giles
Noah Pendleton
jbuonagurio
Richard Meadows
Gareth McMullin
Eivind Alexander Bergem
Damien Merenne
David Lawrence
Francesco Valla
Fredrik Ahlberg
Valmantas Paliksa
Dömötör Gulyás
Thomas Bénéteau
Koen De Vleeschauwer
Alexey Shvetsov
Sid Price
Artur Maciuszonek
Ken Healy
Kirill Zhumarin
dpslwk