This commit removes the previous tdesc_cortex_a, tdesc_cortex_m, and
tdesc_cortex_mf XML string literals used for target description to GDB,
now instead programmatically generating them at runtime to significantly
deduplicate the characters that get embedded into the binary.
Output of ld's --print-memory-usage during final link before:
Memory region Used Size Region Size %age Used
rom: 116388 B 128 KB 88.80%
ram: 3348 B 20 KB 16.35%
Output of ld's --print-memory-usage during final link now:
Memory region Used Size Region Size %age Used
rom: 113032 B 128 KB 86.24%
ram: 3376 B 20 KB 16.48%
So all in all this saves 3356 bytes of flash.
Note: the exact size saved when compiled on your machine may differ, as
the size of the build seems at least partially non-deterministic.
We've gotten slightly different sizes (within 15 bytes of each other)
at different times, with the only differences being things like which
files were rebuilt in an incremental rebuild, or the order object files
were given to the linker command line. The numbers given above were the
numbers we got when testing the final builds from scratch, but all the
sizes we got were extremely similar to the sizes listed above.
this makes the assumption that DPs will be v1 or higher, for SWD-DP scans this is
guaranteed, but on JTAG-SCANS it may not be true, DPv0 does not have DPIDR
implemented and reads are UNPREDICTABLE
Signed-off-by: Rafael Silva <perigoso@riseup.net>
add missing fetching of targetid in jlink probes
clarify how targetid is being read
handle idcode as debug_port_id
use targetid when available to identify device in probe routine
"Single" core STM32WLE still sees AP1 but on first scan aborts gracefully
after some errors and on later runs sees AP1 as unusable. Fixes#832.
Decode the Cross trigger interface found on CPU2 on STM32WBxx.
**Summary**
Modifications to fix flash support on the lpc546xx:
- fix IAP entrypoint to be `0x03000204`, not the value at that address
- add a reset and attach sequence before erasing flash sectors. there's
little documentation around this, but experimentally, erasing sector 0
fails when the ROM bootloader is mapped to it (on reset). stepping the
chip once and attaching is enough to snap the chip out of it, permitting
flash erase on sector 0.
- add a few test commands to the lpc546xx table (read_uid, erase/write
sector, etc).
- write the magic CRC value when writing to sector 0
(`lpc_flash_write_magic_vect`).
- move the lpc546xx probe to before the lpc43xx probe, to prevent
getting the lpc546xx into Lockup when reading an illegal memory location
during lpc43xx probing
Fixes#786.
I don't 100% understand the reset/load sequence of this part, but these
changes are sufficient to program and debug the part now.
I didn't do a detailed analysis of what pyocd (via st-link hardware
adapter) and segger jlink do to handle the same, but both of those
worked without modification, so there's some difference in the
sequence they're using.
**Testing**
Verified I can now successfully erase and write an executable in sector
0 (and other sectors).
Verified the new commands work correctly.
Mikaela Szekely
Rafael Silva
grumat
dragonmux
Anti Sullin
Maciej Musiał
Uwe Bonnes
mean
Koen De Vleeschauwer
Björn Mellström
James Turton
fabalthazar
Thiadmer Riemersma
Noah Pendleton
Aaron Lindsay
Jonathan Giles