af86d50bc2
lpc11xx: Moved the readuid command to where it makes more sense
2022-07-30 16:59:38 -07:00
3d1933a5a0
lpc11xx: Run clang-format across the code
2022-07-30 16:59:38 -07:00
a9fff1e8a6
adiv5: Tidied up in adiv5_component_probe()
2022-07-30 16:43:43 -07:00
ce37d4e833
adiv5: Fix some nomenclature in adiv5_dp_init()
2022-07-30 16:43:43 -07:00
733d8ddc19
adiv5: Fix the invalid AP handling loop so that we don't stop early and bail out before time.
...
This improves target detection reliability.
2022-07-30 16:43:43 -07:00
02b979d382
jtagtap: Added support for configurable TAP idle cycles ready for RISC-V support
2022-07-30 16:26:04 -07:00
5e9a974c42
Fixed compatibility issues with CH32F1 target driver and other STM32F103 clones.
2022-07-30 09:57:28 +01:00
4d64edad7a
fix: Use standard macros for debug message formating
2022-07-29 21:22:17 +01:00
57fec4d0b6
adiv5: Cleaned up a couple of the debug prints
2022-07-29 21:22:17 +01:00
7c14b62419
target: fix probing for lpc1343
2022-07-26 05:14:30 +01:00
bf30580330
target/adiv5: add missing include in hosted build
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-26 05:08:10 +01:00
8b5206fb8d
target: add weak aliasing to allow disabling targets
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-26 05:08:10 +01:00
6f81cb6a68
adiv5: Removed an extraneous pair of perens as they suppress desirable warnings
2022-07-25 18:28:57 +01:00
3592658a26
adiv5: Cleaned up the loop in adiv5_ap_read_id
2022-07-25 18:28:57 +01:00
bb3e74062e
adiv5: Fixed the naming of a timeout in cortexm_prepare
2022-07-25 18:28:57 +01:00
013b2dee60
target/adiv5: further cleanup
2022-07-25 18:28:57 +01:00
0942d7047a
target/adiv5: saner designer code handling and cleanup
...
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
2022-07-25 18:28:57 +01:00
d1fa50336e
target/adiv5: clang format/tidy
2022-07-25 18:28:57 +01:00
c530bd077b
misc: Switched to using C11
2022-07-18 20:59:15 -07:00
10d30821e5
swdptap: Cleaned up the naming and and signatures of the SWDP implementation functions
2022-07-18 18:57:10 -07:00
85d24e8289
target: Implemented a command to allow erasing Flash ranges on any target
2022-07-18 17:12:13 -07:00
1b8e522e87
nrf51: Add command to enable flash protection
...
Add braces for the while loop
2022-07-15 16:57:52 +01:00
6ae846ae24
target/nrf51: Add command to enable flash protection
...
Add command `mon protect_flash` to enable flash read/write protection
2022-07-15 16:57:52 +01:00
94b62ff924
target: Fixed several clang-tidy warnings which improve readability of the code
2022-07-14 16:19:43 -07:00
bdf4dc8731
nrf51: Fixed mass erase after run then user interrupt (Ctrl + C) not working
2022-07-14 14:19:14 -07:00
5607eac812
cortexm: Cleaned up formatting, types and const-correctness in cortexm_attach
2022-07-14 14:19:14 -07:00
069f05ea4b
target/efm32: stop hiding data in driver string
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-14 13:11:19 +01:00
096927b0b8
target/efm32: bootloader lock word handling fix
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-14 13:11:19 +01:00
c2589bc39f
target/efm32: mass erase correctness
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-14 13:11:19 +01:00
00dd7f145f
target/efm32: code cleanup
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-14 13:11:19 +01:00
42d36d9d10
target/efm32: general formatting/style cleanup
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-14 13:11:19 +01:00
018fc517a1
stm32f4: Fixes erase_mass command return error.
...
The final erase_mass command check is looking for the EOP (End of
OPeration) bit to be set. This bit is only set when the EOP interrupts
(EOPIE = 1) are enabled. We are not enabling those on the target so this
bit will never get set. As we are monitoring the BSY flag to make sure
the erase_mass operation is still ongoing and finished it is enough if
we just check the error flags.
2022-07-13 20:57:09 -07:00
6d7c6c5daf
lmi: Added progress dots for mass erase to stop GDB timing out
2022-07-13 19:34:57 -07:00
d64992ade8
rp: Cleanup in how we define some of the Flash constants
2022-07-13 19:34:57 -07:00
ce94169099
stm32l0: Added some links to the reference manuals
2022-07-13 19:34:57 -07:00
a22d6e5056
stm32l0: Run clang-format across the code
2022-07-13 19:34:57 -07:00
b84f883aeb
lmi: Implemented mass erase
2022-07-13 19:34:57 -07:00
90b7362162
stm32l4: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
787d66fe95
stm32h7: Switched to the unified mass erase command, breaking up the implementation cleanly and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
980a1f140c
stm32g0: Switched to the unified mass erase command, breaking out the bank erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
d82ad89715
stm32f4: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
2f0d35de19
samx5x: Bracket and GDB message cleanup
2022-07-13 19:34:57 -07:00
591f05d7e5
samd: Cleanup and fixed a notification TODO
2022-07-13 19:34:57 -07:00
94d5c0576b
samd/samx5x: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
e9b75ba4bc
rp: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
ffd358824f
nrf51: Switched to the unified mass erase command for the recovery target and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
57d8e8f5d9
nrf51: braces cleanup in nrf51_flash_erase
2022-07-13 19:34:57 -07:00
ee694fcb75
nrf51: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
8130b62bcf
lpc546xx: Switched to the unified mass erase command for the recovery target and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
9af2d2a413
lpc: Clean up part of the lpc_iap_call command wait loop
2022-07-13 19:34:57 -07:00
56ecbb3b89
lpc43xx: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
6f57cdf6ba
lpc17xx: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
ae1cb56ce0
kinetis: Switched to the unified mass erase command for the recovery target and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
9d46d0c5c6
target: Refactored out the progress printer to reduce Flash usage
2022-07-13 19:34:57 -07:00
b8ca831cfb
efm32: Switched to the unified mass erase command for the recovery target and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
c1758088cd
efm32: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
17c04d585e
stm32f1: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
c2d72b4825
kinetis: Switched to the unified mass erase command and added progress dots to stop GDB timing out
2022-07-13 19:34:57 -07:00
c35f65c6c0
target: Implemented a global target mass erase command
2022-07-13 19:34:57 -07:00
30e2106e40
target: Make the buffers used to program a target's Flash better bounded in lifetime and memory usage
2022-07-13 19:08:31 -07:00
3e9913e88b
Implement semihosting debug output redirection to usb-uart port.
2022-07-13 18:49:20 -07:00
4bc68409f8
kinetis: Clean up how kl_gen_flash_done builds the command buffers to send to ensure the security byte is OK
2022-07-11 17:12:23 -07:00
f0566979b0
kinetis: Fixed the flash write command generation for K64 devices
2022-07-11 17:12:23 -07:00
6f273cadd8
kinetis: Try to be safer about our FCCOB writes so the Flash controller's less likely to get mad
2022-07-11 17:12:23 -07:00
0c18fcefe3
kinetis: macro organization and clearer function naming
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-09 15:55:37 -07:00
18a49ac853
kinetis: Run clang-format on the code
2022-07-09 15:45:06 -07:00
72e4f4d2b2
kinetis: Refactored out some common code from kinetis_probe for the S32K14 lineup
2022-07-09 15:45:06 -07:00
fee6f28915
kinetis: General formatting and readability cleanup
2022-07-09 15:45:06 -07:00
780ee7a2a8
Fix build error and logic ...
2022-06-28 06:31:16 -04:00
1a963b81f6
target/stm32f1: GD32E230 option write special case handling
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-06-27 18:13:52 -04:00
e7a7d82b33
target/stm32f1: remove unused code snippet and superfluous preprocessor check, less pedantic wording on warning
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-06-27 18:13:52 -04:00
a5ebff14bb
target/stm32f1: remove redundant grouping ad for loop cleanup
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-06-27 18:13:52 -04:00
90ed4fe31a
target/stm32f1: clang-format and code styling for better readability
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-06-27 18:13:52 -04:00
5666fa2a2f
target/sam3x: add aditional check for valid EEFC addr
...
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
2022-06-27 07:48:54 -04:00
1bca0323d9
target/sam3x: saner uninitialized variable prevention
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-06-27 07:48:54 -04:00
730a795f09
Add idcode for GD32F303CG detection
2022-06-26 21:00:26 -04:00
09f64b0627
misc: Added a HACKING.md to provide an explanation of nomenclature and how we handle reset terminology
2022-06-26 16:51:58 -07:00
aa9c80b37d
misc: Formatting consistency
2022-06-26 16:51:58 -07:00
0dae6a4019
misc: Renamed connect_assert_nrst to clarify usage and align naming
2022-06-26 16:51:58 -07:00
b226c53d13
misc: Renamed CORTEXM_TOPT_INHIBIT_NRST to clarify usage and align naming
2022-06-26 16:51:58 -07:00
5edf549b48
misc: Updated comments and READMEs to properly reflect pinouts and function
2022-06-26 16:51:58 -07:00
a8e12d716d
misc: Renamed platform_nrst_{get,set}_val to clarify naming and provide consistency
2022-06-26 16:51:58 -07:00
bc9032da06
Fix uninitialized variables in target sam3x
...
Exposed while building hosted with -Og option
2022-06-26 18:52:12 -04:00
07321a4114
ch32f1: Fixed another broken debug print that made assumptions about %x and %d that are wrong
2022-06-26 14:19:46 -07:00
680a009690
cortexm: Added additional debug information for part probing
2022-06-26 14:19:46 -07:00
b5b2d4dc95
ch32f1: Re-ordered a couple of the operation in ch32f1_probe so it plays nicer with the STM32 parts
2022-06-26 14:19:46 -07:00
0368b76078
ch32f1: Further formatting and layout cleanup
2022-06-26 14:19:46 -07:00
fbc87cc518
ch32f1: Fixed the probe routine distrubing state for other parts wrt `t->idcode`
...
The CH32F1 routine now reads the IDCode into a local.
If the part number matches and appears to be the chip (based on Flash locking), it only then writes the IDCode into `t->idcode`, which is at the point we can only `return true` from the probe routine anyway.
2022-06-26 14:19:46 -07:00
08a8988462
ch32f1: formatting cleanup to bring things closer to inline with the rest of the codebase
2022-06-26 14:19:46 -07:00
2673e34ddd
cortexm: fixed an issue with watchpoint handling and a register sanity check
2022-06-26 13:44:45 -04:00
80c98df2f9
stm32wxxx: CPU2 needs wake-up call and has unexpected PIDR4 in AP1
...
"Single" core STM32WLE still sees AP1 but on first scan aborts gracefully
after some errors and on later runs sees AP1 as unusable. Fixes #832 .
Decode the Cross trigger interface found on CPU2 on STM32WBxx.
2022-06-25 16:52:36 -04:00
471ba19a77
adiv5.c: Read all CIDR data in one call.
...
E.g on STM32WXXX AP1 with C2BOOT not set, the AP base registers have valid
values but reading them fails and turns the AP unusable. BMDA reading CIDR
with multiple calls will will loop and finally hang up BMD. Other target
devices may show similar behaviour.
Reading CIDR with a single call allows recovery from in that case and
additional spares target transactions.
2022-06-25 16:52:36 -04:00
e702afad69
rp: Clean up code a little bit
2022-06-24 20:44:00 -04:00
e67cb9f43c
rp: Update rp_get_flash_length algorithm
...
Try to look for repeating sectors before reverting to reading the
JEDEC ID of the flash chip. This way we don't interrupt the flash
execution if a valid program is running, but can detect the flash
size if the flash memory has been erased.
2022-06-24 20:44:00 -04:00
f2cb13cf36
rp: Add rp_attach and rp_detach callbacks
...
Query JEDEC ID of flash chip on attach to be able to decode flash
chip size.
2022-06-24 20:44:00 -04:00
354e37fbad
rp: Tidy up some other things
2022-06-24 20:44:00 -04:00
ce273889fc
rp: Refector rp_flash_write
...
Fix typo in debug message
2022-06-24 20:44:00 -04:00
f4261c465e
rp: Refactor rp_flash_erase
...
Always align erase length to 4k sector size.
Check that start address and length are actually inside the flash.
2022-06-24 20:44:00 -04:00
dd571467b5
target/sam: slight gpnvm command usage correctness
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-06-24 20:19:47 -04:00
af48a343a8
rp: Add description for SPI flash commands
2022-06-11 11:54:34 -04:00
b43b9a6545
rp: Add erase_sector to command list
...
The command can be used either by specifying the length only, or
the start address and the length like so:
monitor erase_sector <length>
monitor erase_sector <start_addr> <length>
If no start address is specified, it will begin erasing from the
start of the flash sector.
2022-06-11 11:54:34 -04:00
53672f1fc3
rp: Remove CHIP_ERASE command from rp_flash_erase
...
There seems to be a bug in the bootrom for the rp2040 which means
that the chip erase command is not accepted. This is because the
CS pin must be released (set high) directly after sending the chip
erase command (0x60 or 0xC7) (see Winbond W25Q128JV datasheet for
details). Instead the bootrom sends the address after the command,
thus the SPI flash silently ignores the command. Instead, we must
erase each 64KB block one at a time, but thankfull the bootrom
handles this correctly for us.
2022-06-11 11:54:34 -04:00
b1694dfab9
rp: Always use maximum flash size (16MB) when defining flash region
...
There are some cases when the this old method for finding the flash
size will fail, such as if the flash chip has been erased with 0xFF
bytes (rather than blank 0x00 bytes). As this is unreliable,
setting the wrong flash size could cause problems when trying to
inspect memory regions which appear to be out of range.
2022-06-11 11:54:34 -04:00
203c5149e7
rp: Add CORTEXM_TOPT_INHIBIT_SRST to target_options
2022-06-11 11:54:34 -04:00
4ec68023af
cortex-a: Fix compiling for native probe
2022-06-09 04:13:12 -04:00
f6edb54395
Fix RP2040 memory sizes.
2022-06-01 11:41:58 -04:00
2914be1a67
cortexa: Fix the new Watchpoint support causing a no-build
2022-05-31 22:03:21 -04:00
0b7dd00c77
cortexa: Indicate watchpoint as stop reason if there is only one.
2022-05-31 21:58:51 -04:00
b5ef9e5bcf
Implement watchpoints on Cortex-A
2022-05-31 21:58:51 -04:00
1aadcf2678
target/samx7x: handle tcm reconfiguration
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
dcc450a494
target/sam3x: rework gpnvm command
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
cf6ce32371
target: split mem_map_free into ram_map_free and flash_map_free
...
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
2022-05-31 21:48:54 -04:00
8462f5e0d4
target/samx7x: handle tcm config on probe
...
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
2022-05-31 21:48:54 -04:00
508b8d90cc
target/sam3x: name changes to reflect multiple supported families
...
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
430d306511
target: add samx7x probe method
...
adds support for SAME70, SAMS70, SAMV71 and SAMV70
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-05-31 21:48:54 -04:00
2d4d6aa65a
ch32f1: Fixed the assumption that uint32_t is an `unsigned int`
2022-05-31 21:37:02 -04:00
94a0f1587d
ch32f1: Cleaned up some of the formatting
2022-05-31 21:37:02 -04:00
6b465d6a77
Temporarily enable DBG clock in stm32g0_detach(); fixes #1003
2022-04-12 05:39:14 -04:00
e535f53981
remove static vars
2022-04-10 23:40:44 -04:00
844ca65a8f
cosmetic
2022-04-10 23:40:44 -04:00
17dca6f791
tabify
2022-04-10 23:40:44 -04:00
733cf12663
cleanup
2022-04-10 23:40:44 -04:00
17d7dca9ae
build ch32 in its own file
2022-04-10 23:40:44 -04:00
7c120ecb58
put ch32f1 in its own file
2022-04-10 23:40:44 -04:00
04eb33e039
rename to comply to naming scheme
2022-04-10 23:40:44 -04:00
e12939582c
revert function clones_probe
2022-04-10 23:40:44 -04:00
83e3d9c135
disable verification
2022-04-10 23:40:44 -04:00
a3feae60aa
cleanup tabs
2022-04-10 23:40:44 -04:00
fb216a2a98
tabify
2022-04-10 23:40:44 -04:00
9b23265dde
add support for ch32 flash write, it is a bit hackish
2022-04-10 23:40:44 -04:00
90d15e6633
add probe for ch32 + make room for other clones
2022-04-10 23:40:44 -04:00
804a1a4f43
stm32f4: Attach logic cleanup by making sure we only set the extra bits needed when writing DBGMCU_CR
2022-03-31 13:46:29 -04:00
eed1cc81ff
STM32F4: Move DBGMCU_handling to target specific code. Apply for F4 too.
2022-03-31 13:43:52 -04:00
a0c77e216d
adiv5_swdp: Changed the low-level access code to retry till timeout (partial revert of 61efe26)
...
Proper initialisation of the ack value also fixes a potential use-before-init UB
2022-03-29 15:33:23 -07:00
d9ef3ff147
adiv5_swdp: Formatting consistency cleanup
2022-03-29 15:33:23 -07:00
bba2bfdcf4
advi5: Raise the access timeouts as 20ms is too low in some cases
2022-03-29 15:33:23 -07:00
8fb3b7b1a8
reuse exception to avoid using the stack
2022-03-22 10:10:33 -04:00
4fe8fd8944
samd: Fixed the hosted build as the code from #987 assumed unsigned long was 32-bit
2022-03-14 21:38:45 -07:00
e271c16f6c
Removal of MFR descriptions as requested in #978
2022-03-14 21:37:44 -07:00
3bb8c2bf19
jtag_scan: Cleaned up the ones array to use a more correct syntax
2022-03-14 21:37:44 -07:00
75e786da11
jtag_devs: Added a few more parts based on 0170aff and cleaned up the description wording for the existing ones
2022-03-14 21:37:44 -07:00
23534ab174
target: Cleanup in target_new() for the check_error callback
2022-03-14 21:37:44 -07:00
361dc9c234
Revert "adiv5_swdp_scan: If SWD scan fails, try a JTAG scan."
...
This reverts commit 3df692ecb2
2022-03-14 21:37:44 -07:00
d1c9d94174
jtag_scan: Remove the now redundant IDCode parameter from the handlers
2022-03-14 21:37:44 -07:00
27c143a3a3
jtag_scan: Properly fixed the wrong IDCode getting to the handlers
2022-03-14 21:37:44 -07:00
7d2afcff06
Revert "jtag: Make jtag_devs argument to jtag_handler."
...
This reverts commit 6308506276
2022-03-14 21:37:44 -07:00
024152b03e
Revert "jtag_scan: Deliver full idcode to the handler."
...
This reverts commit 1845d71f00
2022-03-14 21:37:44 -07:00
02d9a1d3cf
Revert "jtag_scan: Rework chain detection"
...
This reverts commit 2d4a503135
2022-03-14 21:37:44 -07:00
4045406ed8
Added support for fine-grained bootloader and flash locking in samd.c
...
lock_flash and lock_bootprot currently support only locking the whole flash and locking the maximal leading flash chunk (32k).
An optional numerical parameter is added. It can be specified in decimal or 0x prefixed hexadecimal.
For samd21 'lock_bootprot 0' locks the first 32k of flash while 'lock_bootprot 6' locks the first 512 bytes. 'lock_bootprot 0' is equivalent to 'unlock_bootprot'.
Similarly, 'lock_flash <number>' locks the flash segments corresponding to zeros in the binary representation of the given number.
'lock_flash 0xffff' is equivalent to 'unlock_flash'.
If the optional parameter is not given both commands work as previously.
2022-03-14 00:26:31 -07:00
c1a12edbe9
kinetis: Clarify arguments to kl_gen_command
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gcc11 chokes on the old setup
2022-03-13 19:48:38 -07:00
d594b42976
Cortexm: With connect under reset, keep the device halted until attach.
2022-01-22 14:07:42 +01:00
8def28dee9
Add option bit support for STM32WLxx
...
Support for read/write/erase option bits.
Signed-off-by: Frank Kunz <mailinglists@kunz-im-inter.net>
2022-01-02 12:29:03 +01:00
c832cb04e7
samd: add support for SAMD09
...
The SAMD09 CPU is used in boards such as the Adafruit Seesaw. It has a
smaller amount of memory and flash than other SAMD ports.
This was tested with an Adafruit Seesaw. These boards come with preloaded
firmware. As a test, the firmware was dumped and flash was erased. Then,
flash was verified to be all zeroes. Finally, the firmware was loaded
back in:
(gdb) p/x *(unsigned int *)0@32
$8 = {0x20000f88, 0x1db, 0x1d1, 0x1d9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d9, 0x0, 0x0, 0xf5, 0x1081, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x0, 0x1d9, 0x1d9, 0x25e9, 0x0,
0x0, 0x1d9, 0x1d9, 0x1d9}
(gdb) dump ihex memory flash.ihex 0 8192
(gdb) mon erase_mass
Erase successful!
(gdb) p/x *(unsigned int *)0@32
$9 = {0xffffffff <repeats 32 times>}
(gdb) load flash.ihex
Loading section .sec1, size 0x2000 lma 0x0
Start address 0x00000000, load size 8192
Transfer rate: 5 KB/sec, 910 bytes/write.
(gdb) p/x *(unsigned int *)0@32
$10 = {0x20000f88, 0x1db, 0x1d1, 0x1d9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d9, 0x0, 0x0, 0xf5, 0x1081, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x1d9, 0x0, 0x1d9, 0x1d9, 0x25e9, 0x0,
0x0, 0x1d9, 0x1d9, 0x1d9}
(gdb)
Signed-off-by: Sean Cross <sean@xobs.io>
2021-12-29 15:25:51 +01:00
d00607f71a
samd: parameterize memory and flash sizes
...
Various SAMD devices have different amounts of memory. Up until now, all
SAMD devices have had the same amount, and therefore this value was
hardcoded to 32k of RAM and 256k of flash.
Add a parameter to the description field and set it to default to the
previous values. Use this description field when adding memories to the
target definition.
Signed-off-by: Sean Cross <sean@xobs.io>
2021-12-29 15:25:51 +01:00
d4cd81fa36
start_time undeclared if ENABLE_DEBUG=1
2021-11-21 12:57:30 +01:00
73b4612ec7
adiv5_swdp: Initialize a volatile variable
...
GCC did not warn about possibly missing initialization and so for gdb target
was not recognized.
2021-11-20 22:38:35 +01:00
5cb501049a
adiv5_swdp/scan: Handle parity errors, seen with NRF52 with SYSTEMOFF #381/#949
2021-11-18 22:59:17 +01:00
92d6056711
STM32G0 OTP area programming
2021-11-15 21:19:08 +01:00
73624826b6
semihosting exit code
2021-11-14 12:03:33 +01:00
181466549b
adiv5: Progressive incrementing TRNCNT for the DHCSR write when trying to halt
...
Workaround for CMSIS-DAP/Bulk debugger orbtrace that returns NO_ACK
with high values of TRNCNT. Perhaps only STM32F767 needs write to DHCSR
with high occupancy to catch the device in a moment not sleeping.
2021-10-31 12:55:41 +01:00
88e44d1c12
cmsis: use exception in wait_word().
2021-10-31 12:55:41 +01:00
a1d4649795
SWD: Use dp_low_write to allow multidrop scan.
2021-10-31 12:55:41 +01:00
4f36c1ddf8
Remove dp_low_read() and use exception protected dp_read()
2021-10-31 12:55:41 +01:00
d144f9d54b
adiv5: CMSIS DAP transactions are slow but work in principle
...
Slowness results in strange STM32F767 DHCSR implementation to nearly never
halt in the given 2 second period when F767 is sleeping most of the time.
2021-10-31 12:55:41 +01:00
761e0230d4
cmsis-dap: Print messages when transfers fail.
...
Expect signal integrity errors when using jumper cables. Often probes switch
the SWJ GPIO with highest speed, resulting in possible reflections. Additional
ground wires may help. If there is isolation between probe and targets,
additional ground wires are a must or ground shift will wrack the transfer!
2021-10-31 12:55:41 +01:00
c13778139f
adiv5/hosted: Export the BMP_TYPE in DP.
2021-10-31 12:55:41 +01:00
b7e7aa3f9a
adiv5: Either use only LL functions in cortexm_initial_halt or no LL at all.
...
Platform implementation may disturb ADIV5_AP_DRW and so low_read DHCSR may
give values other from registers
2021-10-31 12:55:41 +01:00
8845a22226
stm32l4: Use targetid when available.
...
Fixes STM32U5 from crashing.
2021-10-31 11:13:34 +01:00
5dafc0828c
SWD: Remove excessive line resets.
2021-10-31 11:12:46 +01:00
7307f086c6
Support for STM32WB55 ( #942 )
...
* add STM32WB55 support
2021-10-30 13:01:06 +02:00
e1a928beb1
Fixes to compile with gcc11 #925
...
Target code changes are pure for formal correctness and not tested!
2021-10-10 15:59:57 +02:00
b076d5cea1
stm32f1: Check if unlock failed and propagate error.
2021-09-22 21:41:43 +02:00
554e34517e
Better reporting when monitor command fails.
2021-09-22 21:41:43 +02:00
9e98cfa220
adiv5: Remove leftover debug output.
2021-09-22 21:41:43 +02:00
9ebc44bcea
Make more functions static.
2021-09-22 15:16:20 +02:00
9de69bb3ab
Adiv5/Initial halt: More fixes for dd28fa5743. #925
...
Stlink does not like low level access and aborts with STLINK_SWD_DP_ERROR.
Either our implementation still has faults or stlink can not handle
MINDP devices with BMP/Firmware also seemm not to like low level access,
either du to some hidden error in BMP or by design
2021-09-22 15:16:20 +02:00
a9854e9b37
adiv5: Fix the MINDP case introduced with dd28fa5743 #925
2021-09-16 12:39:26 +02:00
f66caa0d29
add some more nxp s32k14x variants
...
the sdid bits correspond to s32k14x as well as s32k11x but i only have
access to the k14x variants so didn't bother w/ the k11x variants.
the memory/flash sizes also can come from the sdid bits, but the
splits still need to come from a lookup.
2021-09-13 23:01:05 +02:00
95288bcf75
fix a size format warning
2021-09-13 23:01:05 +02:00
dd28fa5743
adiv5: Tighten up loop to initial halt cortexm
...
Use TRNCNT when available.
Now the F767 with the NutOS 300 ms sleep example with the one ms tick is
halted even in hosted after few ms.
2021-09-04 21:15:07 +02:00
863a41daac
adiv5_swdp: Initialize initial_dp with the definition
2021-08-15 16:43:29 +02:00
6308506276
jtag: Make jtag_devs argument to jtag_handler.
2021-08-15 16:43:29 +02:00
6dff2a9f31
target: target_error_check now defaults to not indicate error.
...
Remove unneeded nop_function from efm32
2021-08-15 16:43:29 +02:00
3df692ecb2
adiv5_swdp_scan: If SWD scan fails, try a JTAG scan.
2021-08-15 16:43:29 +02:00
2d4a503135
jtag_scan: Rework chain detection
...
Fixme: stlinkv2/hosted probably does only handle STM devices. Check if
jtag_devs.c really needed.
2021-08-15 16:43:29 +02:00
1845d71f00
jtag_scan: Deliver full idcode to the handler.
2021-08-15 16:43:29 +02:00
c7bc4b6a5d
Bug fix in Flash erase function for LPC MCUs.
2021-08-13 16:18:53 +02:00
72bd825a60
Add support for NXP LPC11xx XL series, add 'readuid' command for some MCUs of the LPC11xx series where it was missing; add comments mapping Device IDs to part descriptions.
2021-07-31 16:08:34 +02:00
0c63903071
adiv5: Recover from bad AP access.
...
E.g. AP1 on a STM32WLE5 points to a ROM table, but access to the ROM table
via AP1 hangs forever.
- Substantial reduce timeout when wait for a response. Valid access should
succeed fast.
- Abort AP access to free DP for other accesses
- Don't throw exception, only set dp->fault
- React on higher level
2021-07-15 15:06:54 +02:00
5ea01030e2
Add nRF51 command for (only) erasing the UICR registers
...
Original implementation by: Benjamin Vedder <benjamin@vedder.se>
2021-06-07 13:50:36 +02:00
4b8c4990dc
Fix warning about unused variable in adiv5.c
...
This happens if the platform has debugging support but debugging
is not enabled.
2021-06-03 12:56:41 +02:00
711a87f7ba
Fix some warnings when compiling with -Wshadow
...
There are still a few more places that would need to be corrected
before -Wshadow could be added by default.
2021-06-03 12:55:28 +02:00
891633322a
lpc: Care for protected pages on LPC80x devices.
2021-06-01 16:23:19 +02:00
f7b4697280
lpc11xx/lpc8c04: Do not expose two top system flash sectors.
2021-06-01 16:23:19 +02:00
42ebcac329
efm32_devices: Rearrange struct efm32_device_t to save flash space.
2021-06-01 16:23:19 +02:00
21a702dc1e
lpc: More verbosity and more definitions
2021-06-01 16:23:19 +02:00
87acd99fe4
cortexm: For Cortex-M0+ devices, probe also for lpc11 to detect LPC80 #884
2021-05-18 12:24:00 +02:00
517d5b5b31
rp: Show spinner only when called from monitor command.
2021-05-16 11:26:14 +02:00
0ab10fee0b
rp: Increase timeout for flash_range_program
...
If the RP2040 is using the ring oscilator (ROSC) rather than the crystal
oscilator (XOSC) then flashing program will take much longer. As the XOSC is not
enabled at boot we should not assume it will be enabled before the debugger is
connected (or indeed at all), thus should use the longer timeout during load
commands.
2021-05-16 11:26:14 +02:00
ff30259354
rp: Add more debug logging during flash
2021-05-16 11:26:14 +02:00
dragonmux
grumat
ylm
Rafael Silva
Giovanni Santana
Piotr Esden-Tempski
Anti Sullin
Jonathan Giles
SId Price
Maciej Musiał
Uwe Bonnes
James Turton
Dag Ågren
Gareth McMullin
Rafael Silva
Michal Moskal
mean
arpadbuermen
Frank Kunz
Sean Cross
Koen De Vleeschauwer
fabalthazar
SG
dpc
Thiadmer Riemersma
Björn Mellström