Commit Graph

425 Commits

Author SHA1 Message Date
Uwe Bonnes e4421799ba More header cleanup 2021-05-15 12:54:51 +02:00
Uwe Bonnes f9414d5826 cmsis-dap: Handle ADI DP22 devices on probes not multidrop capable. 2021-04-26 18:18:18 +02:00
Uwe Bonnes 1f67bab475 nxpke04: Move unsafe_enables to target bool union. 2021-04-25 16:03:23 +02:00
Uwe Bonnes f87dff8d83 kinetis: Remove static variables, add word union to target_s.
Add a word union to target structure to hold a single word variable.
2021-04-25 16:03:23 +02:00
Uwe Bonnes ac7c1057cc efm32/samd/samx5x: Remove static allocates strings. Allocate in priv_storage.
Static allocated variables in the different targets eat up common RAM and
will collide in chains with multiple similar targets.
2021-04-25 16:03:23 +02:00
Uwe Bonnes cddf02f174 samx5: Verbose error reports on protected devices. 2021-04-25 16:03:23 +02:00
Uwe Bonnes 8c8aa980cf adiv5: Detect unprotected SAMD5x only once 2021-04-25 16:02:20 +02:00
Uwe Bonnes 1b26ff560d rp.c: Add reset_usb_boot as monitor command 2021-04-24 14:48:58 +02:00
Uwe Bonnes 52bffa70cf rp: Handle flash.
- Beware, after reset, only a valid flash payload get mapped to XIP!
  Only 0 is read from flash when flash image is not valid
2021-04-21 21:55:03 +02:00
Uwe Bonnes 2b0e255c40 cortexm: timeout and debug for run_stub() 2021-04-21 21:50:38 +02:00
Uwe Bonnes 61efe26348 swdp_scan: Break infinite loop after Dormant->SWD transition. 2021-04-21 21:50:38 +02:00
Uwe Bonnes fa5e69e3be RP 2040: Special handling for rescue DP
As the rescue DP provided no AP, trigger the reset with attach().
However attach will indicate failure also reset/halt has succeeded.
2021-04-21 21:50:38 +02:00
Uwe Bonnes ea92c8b8c8 cmsis-dap: Allow to use adiv5_swdp_scan. 2021-04-21 21:50:38 +02:00
Uwe Bonnes 23f942ac8c Raspberry RP2040: Recognize. No flash handling yet. 2021-04-21 21:50:35 +02:00
Uwe Bonnes 04d1c9805b swd: Remove swd_proc and swdptap.h. 2021-04-21 21:50:04 +02:00
Uwe Bonnes b6fbf86743 Extend ADIv5_DP_t for low level routines needed for multi-drop.
Will replace swd_proc
2021-04-21 21:50:04 +02:00
Uwe Bonnes 5abb288c7a hosted: Provide the DP functions in swd_proc. 2021-04-21 21:50:04 +02:00
Uwe Bonnes fa561c8d66 adiv5_swdp: Starting point to handle multi-drop
- RP2040 show both DPs
- Multidrop test with STM32L552 and STM32H745 allows selection
  with "-m 0x4500041" (H7), "-m 1" (L552) or "-m 0x01002927" (RP2040)
2021-04-21 21:50:04 +02:00
Uwe Bonnes be3bfc48a8 cortexm: M33 has up to 8 hardware breakpoints 2021-04-21 21:22:59 +02:00
Uwe Bonnes b1ac4187b9 Fix some formatting strings for 32-bit compile 2021-04-21 21:22:59 +02:00
Fabio Baltieri beaccf2714 target: stm32l4: add support for STM32WLxx
This adds support for the STM32WL series in stm32l4.c. These parts have
the same flash registers layout as the L4 series, but a different base.
Since there are already two sets of registers in this target file, this
adds support for register maps that can be customized for each device
ID.
2021-04-20 18:42:36 +02:00
Fabio Baltieri f55ad67b1b adiv5: catch timeout on adiv5_ap_read_id and abort
This adds a TRY_CATCH around the adiv5_ap_read_id() in
adiv5_component_probe() and resets the DP when that happens.
It seems like the STM32WLE5 comes with the AP of the inactive core
enabled in a way that does not make it detectable, and the current code
times out and leaves the whole device hanging.

Catching the timeout and calling adiv5_dp_abort() seems to restore the
device to a useable state.

Tested on Seed LoRa-E5 (STM32E5JC).
2021-04-19 16:57:13 +02:00
fabalthazar d6b24c00c8 Fixed STM32G43x/G44x option bytes support
Previously took L4 values so FLASH_SEC1R was not applied
2021-04-17 14:44:30 +02:00
fabalthazar 99f9557cc0 Support for STM32G49x/G4Ax (category 4) 2021-04-17 14:44:30 +02:00
fabalthazar c85c946ce3 PRIx32 fix 2021-04-17 14:44:30 +02:00
Uwe Bonnes a6a8606edb STM32L55: Detect, memory map, read and flash write. Options handling missing.
Only non-secure states considered!
2021-04-04 17:26:31 +02:00
fabalthazar 6d6cfd6c98 Comprehensive STM32G03/4/5/6/7/8/B/C driver 2021-03-29 21:42:40 +02:00
Uwe Bonnes 58f153e12b cortexm: Always halt and release reset before romtable scan
Only release from halt once after romtable scan
Should fix #836.
2021-03-26 17:43:11 +01:00
Uwe Bonnes a025c9a7bd Revert "stm32f1: On ST parts there is no need to read IDCODE again."
Romtable partno is not unique for devices, e.g. in STM32F0
This reverts commit f89b07d892.
2021-03-26 17:35:00 +01:00
Uwe Bonnes f89b07d892 stm32f1: On ST parts there is no need to read IDCODE again.
IDCODE is already known from the Romtable
Probably this has the same effect as #836
2021-03-12 20:45:34 +01:00
Uwe Bonnes 7859a2aabd adiv5_swd: Factor out creation of packet request. 2021-03-06 13:30:09 +01:00
Uwe Bonnes cfb784d428 adiv5: Fix comments and debug output 2021-03-05 16:49:19 +01:00
Thiadmer Riemersma 560a046a22 Add support for NXP LPC802, LPC804, LPC832 and LPC834 2021-02-22 19:37:46 +01:00
Uwe Bonnes 0df44e205b ADIv5: Abort Romtable scan also if CIDR0 is invalid after halting #832
STM32WLE5 has the same dual core chip as STM32WL5. For the second
core, the additional AP can be see, but access to e.g. CIDR0 for that
Romtable fails.
Aborting the scan too if again the second read of CIDR0 fails makes
sense anyways!
2021-02-19 18:48:02 +01:00
Uwe Bonnes c776e7a9a6 swd_scan: Add '-m' as targetid argument to swd_scan to prepare multi-drop.
In a real multi-drop setup, the device to use must be specified.
2021-02-15 17:47:29 +01:00
Uwe Bonnes 8e2f6937d5 hosted: Run target specific monitor commands with -M "command" .
Lists available commands: "blackmagic -M help"
Quote multi argument monitor commands, e.g. STM32F1: blackmagic -M "option help"
2021-02-15 17:47:29 +01:00
Uwe Bonnes 165560edd8 cl_utils: target selection '-n' argument needs optarg.
foreach now returns the number of targets.
2021-02-15 17:47:29 +01:00
Alex Norman 42f590ce0b fixing some memory map errors for stm32h7, PR #821 2020-12-23 20:10:39 +01:00
Sean Cross 2b06f045c4 target: kinetis: add S32K148
This adds support for the NXP S32K148. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-12-16 12:49:23 +01:00
Noah Pendleton 020600aa56 target/lpc546xx: fix lpc546xx flash support (#801)
**Summary**
Modifications to fix flash support on the lpc546xx:

- fix IAP entrypoint to be `0x03000204`, not the value at that address
- add a reset and attach sequence before erasing flash sectors. there's
little documentation around this, but experimentally, erasing sector 0
fails when the ROM bootloader is mapped to it (on reset). stepping the
chip once and attaching is enough to snap the chip out of it, permitting
flash erase on sector 0.
- add a few test commands to the lpc546xx table (read_uid, erase/write
sector, etc).
- write the magic CRC value when writing to sector 0
(`lpc_flash_write_magic_vect`).
- move the lpc546xx probe to before the lpc43xx probe, to prevent
getting the lpc546xx into Lockup when reading an illegal memory location
during lpc43xx probing

Fixes #786.

I don't 100% understand the reset/load sequence of this part, but these
changes are sufficient to program and debug the part now.

I didn't do a detailed analysis of what pyocd (via st-link hardware
adapter) and segger jlink do to handle the same, but both of those
worked without modification, so there's some difference in the
sequence they're using.

**Testing**
Verified I can now successfully erase and write an executable in sector
0 (and other sectors).
Verified the new commands work correctly.
2020-12-12 19:48:05 +01:00
Aaron Lindsay 518529a772 Support GD32E23x 2020-12-12 18:29:30 +01:00
Uwe Bonnes dd6aadc54d jtag: Add verbosity about devices found. 2020-12-06 15:18:08 +01:00
Stoyan Shopov e318f884bf Change the type of 'cortexm_wait_timeout' to unsigned.
It makes sense that the timeout value is unsigned, it also
resolves build errors on some platforms.
2020-12-04 11:44:50 +01:00
mean e3fd12ebc6 gd32f1/f3 detection and ram/flash autoset 2020-12-03 11:16:47 +01:00
Jonathan Giles 575c25e570 Add support for STM32F1 clone with new AP_DESIGNER id 2020-12-01 10:23:16 +01:00
Uwe Bonnes 48a79ff9da adiv5: More checks for a sensible DPIDR. 2020-11-29 21:11:11 +01:00
Uwe Bonnes 752bc26536 adiv5: Fix memleak with duplicated base. 2020-11-29 21:11:11 +01:00
Uwe Bonnes acec489647 adiv5_jtagdp: Always set idcode. 2020-11-29 21:11:11 +01:00
Uwe Bonnes f45c56af83 adiv5/swdp: Check early for valid DP idcode. 2020-11-29 15:48:50 +01:00
Uwe Bonnes 7df314e265 Firmware/Jlink: Fix double free when debug power-up fails (#780) 2020-11-29 15:48:50 +01:00
Uwe Bonnes bf548e92c0 swd: After write low_access, always append 8 clk to move data through SW-DP.
Especially needed when leaving the debugger or during debug unit power-up.

ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
tells to clock the data through SW-DP to either :
- immediate start a new transaction
- continue to drive idle cycles
- or clock at least 8 idle cycles

Implement last option to favour correctness over slight speed decrease

Implement only for adapters where we assemble the seq_out_parity in our code,
as on firmware, ftdi and jlink. Hopefully the high level adapters do it right.

Reverts 2c33cde63f and
cde7726b87
2020-11-27 22:26:48 +01:00
Uwe Bonnes 3ee31473c6 cortexm.c: LPC15xx has designer 43b and Partno 4c3
Thanks to JojoS!
2020-11-27 22:26:48 +01:00
Uwe Bonnes 19e1fddba2 adiv5: Remove unnescessary read. 2020-11-27 22:26:48 +01:00
Uwe Bonnes cda83d3084 Fix memleaks.
Happened e.g. when Stlink could not enter debug or when cortexm_prepare timed out.
2020-11-27 22:26:48 +01:00
Uwe Bonnes 9ac5adfcef adiv5: Additional decoding. 2020-11-27 22:26:48 +01:00
Uwe Bonnes d78d7838d3 stm32f1: Always read DBGMCU_IDCODE for t->idcode (#770)
At least STM32F042 has 0x440 as romtable partno vs 0x445 as DBGMCU_IDCODE.
Thanks to Andrey Melnikov(aam335) for pointing out!
2020-11-27 22:26:48 +01:00
Uwe Bonnes 653d486ee2 cortexm: Store CPUID in target structure. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 80154c5c7a adiv5_swdp: Fix more memory leak. 2020-11-27 22:26:48 +01:00
Noah Pendleton 35bcb4f7c6 Switch on the lpc546xx target
Enable the lpc546xx target. Tested on the LPCXpresso54628 dev board,
able to flash and debug.
2020-11-24 21:32:39 +01:00
Sean Cross e9c02296f2 target: kinetis: add S32K118
This adds support for the NXP S32K118. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-11-14 13:06:23 +01:00
jbuonagurio f18be6ef7a Add support for Kinetis K12 and placeholders for other K-series MCUs 2020-11-07 12:44:05 +01:00
Uwe Bonnes 2c33cde63f cortexm.c/cortexm_halt_resume: Add some clock cycles to always get CPU going (#768) 2020-11-01 21:53:23 +01:00
Uwe Bonnes 1f7a716710 adiv5.c: Run cortexm_prepare on all suspected CortexM instances.
Gets all debug units of the second CPU of a STM32H745 visible.
2020-10-23 09:40:15 +02:00
Uwe Bonnes 18673d9a56 adiv5: Rework DP/AP refcounting.
ASAN non longer reports leaks with the STM32H745.
2020-10-23 09:40:15 +02:00
Uwe Bonnes f76a7c4e92 adiv5: Release devices after scan.
Before, scanning only kept device stopped until POR or attach/detach cycle.
2020-10-23 09:40:15 +02:00
Uwe Bonnes 59dc1b7eb4 cortex-m7: Give hint about buggy core revision. 2020-10-23 09:40:15 +02:00
Uwe Bonnes 976c763747 jtag remote: Start fixing handling M0 (second jtag) for LPC4322 in high-level
- LPC11: Only print none-null unknown idcodes.
2020-10-23 09:40:15 +02:00
Uwe Bonnes c161521c26 cortexm: Designer ARM must be in the default path when probing. 2020-10-23 09:40:15 +02:00
Uwe Bonnes cdd07544d5 Cortexm: Allow pure debug on devices not yet handled for flashing
- Recognize STM32L552 and MIMXRT10XX
- Fix another PIDR
- Fix bad debug print string.
2020-10-23 09:40:15 +02:00
Uwe Bonnes 0ffb4f7b18 cortexm: Fix protected SAM detection
- Only run cortex_prepare() if reading cidr fails
- With Atmel DSU detected, run cortexm_probe()
2020-10-17 12:49:37 +02:00
Uwe Bonnes 5bc743d221 samd: Propagate security after setting security by chip reset. 2020-10-17 12:49:37 +02:00
Uwe Bonnes 8b929c12c9 hosted/jtag: Transfer jtag_devs to firmware. 2020-10-16 20:03:03 +02:00
Uwe Bonnes 3d92b82678 jtag: Use index and not device structure for jtag_dev_write_ir and jtag_dev_shift_dr 2020-10-16 20:03:03 +02:00
Uwe Bonnes 7ccf0d3e03 jtag_dev_t: Make dev, idcode and desc less generic.
No codechange intended.
2020-10-16 20:03:03 +02:00
Uwe Bonnes 87b546777a nrf51: Be more verbose about the protection status. 2020-10-16 12:16:33 +02:00
Richard Meadows 4108b649c2 stm32h7: Add support for new product lines
Add support for:
* STM32H7B3/B0/A3 (RM0455)
* STM32H723/33/25/35/30 (RM0468)

Successfully tested with:
* STM32H7A3ZIT (RM0455)
* STM32H747XIH (check for regressions)
2020-10-10 22:09:34 +02:00
Uwe Bonnes 877b4be8ee cortexm: Restrict probing by using the ap_designer.
More designers need to be observed and reported by users and added.
Request users to send needed data.
2020-10-07 20:12:35 +02:00
Uwe Bonnes 91d1ef8bf6 target/stm32: Use t->idcode with probe. 2020-10-07 20:12:35 +02:00
Uwe Bonnes 44bfb62715 Adiv5: Print Designer/Partno when device is not recognized
t->idcode is now 16 bit.
2020-10-07 20:12:35 +02:00
Uwe Bonnes c456fc7f61 adiv5: Store AP designer and partno in the AP structure. 2020-10-07 20:12:32 +02:00
Uwe Bonnes 159196c2ad Cortexm: Remove forced_halt. 2020-10-07 20:11:33 +02:00
Uwe Bonnes 9bb2807706 adiv5/romtable: Prepare CortexM devices to read the ROMTABLE
It seems, writing to DHCSR fails silent when the device is sleeping.
Reading DHCS during sleep may return nonsense.
Repeated write may at some point catch the device running and succeed.
With devices sleeping for long time and running on faster clock the
chance for a successful hotplug gets smaller.

- Try hard to halt a sleeping device
- Prepare vector catch and enable all debug units by TRACENA
- Release reset
- Apply device specific fixes
-- STM32F7: Store old value of DBGMCU_CR, enable debug in sleep in
   DBGMCU before reading PIDR and restore DBGMCU on detach.

Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
2020-10-07 20:11:17 +02:00
Gareth McMullin dc8924a2bc
stm32h7: Don't tc_printf from flash functions (#747)
* stm32h7: Don't tc_printf from flash functions

Receving an 'O' packet while flashing confuses GDB and then
weird stuff happens.

* Replace tc_printf with DEBUG_WARN
2020-10-05 10:45:18 +02:00
Uwe Bonnes 014abf6cc9 adiv5.c: Reduce number of errors if reading cidr fails. 2020-10-01 15:33:28 +02:00
Uwe Bonnes be40d2b851 adiv5: Check Debug Base Address early
Reduces printout when scanning the romtable
2020-10-01 15:22:17 +02:00
Eivind Alexander Bergem 38bc5bbf82 Add LPC546xx support #741 #553 2020-09-30 12:56:53 +02:00
Uwe Bonnes 2fdd94adeb STM32F7: Add another missing Arch ID. 2020-09-24 16:20:34 +02:00
Uwe Bonnes bdb351a6ea adiv5_swdp: On ACK_FAULT, error() and try again once #731
when writing CSW.
2020-09-18 20:07:32 +02:00
Damien Merenne 120b3134bb Add SAM4SD32C/B support. 2020-09-07 17:36:15 +02:00
Uwe Bonnes 8a2bce26f2 Hosted: Fix memory leak when platform_swdptap_init fails. 2020-09-04 11:49:13 +02:00
David Lawrence f65afb1588 Use correct IAP entry address for LPC84x 2020-08-14 20:00:18 +02:00
Uwe Bonnes 71e9d78210 adiv5.c: Add another ARCH_ID found STM32F205. 2020-08-01 14:00:17 +02:00
Uwe Bonnes 1b12e407fd adiv5: Add missing arch identifiers for Cortex-M7 ETM. 2020-07-31 11:53:15 +02:00
Francesco Valla 696daa8352 adiv5: fix debug print of dev_type
Since dev_type is an 8 bit unsigned integer, use the PRIx8 macro instead
of PRIx32.
2020-07-29 11:32:24 +02:00
Uwe Bonnes 726d4b4496 adiv5.c: Add missing DEVTYPE and ARCHID to some existing PIDRs(#698,#699)
Probably more additions are needed.
2020-07-14 16:26:32 +02:00
Uwe Bonnes 09ceaea70f adiv5_swdp: Fix another memory leak. 2020-07-14 15:02:13 +02:00
Fredrik Ahlberg 7ebb94d134 cortexm: Add comment on CPUID register 2020-07-12 22:54:39 +02:00
Fredrik Ahlberg 4391851f4d adiv5: Change component descriptions from MTB to Micro Trace Buffer for consistency 2020-07-12 22:29:04 +02:00
Fredrik Ahlberg 0aadd0abce Adiv6: Add comment on DEVTYPE and ARCHID fields with references 2020-07-12 22:27:46 +02:00
Fredrik Ahlberg fcd945a529 cortexm: Read CPUID to identify core version 2020-07-12 12:08:22 +02:00