Commit Graph

108 Commits

Author SHA1 Message Date
dragonmux 733d8ddc19 adiv5: Fix the invalid AP handling loop so that we don't stop early and bail out before time.
This improves target detection reliability.
2022-07-30 16:43:43 -07:00
ylm 4d64edad7a fix: Use standard macros for debug message formating 2022-07-29 21:22:17 +01:00
dragonmux 57fec4d0b6 adiv5: Cleaned up a couple of the debug prints 2022-07-29 21:22:17 +01:00
Rafael Silva 8b5206fb8d target: add weak aliasing to allow disabling targets
Signed-off-by: Rafael Silva <perigoso@riseup.net>
2022-07-26 05:08:10 +01:00
dragonmux 6f81cb6a68 adiv5: Removed an extraneous pair of perens as they suppress desirable warnings 2022-07-25 18:28:57 +01:00
dragonmux 3592658a26 adiv5: Cleaned up the loop in adiv5_ap_read_id 2022-07-25 18:28:57 +01:00
dragonmux bb3e74062e adiv5: Fixed the naming of a timeout in cortexm_prepare 2022-07-25 18:28:57 +01:00
Rafael Silva 013b2dee60 target/adiv5: further cleanup 2022-07-25 18:28:57 +01:00
Rafael Silva 0942d7047a target/adiv5: saner designer code handling and cleanup
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
2022-07-25 18:28:57 +01:00
Rafael Silva d1fa50336e target/adiv5: clang format/tidy 2022-07-25 18:28:57 +01:00
dragonmux 0dae6a4019 misc: Renamed connect_assert_nrst to clarify usage and align naming 2022-06-26 16:51:58 -07:00
dragonmux a8e12d716d misc: Renamed platform_nrst_{get,set}_val to clarify naming and provide consistency 2022-06-26 16:51:58 -07:00
Uwe Bonnes 80c98df2f9 stm32wxxx: CPU2 needs wake-up call and has unexpected PIDR4 in AP1
"Single" core  STM32WLE still sees AP1 but on first scan aborts gracefully
after some errors and on later runs sees AP1 as unusable. Fixes #832.

Decode the Cross trigger interface found on CPU2 on STM32WBxx.
2022-06-25 16:52:36 -04:00
Uwe Bonnes 471ba19a77 adiv5.c: Read all CIDR data in one call.
E.g on STM32WXXX AP1 with C2BOOT not set, the AP base registers have valid
values but reading them fails and turns the AP unusable. BMDA reading CIDR
with multiple calls will will loop and finally hang up BMD. Other target
devices may show similar behaviour.
Reading CIDR with a single call allows recovery from in that case and
additional spares target transactions.
2022-06-25 16:52:36 -04:00
Uwe Bonnes eed1cc81ff STM32F4: Move DBGMCU_handling to target specific code. Apply for F4 too. 2022-03-31 13:43:52 -04:00
Uwe Bonnes d594b42976 Cortexm: With connect under reset, keep the device halted until attach. 2022-01-22 14:07:42 +01:00
Koen De Vleeschauwer d4cd81fa36 start_time undeclared if ENABLE_DEBUG=1 2021-11-21 12:57:30 +01:00
Uwe Bonnes 181466549b adiv5: Progressive incrementing TRNCNT for the DHCSR write when trying to halt
Workaround for CMSIS-DAP/Bulk debugger orbtrace  that returns NO_ACK
with high values of TRNCNT. Perhaps only STM32F767 needs write to DHCSR
with high occupancy to catch the device in a moment not sleeping.
2021-10-31 12:55:41 +01:00
Uwe Bonnes d144f9d54b adiv5: CMSIS DAP transactions are slow but work in principle
Slowness results in strange STM32F767 DHCSR implementation to nearly never
halt in the given 2 second period when F767 is sleeping most of the time.
2021-10-31 12:55:41 +01:00
Uwe Bonnes b7e7aa3f9a adiv5: Either use only LL functions in cortexm_initial_halt or no LL at all.
Platform implementation may disturb ADIV5_AP_DRW and so low_read DHCSR may
give values other from registers
2021-10-31 12:55:41 +01:00
Uwe Bonnes 9e98cfa220 adiv5: Remove leftover debug output. 2021-09-22 21:41:43 +02:00
Uwe Bonnes 9de69bb3ab Adiv5/Initial halt: More fixes for dd28fa5743. #925
Stlink does not like low level access and aborts with STLINK_SWD_DP_ERROR.
Either our implementation still has faults or stlink can not handle

MINDP devices with BMP/Firmware also seemm not to like low level access,
either du to some hidden error in BMP or by design
2021-09-22 15:16:20 +02:00
Uwe Bonnes a9854e9b37 adiv5: Fix the MINDP case introduced with dd28fa5743 #925 2021-09-16 12:39:26 +02:00
Uwe Bonnes dd28fa5743 adiv5: Tighten up loop to initial halt cortexm
Use TRNCNT when available.

Now the F767 with the NutOS 300 ms sleep example  with the one ms tick is
halted even in hosted after few ms.
2021-09-04 21:15:07 +02:00
Uwe Bonnes 0c63903071 adiv5: Recover from bad AP access.
E.g. AP1 on a STM32WLE5 points to a ROM table, but access to the ROM table
via AP1 hangs forever.
- Substantial reduce timeout when wait for a response. Valid access should
  succeed fast.
- Abort AP access to free DP for other accesses
- Don't throw exception, only set dp->fault
- React on higher level
2021-07-15 15:06:54 +02:00
Björn Mellström 4b8c4990dc Fix warning about unused variable in adiv5.c
This happens if the platform has debugging support but debugging
is not enabled.
2021-06-03 12:56:41 +02:00
James Turton f880734050 Fix compiling for native probe 2021-05-16 11:26:14 +02:00
Uwe Bonnes 8c8aa980cf adiv5: Detect unprotected SAMD5x only once 2021-04-25 16:02:20 +02:00
Uwe Bonnes ea92c8b8c8 cmsis-dap: Allow to use adiv5_swdp_scan. 2021-04-21 21:50:38 +02:00
Uwe Bonnes 23f942ac8c Raspberry RP2040: Recognize. No flash handling yet. 2021-04-21 21:50:35 +02:00
Uwe Bonnes fa561c8d66 adiv5_swdp: Starting point to handle multi-drop
- RP2040 show both DPs
- Multidrop test with STM32L552 and STM32H745 allows selection
  with "-m 0x4500041" (H7), "-m 1" (L552) or "-m 0x01002927" (RP2040)
2021-04-21 21:50:04 +02:00
Uwe Bonnes b1ac4187b9 Fix some formatting strings for 32-bit compile 2021-04-21 21:22:59 +02:00
Fabio Baltieri f55ad67b1b adiv5: catch timeout on adiv5_ap_read_id and abort
This adds a TRY_CATCH around the adiv5_ap_read_id() in
adiv5_component_probe() and resets the DP when that happens.
It seems like the STM32WLE5 comes with the AP of the inactive core
enabled in a way that does not make it detectable, and the current code
times out and leaves the whole device hanging.

Catching the timeout and calling adiv5_dp_abort() seems to restore the
device to a useable state.

Tested on Seed LoRa-E5 (STM32E5JC).
2021-04-19 16:57:13 +02:00
Uwe Bonnes 58f153e12b cortexm: Always halt and release reset before romtable scan
Only release from halt once after romtable scan
Should fix #836.
2021-03-26 17:43:11 +01:00
Uwe Bonnes cfb784d428 adiv5: Fix comments and debug output 2021-03-05 16:49:19 +01:00
Uwe Bonnes 0df44e205b ADIv5: Abort Romtable scan also if CIDR0 is invalid after halting #832
STM32WLE5 has the same dual core chip as STM32WL5. For the second
core, the additional AP can be see, but access to e.g. CIDR0 for that
Romtable fails.
Aborting the scan too if again the second read of CIDR0 fails makes
sense anyways!
2021-02-19 18:48:02 +01:00
Uwe Bonnes 48a79ff9da adiv5: More checks for a sensible DPIDR. 2020-11-29 21:11:11 +01:00
Uwe Bonnes 752bc26536 adiv5: Fix memleak with duplicated base. 2020-11-29 21:11:11 +01:00
Uwe Bonnes f45c56af83 adiv5/swdp: Check early for valid DP idcode. 2020-11-29 15:48:50 +01:00
Uwe Bonnes 19e1fddba2 adiv5: Remove unnescessary read. 2020-11-27 22:26:48 +01:00
Uwe Bonnes cda83d3084 Fix memleaks.
Happened e.g. when Stlink could not enter debug or when cortexm_prepare timed out.
2020-11-27 22:26:48 +01:00
Uwe Bonnes 9ac5adfcef adiv5: Additional decoding. 2020-11-27 22:26:48 +01:00
Uwe Bonnes 1f7a716710 adiv5.c: Run cortexm_prepare on all suspected CortexM instances.
Gets all debug units of the second CPU of a STM32H745 visible.
2020-10-23 09:40:15 +02:00
Uwe Bonnes 18673d9a56 adiv5: Rework DP/AP refcounting.
ASAN non longer reports leaks with the STM32H745.
2020-10-23 09:40:15 +02:00
Uwe Bonnes f76a7c4e92 adiv5: Release devices after scan.
Before, scanning only kept device stopped until POR or attach/detach cycle.
2020-10-23 09:40:15 +02:00
Uwe Bonnes c161521c26 cortexm: Designer ARM must be in the default path when probing. 2020-10-23 09:40:15 +02:00
Uwe Bonnes cdd07544d5 Cortexm: Allow pure debug on devices not yet handled for flashing
- Recognize STM32L552 and MIMXRT10XX
- Fix another PIDR
- Fix bad debug print string.
2020-10-23 09:40:15 +02:00
Uwe Bonnes 0ffb4f7b18 cortexm: Fix protected SAM detection
- Only run cortex_prepare() if reading cidr fails
- With Atmel DSU detected, run cortexm_probe()
2020-10-17 12:49:37 +02:00
Uwe Bonnes 877b4be8ee cortexm: Restrict probing by using the ap_designer.
More designers need to be observed and reported by users and added.
Request users to send needed data.
2020-10-07 20:12:35 +02:00
Uwe Bonnes 44bfb62715 Adiv5: Print Designer/Partno when device is not recognized
t->idcode is now 16 bit.
2020-10-07 20:12:35 +02:00